JP2007299142A - MEMORY CONTROLLER, NONVOLATILE MEMORY DEVICE, NONVOLATILE MEMORY SYSTEM, AND DATA WRITE METHOD - Google Patents

Abstract

An optimum writing performance is obtained in accordance with the performance of a nonvolatile memory to be used.
A write rate (rate 3) to a memory cell array 112 is detected based on an ID code 114 of a nonvolatile memory 110 and adjusted so that rate 1 of a bus 1 is approximately equal to rate 3. Data is stored in the buffer 101 at a rate 1, and data is written from the buffer 101 to the nonvolatile memory 110 at a rate 1. Therefore, for example, in the case of a high-speed non-volatile memory with a rate 3 of 30 Mbyte / sec, the rate 1 is increased to the rate 3, and the non-volatile storage system has a high rate of 30 Mbyte / sec. On the other hand, in the case of a relatively low-speed nonvolatile memory with a rate 3 of 10 Mbytes / second, the rate 1 is lowered, so that the peak current of the memory controller 100 can be suppressed and noise can be reduced. Further, since the input / output rate with respect to the buffer 101 can be made equal, the capacity can be reduced.
[Selection] Figure 1

Description

  The present invention relates to a nonvolatile memory device such as a semiconductor memory card having a nonvolatile memory, and a memory controller built in the nonvolatile memory device. Furthermore, a nonvolatile storage system in which an access device is added to the nonvolatile storage device as a constituent element, and a data writing method relating to the operation of the memory controller are also included.

  The demand for a nonvolatile memory device including a rewritable nonvolatile memory is increasing as a semiconductor memory card as a central embodiment. Further, the demand for nonvolatile storage systems using semiconductor memory cards is increasing, especially in digital still cameras. There are various types of such semiconductor memory cards, and one of them is an SD (Secure Digital) memory card. This SD memory card includes a flash memory as a nonvolatile main storage memory and has a memory controller for controlling the flash memory. The memory controller performs read / write control on the flash memory in response to a read / write instruction from an access device such as a digital still camera or a personal computer (personal computer) main body.

  It is assumed that such an SD memory card is attached to an access device such as a digital still camera, and is regarded as a removable disk from the access device side and managed by the FAT file system to access data. The FAT file system is a system for instructing reading and writing of data using a file allocation table (hereinafter referred to as FAT) when recording a file or data on a recording device.

  The flash memory that constitutes the SD memory card requires a relatively long time for writing to and erasing from the memory cell array, which is a storage unit, so that a plurality of memory cells can be erased and written at once. Yes. Specifically, it is composed of a plurality of physical blocks (erase units), each physical block includes a plurality of pages (write units), erase is performed in units of physical blocks, and writing is performed in units of pages.

  In recent years, a variety of flash memories that can store 2-bit information in one memory cell, such as a multi-level NAND flash memory, has become mainstream in response to demands for large capacity and low cost. Such a multi-level NAND flash memory requires a longer time for erasing and writing of memory cells than a conventional binary NAND flash memory. Therefore, by increasing the size of the physical block that is the erase unit and the size of the page that is the write unit, the erase time per unit capacity (hereinafter referred to as the erase rate) and the write time per unit time ( Thereafter, a device has been devised to improve the writing rate. A typical multi-level NAND flash memory has a write rate of 2.5 Mbytes / second according to the following equation (hereinafter, equation 1).

2 kbytes (page size) ÷ 800 μsec (writing time) = 2.5 Mbyte / sec A data writing method of a typical nonvolatile memory system using an SD memory card having such a flash memory will be described with reference to FIG. To do.

  In FIG. 6, the access device 2000 writes data to the nonvolatile storage device 5000.

  In the SD memory card, the minimum writing unit is 512 bytes. However, for the sake of simplicity, it is assumed that a writing instruction for one cluster is issued from the access device 2000. The size of one cluster is 16 kbytes.

  The 16-kbyte data transferred from the access device 2000 is first received by the host interface 2001. When the host interface 2001 detects data reception, the host interface 2001 notifies the CPU unit 2007 that reception has started. The CPU 2007 sends an instruction to the switching circuit 2002 and the switching circuit 2005, and causes the switching circuit 2002 to perform switching so that data can be temporarily stored in the buffer 2003. At the same time, the switching circuit 2005 performs switching so that the data temporarily stored in the buffer 2004 can be written into the nonvolatile memory 4000 via the read / write control unit 2006. At this time, since the buffer 2004 is empty, data is not written to the nonvolatile memory 4000.

  Next, when the CPU 2007 detects that the host interface 2001 has received 2 kbytes of data and has temporarily stored 2 kbytes of data in the buffer 2003, it sends an instruction to the switching circuit 2002 and the switching circuit 2005 to switch Switching is performed so that the circuit 2002 can temporarily store data in the buffer 2004. At the same time, switching is performed so that the switching circuit 2005 can write data temporarily stored in the buffer 2003 to the nonvolatile memory 4000 via the read / write control unit 2006. At this time, since data of 2 kbytes is temporarily stored in the buffer 2003, the read / write control unit 2006 writes data to the nonvolatile memory 4000.

  The CPU 2007 determines the write destination (physical address) of the nonvolatile memory 4000 based on the logical address received from the access device 2000 and designates the physical address to the read / write controller 2006. The read / write control unit 2006 transfers the physical address designated by the CPU unit 2007 and data of 2 kbytes as a set to the nonvolatile memory 4000.

  In the nonvolatile memory 4000, the control circuit 4003 receives the physical address transferred from the read / write control unit 2006, and the control circuit 4003 designates a write destination to the physical address in the memory cell array 4002. Then, at the stage where all the data of 2 kbytes transferred from the read / write control unit 2006 are temporarily stored in the register 4001, the read / write control unit 2006 transfers a write start command to the nonvolatile memory 4000, and receives the control circuit 4003 Writes data from the register 4001 to the memory cell array 4002.

  As described above, the CPU section 2007 alternately switches between temporary storage and reading in the buffers 2003 and 2004, so that 16 kbytes of data can be received and written to the nonvolatile memory 4000 in a pipeline manner. .

  Here, the rates of the buses 1 to 3 will be described. The write rate of the bus 1 (hereinafter referred to as rate 1) is currently set at a maximum of 25 Mbytes / second in the physical standard of the SD memory card, but may be further improved in the future. The actual value of rate 1 varies depending on the type of access device. The write rate of bus 2 (hereinafter referred to as rate 2) varies depending on the design. For example, when an 8-bit bus type (16-bit bus type) flash memory is used and operated at a frequency of 20 MHz, 20 Mbyte / sec. The writing rate of the bus 3 (hereinafter referred to as rate 3) is determined by the writing time of the flash memory as described in Equation 1 above, and is, for example, 2.5 Mbytes / second. Thus, the write rate of the nonvolatile storage system is rate-limited at rate 3. However, since the flash memory has the following restrictions (A) and (B), the realistic write rate on the bus 3 is slower than the rate 3 (2.5 Mbyte / second).

(A) Overwriting is not possible (B) As described above, writing from an access device having a different erasing unit and writing unit includes rewriting, and considering the above constraints (A) and (B), The memory controller may cause processing other than writing, such as erasing the physical block of the writing destination before writing, or performing valid page saving processing when rewriting some pages of the physical block. Since these processes vary depending on the recording state of the flash memory, the realistic writing rate on the bus 3 cannot be uniquely determined as the rate 3.

  In any case, since the rate of the nonvolatile memory system shown in FIG. 6 is less than rate 3, in order to improve rate 3 and improve the writing rate of the nonvolatile memory system, the following ideas and efforts are made. Has been made.

(1) Parallel access of multiple non-volatile memories (2) Increase in register size (3) Development of high-speed non-volatile memories to replace flash memories (1) is a device already supported by actual products Since there is a limit to the number of non-volatile memories that can be mounted on the semiconductor memory card, it is difficult to increase the write rate of the non-volatile storage system to the level of rate 1 or rate 2. Further, (2) is not preferable because of the enormous number of registers and the cost of the nonvolatile memory. In (3), a so-called non-volatile RAM such as a resistance change memory as shown in Patent Document 1 has been developed, and is regarded as a promising alternative to a flash memory.

A nonvolatile memory typified by a resistance change memory is an overwritable nonvolatile memory, and can be accessed at a high speed of several tens of nanoseconds (n is nano). For example, if the writing unit is 33 nsec and the writing unit is 1 byte, the rate corresponding to the rate 3 is 30 Mbyte / sec, which is expected as a memory element that dramatically improves the rate of the nonvolatile storage system.
JP 2004-185754 A

  However, even when a high-speed memory such as the resistance change type memory is applied, in the above-described nonvolatile storage system (FIG. 6), there is a mechanism that can change the rate 1 and the rate 2 according to the performance of the nonvolatile memory. Therefore, the rate is limited to rate 2, and the performance of rate 3 cannot be achieved.

  Furthermore, since the flash memory has the constraints (A) and (B) as described above, the realistic write rate on the bus 3 cannot be defined as the rate 3, so the nonvolatile memory system can be defined according to the rate 3. There was little point in optimizing the rate.

  Therefore, in view of the above problems, the present invention provides a memory controller, a nonvolatile storage device, and a nonvolatile storage system that can provide the highest writing performance not limited to rate 1 or rate 2 according to the performance of the nonvolatile memory to be used. And a data writing method.

  In order to achieve the above object, the present invention takes the following technical means.

  That is, the technical means in the present invention is a memory controller that controls reading of data from a nonvolatile memory and writing of data transferred from the outside at a predetermined transfer rate (rate 1) to the nonvolatile memory. The memory controller temporarily stores the data before being written to the nonvolatile memory at the rate 1 and the memory cell array in the nonvolatile memory based on the ID code of the nonvolatile memory. Rate 3 detecting means for detecting the write rate (rate 3), read / write means for writing the data temporarily stored in the buffer to the nonvolatile memory at the rate 1, and rate 3 for notifying the rate 3 to the outside And a notification means.

  The size of the buffer is preferably a capacity in units of writing to the nonvolatile memory.

  More preferably, the non-volatile memory may be a non-volatile RAM represented by a resistance change memory, a ferroelectric memory, a magnetic recording type arbitrary write / read memory, and an ovonic unified memory.

  The technical means in the present invention controls the nonvolatile memory, the reading of data from the nonvolatile memory, and the writing of data transferred from the outside at a predetermined transfer rate (rate 1) to the nonvolatile memory. A non-volatile storage device having a memory controller, wherein the memory controller has a buffer for temporarily storing data before being written to the non-volatile memory at the rate 1 and the non-volatile memory Rate 3 detection means for detecting a write rate (rate 3) to the memory cell array in the nonvolatile memory based on the ID code, and writing / reading data temporarily stored in the buffer to the nonvolatile memory at the rate 1 And rate 3 notification means for notifying the rate 3 to the outside.

  The size of the buffer is preferably a capacity in units of writing to the nonvolatile memory.

  More preferably, the non-volatile memory may be a non-volatile RAM represented by a resistance change memory, a ferroelectric memory, a magnetic recording type arbitrary write / read memory, and an ovonic unified memory.

  The technical means in the present invention includes an access device, a nonvolatile memory, a memory controller that controls reading of data from the nonvolatile memory and writing of data transferred from the access device to the nonvolatile memory. The access device transfers data at a predetermined transfer rate (rate 1) to the memory controller to access the nonvolatile memory, and the memory controller A buffer that temporarily stores data before being written to the nonvolatile memory at the rate 1, and a writing rate (rate 3) to the memory cell array in the nonvolatile memory based on the ID code of the nonvolatile memory. Rate 3 detection means for detecting the data temporarily stored in the buffer; Read / write means for writing to the non-volatile memory at 1 and rate 3 notification means for notifying the access device of the rate 3 so that the access device can make the rate 1 substantially equal to the rate 3 It has the rate 1 adjustment means to adjust, It is characterized by the above-mentioned.

  The size of the buffer is preferably a capacity in units of writing to the nonvolatile memory.

  More preferably, the non-volatile memory may be a non-volatile RAM represented by a resistance change memory, a ferroelectric memory, a magnetic recording type arbitrary write / read memory, and an ovonic unified memory.

  The technical means in the present invention is a data writing method for writing data to a nonvolatile memory device comprising a nonvolatile memory and a buffer, and the data in the nonvolatile memory is based on an ID code of the nonvolatile memory. A write rate (rate 3) to the memory cell array is detected, a predetermined transfer rate (rate 1) to the buffer is adjusted to be approximately equal to the rate 3, and the data is temporarily transmitted at the rate 1. The data stored in the buffer and temporarily stored in the buffer is written to the nonvolatile memory at the rate 1.

  The size of the buffer is preferably a capacity in units of writing to the nonvolatile memory.

  More preferably, the non-volatile memory may be a non-volatile RAM represented by a resistance change memory, a ferroelectric memory, a magnetic recording type arbitrary write / read memory, and an ovonic unified memory.

  Needless to say, the rate is not a so-called speed information such as an access time (time) or a transfer frequency, but is defined as a parameter representing the amount of transfer information per unit time. If rate 1 or rate 3 is the speed information, the bit width of the path for receiving data from the outside or the access device is different from the bit width of the write path to the memory cell array in the nonvolatile memory. The amount of transfer information per unit time on the route cannot be adjusted to be approximately equal.

  According to the present invention, the write rate (rate 3) to the memory cell array in the nonvolatile memory is detected based on the ID code of the nonvolatile memory, and the transfer rate (rate 1) to the buffer is substantially equal to the rate 3. Since the data was temporarily stored in the buffer at rate 1 and the data temporarily stored in the buffer was written in the nonvolatile memory at rate 1, a high-speed nonvolatile memory was used. In this case, that is, when the rate 3 is higher than the rate 1, the rate 1 is increased to the rate 3, and the rate of the nonvolatile storage system becomes the rate 3. In other words, a high-speed system that does not control the rate 2 before adjustment is realized. it can. When a low-speed nonvolatile memory is used, that is, when the rate 3 is smaller than the rate 1, the rate 1 is lowered to the rate 3, and the peak current of the memory controller can be suppressed and the noise can be reduced.

  Furthermore, since temporary storage and reading to and from the buffer can be performed synchronously at a rate of 1, a circuit for adjusting the rate in the memory controller is unnecessary, and the buffer size can be reduced, thus realizing a low-cost system. can do. Further, the transfer rate of the nonvolatile memory from the memory controller is set to the same rate as the transfer rate from the access device (rate 1), and the rate 1 can be automatically adjusted according to the rate 3, so that the nonvolatile memory to be used is used. Therefore, it is not necessary to redesign the memory controller according to the type, and the development cost can be rationalized.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment)
FIG. 1 is a block diagram showing a method for implementing a nonvolatile memory system according to an embodiment of the present invention. The characteristic blocks of the present invention are a rate 3 detection unit 103, a rate 3 notification unit 104, an ID code 114, and a rate 1 adjustment unit 151.

  In FIG. 1, the nonvolatile storage system includes an access device 150 and a nonvolatile storage device 120, and the nonvolatile storage device 120 includes a memory controller 100 and a nonvolatile memory 110. The memory controller 100 includes a host interface 2001, a buffer 101, a read / write control unit 102, a rate 3 detection unit 103, a rate 3 notification unit 104, and a CPU unit 105.

  The size of the buffer 101 is the same as the size of the register 111 in the nonvolatile memory 110. Note that it may be larger than the size of the register 111.

  The read / write control unit 102 is a block for writing data temporarily stored in the buffer 101 to the nonvolatile memory 110 and reading data stored in the nonvolatile memory 110 to the buffer 101.

  The rate 3 detection unit 103 is a block that detects rate 3 as the rate of the bus 3 based on the ID code 114 held in the nonvolatile memory 110, and the rate 3 notification unit 104 is detected by the rate 3 detection unit 103. This register holds rate 3, and the access device 150 notifies the access device 150 of the rate 3 by referring to this register.

  The CPU unit 105 controls the entire memory controller 100 or generates a physical address of the nonvolatile memory 110 based on the logical address received from the access device 150, as with the CPU 2007 of the conventional nonvolatile system. is there.

  The nonvolatile memory 110 includes a memory cell array of a resistance change type memory disclosed in the cited Patent Document 1. It may be a ferroelectric memory, a magnetic recording type writing / reading memory, or an ovonic unified memory. These are collectively referred to as a nonvolatile RAM.

  The register 111 is a register capable of holding 1 byte of data. The memory cell array 112 is composed of a plurality of resistance change type memory cells. The control circuit 113 stores the data temporarily stored in the register 111 into the memory cell array. 112 is a circuit for writing to 112 and setting the physical address of the memory cell array 112. The ID code 114 is a code stored in a ROM or the like of the control circuit 113, and can identify the type of the nonvolatile memory 110. Note that the ID code 114 may be written in advance in a partial area in the memory cell array 112.

  The access device 150 includes at least a rate 1 adjustment unit 151. The rate 1 adjustment unit 151 is a block that controls the frequency of a transfer clock (hereinafter referred to as TCK) used during transfer of the access device 150 based on the rate 3 information read from the rate 3 notification unit 104.

  Other circuit blocks are the same as those of the conventional nonvolatile memory system.

  FIG. 2 is an explanatory diagram showing the configuration of the buffer 101. 2, 201 is a D flip-flop for latching data, and 202 is a latch control circuit that divides TCK and outputs a clock signal (hereinafter referred to as DCK) of the D flip-flop 201.

  FIG. 3 is a memory map showing a rate table included in the rate 3 detection unit 103.

  FIG. 4 is a flowchart showing the processing contents of the rate 1 adjustment unit 151.

  FIG. 5 is a time chart showing a state of temporary storage in the buffer 101.

  The nonvolatile memory system of the present invention configured as described above will be described separately in an initial state, an initialization process at power-on, and a data write process in normal operation.

[initial state]
First, the following two points are set as information set by the manufacturer before shipment.

(1) Information set in the nonvolatile memory 110 An ID code 114 for identifying the nonvolatile memory 110 is stored in the ROM in the control circuit 113. It may be stored in the memory cell array 112. Further, in the memory cell array 112, there are a system area in which system information such as security information is stored, and a normal area in which a user reads and writes data, but the description of the system information is omitted for the sake of simplification. Here, description will be made assuming that the entire area of the memory cell array 112 is a normal area.

(2) Information set in the rate 3 detection unit 103 The rate table (FIG. 3) included in the rate 3 detection unit 103 stores the write rate (rate 3) for each of various nonvolatile memories, and the ID code. Corresponding to 114, rate 3 can be referred to. The rate table is preferably generated in advance on the ROM.

[Initialization at power-on]
When the access device 150 is turned on, the nonvolatile storage device 120 is also turned on via the bus 1 and the nonvolatile storage device 120 shifts to an initialization process. In the initialization process, the CPU unit 105 reads the ID code 114 via the read / write control unit 102 and transfers it to the rate 3 detection unit 103. Next, the rate 3 detection unit 103 reads the rate 3 parameter corresponding to the ID code with reference to the built-in rate table (FIG. 3), and transfers it to the rate 3 notification unit 104. The rate 3 notification unit 104 holds a rate 3 parameter.

  The rate 1 adjustment unit 151 in the access device 150 calculates TCK according to the flowchart shown in FIG. In FIG. 4, it is first determined whether or not it is an initialization process (S400). If it is an initialization process, the rate 3 notification unit 104 is referred to (S401). Here, the correspondence relationship between the rate 3 parameter and the rate 3 held in the rate 3 notification unit 104 may be determined by the standard of the memory card or the like. Next, TCK is determined based on the bit width of the bus 1 of the access device 150 (hereinafter referred to as WBIT) and the following equation (hereinafter, equation 2) (S402). In this embodiment, WBIT is 4 bits.

TCK [Hz] = Rate 3 [Mbyte / sec] × (8 bits / WBIT)
In a conventional nonvolatile storage system using a flash memory as the nonvolatile memory 110, the guaranteed number of rewrites of the flash memory is relatively small at 10,000 times to 100,000 times, so that logical physics for wear leveling is performed. Although the conversion table or the like has to be created on the RAM in the memory controller, as shown in the embodiment of the present invention, in the nonvolatile memory system using the nonvolatile RAM such as the resistance change type memory, the resistance Since the guaranteed number of rewrites of the changeable memory is as large as 10 billion, there is no need to wear leveling. Therefore, it is not particularly necessary to create a conventional logical / physical address conversion table or the like and perform logical / physical address conversion processing. In the embodiment of the present invention, for simplicity, the logical address designated by the access device 150 is used as the physical address of the nonvolatile memory 110.

[Data write processing during normal operation]
A case will be described in which the access device 150 writes 512 bytes of data in a sector unit (512 bytes) which is the minimum writing unit. As the nonvolatile memory 110, a nonvolatile memory having an ID code of 0x8 (0x is a symbol representing a hexadecimal number), that is, a rate of 30 Mbytes / second is used (FIG. 3). In this case, in the initialization process, the CPU unit 105 reads the ID code 114 (value 0x8) from the non-volatile memory 110, and the rate 3 detection unit 103 refers to the built-in rate table (FIG. 3) and stores the ID code in the ID code. The corresponding rate 3 parameter (value 0x1e) is read and transferred to the rate 3 notification unit 104. The rate adjustment unit 151 in the access device 150 refers to the rate 3 notification unit 104 and transfers data with TCK set to 60 MHz based on the above-described Equation 2.

  In FIG. 5, the access device 150 transfers a write command (hereinafter referred to as WCMD) having a logical sector address in units of 512 bytes as an argument to the host interface 2001, and then transfers 512 bytes of data. The host interface 2001 notifies the CPU unit 105 that the write command has been received, and latches data internally at the rising edge of TCK. Note that 0L and 0U represent the lower 4 bits and the upper 4 bits of byte 0, respectively, and are latched in 8-bit units in which the lower 4 bits and the upper 4 bits are combined.

  The CPU unit 105 sets the reception flag to active (value 1) immediately after the host interface 2001 receives the WCMD, and starts writing data into the buffer 101.

  In FIG. 2, the latch control circuit 202 calculates a frequency division ratio based on Equation 3 shown below and divides TCK into DCK. Note that DBIT is the bit width of the D flip-flop 201 and is 8 bits in this embodiment. Therefore, the frequency division ratio is “2”. It is preferable that the bit width of the D flip-flop 201 corresponds to the size of the register 111.

Dividing ratio = DBIT (8 bits) / WBIT (4 bits)
Data is latched in the D flip-flop 201 at the rising edge of the DCK, and the data latched in the D flip-flop 201 and the DCK are transferred to the read / write control unit 102. In the data read / write control unit 102, the data latched in the D flip-flop 201 is fetched at the falling edge of DCK while the write enable flag is active (value 1), and is stored in the nonvolatile memory 110 via the bus 2. Write to register 111. At the same time, the CPU unit 105 transfers a logical byte address obtained by dividing the logical sector address received from the access device 150 into byte units to the control circuit 113, and immediately after that, the read / write control unit 102 instructs a write start instruction, One byte of data is written from the register 111 to the memory cell array 112. The write enable flag is a flag generated when the latch control circuit 202 latches the reception flag described above twice at the rising edge of DCK. In this way, 512 bytes of data are written to the nonvolatile memory 110 via the buffer 102 and the read / write controller 102.

  As described above, the nonvolatile memory system according to the embodiment of the present invention detects the write rate (rate 3) to the memory cell array 112 in the nonvolatile memory 110 based on the ID code 114 included in the nonvolatile memory 110, and The rate 1 is adjusted so that the rate at which the access device 150 transfers data and the rate at which the data is transferred from the buffer 101 to the nonvolatile memory 110 are approximately rate 3. Therefore, for example, when a high-speed nonvolatile memory having a rate of 30 Mbyte / second is used, the rate 1 is increased to a high rate of 30 Mbyte / second, and the rate of the nonvolatile storage system is a high rate of 30 Mbyte / second. It becomes. On the other hand, for example, when a relatively low-speed non-volatile memory having a rate of 10 Mbytes / second is used, the rate 1 is lowered to a low rate of 10 Mbytes / second, thereby suppressing the peak current of the memory controller and reducing noise. Can be realized. Further, the rate at which the access device 150 transfers data and the rate at which data is transferred from the buffer 101 to the nonvolatile memory 110 can be made equal, in other words, the rate adjustment in the buffer 101 becomes unnecessary, so the capacity of the buffer 101 is reduced and D This can be realized with a small circuit such as the flip-flop 201.

  In the embodiment of the present invention, the resistance change type memory is used as the nonvolatile memory 110. However, other nonvolatile memories may be used. The register 111 is in units of bytes, but may be a unit of capacity convenient for the nonvolatile memory, such as 2 bytes or 4 bytes. Also, the buffer 101 need not be in units of bytes, but may be in other units of capacity. However, it is preferable to match the size of the register. The rate 1 adjustment unit 151 refers to the rate 3 parameter held by the rate 3 notification unit 104. However, the rate 1 adjustment unit 151 transmits the rate 3 parameter to the access device 150 from the rate 3 notification unit 104 side. It doesn't matter. Further, although the rate 3 notification unit 104 is a register that can hold the rate 3 parameter, the rate 3 parameter may be stored in a partial area of the memory cell array 112 and the access device 150 may refer to it. Absent.

  The nonvolatile memory system according to the present invention proposes a system and a writing method capable of high-speed writing in a nonvolatile memory device using a high-speed memory device such as a resistance change type memory. This is useful in a still image recording / reproducing device, a moving image recording / reproducing device, a cellular phone, etc.

The block diagram which shows the implementation method of the non-volatile storage system in embodiment of this invention The block diagram which shows the structure of the buffer of the non-volatile storage system Schematic diagram showing a rate table included in the rate 3 detector of the nonvolatile storage system The flowchart which shows the processing content of the rate 1 adjustment part of the non-volatile storage system Time chart showing the state of temporary storage in the buffer of the nonvolatile storage system A block diagram showing an implementation method of a conventional nonvolatile storage system

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Memory controller 101 Buffer 102 Reading / writing control part 103 Rate 3 detection part 104 Rate 3 notification part 105 CPU part 110 Non-volatile memory 111 Register 112 Memory cell array 113 Control circuit 114 ID code 120 Non-volatile memory device 150 Access apparatus 151 Rate 1 adjustment part 201 D flip-flop 202 Latch control circuit 2000 Access device 2001 Host interface 2002, 2005 Switching circuit 2003, 2004 Buffer 2006 Read / write control unit 3000 Memory controller 4000 Non-volatile memory 4001 Register 4002 Memory cell array 4003 Control circuit 5000 Non-volatile storage device

Claims (12)

A memory controller that controls reading of data from a nonvolatile memory and writing of data transferred from the outside at a predetermined transfer rate (rate 1) to the nonvolatile memory,
The memory controller is
A buffer that temporarily stores data before being written to the nonvolatile memory at the rate 1;
Rate 3 detection means for detecting a write rate (rate 3) to a memory cell array in the nonvolatile memory based on an ID code of the nonvolatile memory;
Read / write means for writing the data temporarily stored in the buffer to the nonvolatile memory at the rate 1;
Rate 3 notification means for notifying the rate 3 to the outside;
A memory controller. The memory controller according to claim 1, wherein the size of the buffer is a capacity of a unit of writing to the nonvolatile memory. The nonvolatile memory is a nonvolatile RAM, and includes any one of a resistance change type memory, a ferroelectric memory, a magnetic recording type arbitrary write / read memory, and an ovonic unified memory. The memory controller according to claim 1 or 2. Nonvolatile memory having a nonvolatile memory and a memory controller that controls reading of data from the nonvolatile memory and writing of data transferred from the outside at a predetermined transfer rate (rate 1) to the nonvolatile memory A device,
The memory controller is
A buffer that temporarily stores data before being written to the nonvolatile memory at the rate 1;
Rate 3 detection means for detecting a write rate (rate 3) to a memory cell array in the nonvolatile memory based on an ID code of the nonvolatile memory;
Read / write means for writing the data temporarily stored in the buffer to the nonvolatile memory at the rate 1;
Rate 3 notification means for notifying the rate 3 to the outside;
A non-volatile storage device comprising: The nonvolatile memory device according to claim 4, wherein the size of the buffer is a capacity of a unit of writing to the nonvolatile memory. The nonvolatile memory is a nonvolatile RAM, and includes any one of a resistance change type memory, a ferroelectric memory, a magnetic recording type arbitrary write / read memory, and an ovonic unified memory. The nonvolatile memory device according to claim 4 or 5. A non-volatile storage system having an access device, a non-volatile memory, and a memory controller that controls reading of data from the non-volatile memory and writing of data transferred from the access device to the non-volatile memory. And
The access device transfers data at a predetermined transfer rate (rate 1) to the memory controller to access the nonvolatile memory,
The memory controller is
A buffer that temporarily stores data before being written to the nonvolatile memory at the rate 1;
Rate 3 detection means for detecting a write rate (rate 3) to a memory cell array in the nonvolatile memory based on an ID code of the nonvolatile memory;
Read / write means for writing the data temporarily stored in the buffer to the nonvolatile memory at the rate 1;
Rate 3 notification means for notifying the access device of the rate 3;
The non-volatile storage system according to claim 1, wherein the access device includes rate 1 adjusting means for adjusting the rate 1 so as to be approximately equal to the rate 3. The nonvolatile memory system according to claim 7, wherein the size of the buffer is a capacity of a unit of writing to the nonvolatile memory. The nonvolatile memory is a nonvolatile RAM, and includes any one of a resistance change type memory, a ferroelectric memory, a magnetic recording type arbitrary write / read memory, and an ovonic unified memory. The nonvolatile memory system according to claim 7 or 8. A data writing method for writing data to a nonvolatile storage device comprising a nonvolatile memory and a buffer,
Based on the ID code of the non-volatile memory, a write rate (rate 3) to the memory cell array in the non-volatile memory is detected,
Adjusting the predetermined transfer rate (rate 1) to the buffer to be approximately equal to the rate 3;
Temporarily storing the data at the rate 1 in the buffer;
A data writing method for writing data temporarily stored in the buffer to the nonvolatile memory at the rate 1. The data writing method according to claim 10, wherein the size of the buffer is a capacity of a unit of writing to the nonvolatile memory. The nonvolatile memory is a nonvolatile RAM, and includes any one of a resistance change type memory, a ferroelectric memory, a magnetic recording type arbitrary write / read memory, and an ovonic unified memory. The data writing method according to claim 10 or 11.

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