JP2007280608A - Semiconductor memory device - Google Patents

Abstract

The power consumption of a refresh operation is reduced, and the power consumption in a power-down state is greatly reduced.
A semiconductor memory device that needs to be periodically refreshed to hold memory cells, wherein a first refresh mode for refreshing all memory cells and at least some memory cells are refreshed. A refresh address register 61b for storing address information of a memory cell to be refreshed in the second refresh mode, wherein the refresh address register is an address of a cell serving as a starting point of refresh Information 611 and refresh command occurrence count 613 are held.
[Selection] Figure 6

Description

  The present invention relates to a semiconductor memory device, and more particularly, to a dynamic semiconductor memory device that requires a periodic refresh operation for memory retention of memory cells.

  In recent years, dynamic semiconductor memory devices such as DRAMs (Dynamic Random Access Memory) have been highly integrated and increased in capacity with the progress of semiconductor manufacturing technology. In such a semiconductor memory device, the refresh operation in the active state is performed based on an external refresh command input, and the refresh operation in the power-down state generates a clock by an internal oscillator or the like in the device. In addition, the address of the memory cell to be refreshed is automatically generated by a refresh address counter provided in the device. There is a demand for providing a semiconductor memory device that can further reduce the power consumption of the refresh operation (self-refresh operation) of such a dynamic semiconductor memory device.

  FIG. 1 is a block diagram showing an example of a conventional semiconductor memory device, showing the configuration of a refresh circuit of a synchronous DRAM (SDRAM). In FIG. 1, reference numeral 101 is a clock buffer (CLK buffer), 102 is a command decoder, 103 is an address buffer, 104 is a refresh control circuit, 105 is an oscillator (OSC), and 106 is a mode register. Reference numeral 107 is a refresh address counter, 108 is a RAS control circuit, 109 is a DRAM core, 110 is a selector, and 111 is an address latch.

  In the conventional SDRAM (semiconductor memory device) shown in FIG. 1, when an external refresh command (AUTO REFRESH) is input, a refresh command signal AR 1 is input from the command decoder 102 to the refresh control circuit 104 in the active state. The refresh control circuit 104 generates a refresh control signal REF1 based on the refresh command signal AR1. Here, chip select signal / CS, row address strobe signal / RAS, column address strobe signal / CAS, and write enable signal / WE are input to command decoder 102, and clock CLK The clock enable signal CKE is input, and the address buffer 103 receives address signals A0 to Ak. The refresh command (AUTO REFRESH) is given from the outside as a combination of, for example, a clock enable signal CKE and a row address strobe signal / RAS.

  The refresh address counter 107 is configured as a counter that counts up one address when the refresh control signal REF1 is input once, and automatically generates the refresh address ADR1 every time the refresh control signal REF1 is input. The refresh control signal REF1 is also supplied to the selector 110. When the refresh control signal REF1 is input, the selector 110 selects the refresh address ADR1 that is the output of the refresh address counter 107, and in other cases When the refresh control signal REF1 is not input, the external address AD1, which is the output of the address buffer 103, is selected and transmitted to the address latch 111, respectively.

  The refresh control signal REF1 is also supplied to the RAS control circuit 108, and refreshes the memory cells connected to the word line of the DRAM core 109 selected by the output of the address latch 111. In order to hold the memory of all the memory cells in the DRAM core 109, a refresh command is input a predetermined number of times within a predetermined time, and the refresh operation is repeated.

  On the other hand, in the power-down state, first, when a self-refresh command (SELF REFRESH) is supplied from the outside in the active state, the command decoder 102 generates a self-refresh command signal SR1, and the device (semiconductor memory device) is in the power-down state. become. Self refresh is a power-down mode in which the refresh operation is continued.

  The refresh control circuit 104 starts the oscillator (OSC) 105 by the control signal SR2 when the self-refresh command signal SR1 is input, and periodically generates the refresh control signal REF1 based on the clock signal generated by the oscillator 105. Note that the operations of the selector 110, the RAS control circuit 108, and the like are the same as the refresh operation in the above-described active state, and a description thereof will be omitted.

  The mode register 106 receives the output of the command decoder 102 and the output of the address buffer 103, and holds, for example, the burst length in the SDRAM burst mode, the latency from when the command is input to when the data is output, and the like.

  As described above, the conventional dynamic semiconductor memory device (SDRAM) refreshes all the memory cells in the DRAM core 109 in both the refresh operation in the active state and the refresh operation in the power down state.

  By the way, depending on the application, even if there is a lot of information that is temporarily handled, there is a small amount of information that needs to be stored continuously. Therefore, some memory cells in the DRAM core 109 are in a power-down state. There are many cases where it is sufficient to store only the data. Specifically, in a battery-powered portable terminal device (for example, a mobile phone), if only a part of data is kept in a state in which the power is turned on, it is not necessary to keep all other information. There is something good.

  However, in the conventional dynamic semiconductor memory device, since all the memory cells in the DRAM core 109 are refreshed, it is possible to further reduce the power consumption during power down (for example, about several hundred μA). It was difficult. In particular, in a portable terminal device or the like used by battery driving, for example, power consumption during power down directly affects the continuous standby time. Therefore, it is very important to reduce power consumption. The demand for power consumption reduction is required not only for battery-driven portable terminal devices but also for various other devices that use dynamic semiconductor memory devices.

  An object of the present invention is to reduce the power consumption of the refresh operation by refreshing only a necessary region in view of the problems of the above-described conventional semiconductor memory device, and to greatly reduce the power consumption in the power-down state. And

  According to the first aspect of the present invention, there is provided a semiconductor memory device that needs to be refreshed periodically for memory retention of memory cells, and has at least one refresh mode that refreshes all memory cells. And a refresh address register for storing address information of a memory cell to be refreshed in the second refresh mode, wherein the refresh address register There is provided a semiconductor memory device characterized by retaining address information of a cell as a starting point and information on the number of occurrences of a refresh command.

  According to the second aspect of the present invention, there is provided a semiconductor memory device that needs to be refreshed periodically for storage retention of memory cells, and at least one refresh mode for refreshing all memory cells. A second refresh mode for refreshing a portion of memory cells, a refresh address register for storing address information of a memory cell to be refreshed in the second refresh mode, a refresh address counter for generating a refresh address, A comparator for comparing a refresh address and information stored in the refresh address register, and refreshing each refresh address generated by the refresh address counter in the first refresh mode; Serial in the second refresh mode, a semiconductor memory device and performs the refresh according to the comparison result of the comparator is provided.

  According to the third aspect of the present invention, there is provided a semiconductor memory device that needs to be refreshed periodically for memory retention of memory cells, and has at least one refresh mode that refreshes all memory cells. A second refresh mode for refreshing a portion of the memory cells, a refresh address register for storing address information of a memory cell to be refreshed in the second refresh mode, and a refresh address counter for generating a refresh address In each of the first and second refresh modes, refresh is performed on each refresh address generated by the refresh address counter. In the second refresh mode, information stored in the refresh address register is provided. Therefore the semiconductor memory device, characterized in that to limit the counting range of the refresh address counter is provided.

  According to the semiconductor memory device of the present invention, since the second refresh mode for refreshing at least some of the memory cells is provided, only a necessary region can be refreshed to reduce the power consumption of the refresh operation. .

  In the semiconductor memory device according to the present invention described above, the refresh address register can be provided as part of the mode register, and the refresh address register and the mode register can be configured as the same register. Further, the information stored in the refresh address register may be the minimum value, the maximum value, or both the minimum value and the maximum value of the address range to be refreshed in the second refresh mode. Furthermore, the information stored in the refresh address register is the number of refresh operations for refreshing all memory cells to be refreshed in the second refresh mode, the initial value of the refresh address counter, or the refresh target. Both the number of refresh operations for refreshing all memory cells and the initial value of the refresh address counter may be used. Note that the initial value of the refresh address counter may be the minimum value or the maximum value of the range of addresses to be refreshed.

  The semiconductor memory device of the present invention includes a plurality of memory cell blocks, and the information stored in the refresh address register may be address information for selecting a memory cell block to be refreshed in the second refresh mode. . Furthermore, the semiconductor memory device of the present invention includes a plurality of memory cell blocks, and the information stored in the refresh address register is address information for selecting a memory cell block to be refreshed in the second refresh mode. There may be. Note that the refresh address generator may include a selector.

  The first refresh mode may be refreshed in synchronization with an external timing signal, and the second refresh mode may be refreshed in synchronization with an internally generated clock. Furthermore, the frequency of the refresh operation in the second refresh mode may be changed according to the number of memory cells to be refreshed set in the refresh address register. The second refresh mode may be a mode for performing self refresh of the memory cells in the power-down state.

  According to the semiconductor memory device of the present invention, it is possible to reduce the power consumption in the refresh operation by refreshing only the necessary area for holding data, and to greatly reduce the power consumption in the power-down state.

  Embodiments of a semiconductor memory device according to the present invention will be described below in detail with reference to the drawings.

  FIG. 2 is a block diagram showing a first embodiment of the semiconductor memory device according to the present invention, and shows a configuration of a refresh circuit of a synchronous DRAM (SDRAM). In FIG. 2, reference numeral 1 is a clock buffer (CLK buffer), 2 is a command decoder, 3 is an address buffer, 4 is a refresh control circuit, 5 is an oscillator (OSC), and 6 is a mode register. Reference numeral 7 is a refresh address counter, 8 is a RAS control circuit, 9 is a DRAM core, 10 is a selector, 11 is an address latch, 12 is a comparator, and 13 is an AND gate.

  As is apparent from a comparison between the semiconductor memory device of the first embodiment of the present invention shown in FIG. 2 and the conventional semiconductor memory device of FIG. 1, the first embodiment is different from the conventional example of FIG. A refresh address register 61, a comparator 12, and an AND gate 13 provided in the mode register 6 are added.

  That is, in the SDRAM (semiconductor memory device) of the first embodiment shown in FIG. 2, the refresh address register 61 contains the minimum value and the maximum value of the address range of the memory cell to be self-refreshed (or the self-refresh target). The block selection address of the memory cell block in the DRAM core 9 is stored. The minimum value and the maximum value stored in the refresh address register 61 are supplied to the comparator 12 and compared with the output ADR1 of the refresh address counter. In the first embodiment, the refresh address register 61 is configured as the same register as the mode register 6 (provided in the mode register 6). For example, when the mode register is set after power-on, an external command signal ( / CS, / RAS, / CAS, / WE) and address signals (A0-Ak), but are created by masks at the chip manufacturing stage, programmed by laser fuse, or wire bonding It is also possible to change the setting depending on the difference.

  The comparator 12 compares the refresh address ADR1 generated by the refresh address counter 7 with the contents of the refresh address register 61 (the minimum value and the maximum value of the address of the memory cell to be self-refreshed), and if they match (the self-refresh target When the address is detected), the output signal CMP is set to a high level “H”. In the self-refresh mode, the self-refresh control signal SR2 is activated to compare the addresses, and in the self-refresh mode, the address is compared. In other cases, the output CMP is fixed to a low level “L”.

  FIG. 3 is a diagram for explaining a self-refresh operation in the semiconductor memory device of FIG.

  As shown in FIG. 3, the comparator 12 includes a refresh address ADR1 generated by the refresh address counter 7 with the minimum value Am and the maximum value An of the address of the memory cell to be self-refreshed held in the refresh address register 61. Compared with (A0-Ak), the output signal CMP is set to the high level “H” in the matching address range Am-An, and self-refreshing is performed. The self-refresh is not performed at the low level “L”.

  That is, the refresh control signal REF2, which is the output of the refresh control circuit 4, is generated as the refresh control signal REF1 when the input signal (output signal of the comparator 12) CMP of the AND gate is at a high level “H”. Self refresh is performed only in the address range Am to An of the memory cell that is supplied to the selector 10 and is held in the refresh address register 61 and that is the target of self refresh.

  In the active state, the refresh command signal AR1 is refreshed from the command decoder 2 when an external refresh command (AUTO REFRESH) is input, as in the conventional semiconductor memory device described with reference to FIG. Input to the control circuit 4, the refresh control circuit 4 generates a refresh control signal REF2 based on the refresh command signal AR1. Here, chip select signal / CS, row address strobe signal / RAS, column address strobe signal / CAS, and write enable signal / WE are input to command decoder 2, and clock buffer CLK is input to CLK buffer 1. The clock enable signal CKE is input, and the address buffer 3 receives the address signals A0 to Ak. The refresh command (AUTO REFRESH) is given from the outside as a combination of, for example, a clock enable signal CKE and a row address strobe signal / RAS.

  The refresh address counter 7 is configured as a counter that increments one address when the refresh control signal REF2 is input once, and automatically generates the refresh address ADR1 every time the refresh control signal REF2 is input. The refresh control signal REF2 is also supplied to the AND gate 13, and the refresh control signal REF1 is supplied to the RAS control circuit 8 and the selector 10 by taking a logical product with the output CMP of the comparator 12. Here, the output CMP of the comparator 12 is fixed to the low level “L” except during the self-refresh.

  In the power-down state, when a self-refresh command (SELF REFRESH) is supplied from the outside in the active state, the command decoder 2 generates a self-refresh command signal SR1 and the device enters the power-down state, and the refresh control circuit 4 Starts the oscillator (OSC) 5 by the control signal SR2, and periodically generates the refresh control signal REF2 supplied to the refresh address counter 7 and the AND gate 13 based on the clock signal generated by the oscillator 5.

  Further, the refresh control signal REF1 is supplied to the selector 10, and when the refresh control signal REF1 is input, the refresh address ADR1 that is the output of the refresh address counter 7 is selected, and in other cases (refresh control signal REF1 Is not input), the external address AD1 which is the output of the address buffer 3 is selected and transmitted to the address latch 11 respectively. The refresh control signal REF1 is also supplied to the RAS control circuit 8 to refresh the memory cells connected to the word line of the DRAM core 9 selected by the output of the address latch 11. .

  According to the first embodiment of the present invention, the address information of the memory cell to be refreshed at the time of power-down is set in the refresh address register 61 from the outside, so that the refresh address register 61 designates the self-refresh. Only when an address within the range is generated from the refresh address counter 7 (only an area where data retention is necessary) can be refreshed to reduce the power consumption of the refresh operation.

  FIG. 4 is a block diagram showing a second embodiment of the semiconductor memory device according to the present invention, and FIG. 5 is a diagram for explaining a self-refresh operation in the semiconductor memory device of FIG.

  The second embodiment shown in FIG. 4 further reduces power consumption by limiting the operation of the refresh address counter 7 (7a), which was always operating in the first embodiment shown in FIG. Is. In FIG. 4, reference numeral 6a is a mode register, 61a is a refresh address register, 611 is a register for storing the minimum value of the refresh address, 612 is a register for storing the maximum value of the refresh address, 7a is a refresh address counter, and 12a is a comparison. And 121 indicates an OR gate.

  As shown in FIG. 4, in the second embodiment, the minimum value (611) of the refresh address held in the refresh address register 61a is supplied to the refresh address counter 7a as it is and also held in the refresh address register 61a. The maximum value (612) of the refresh address thus supplied is supplied to the comparator 12a. The output signal CMP of the comparator 12a and the self-refresh control signal SR3 which is the output of the refresh control circuit 4 are ORed by the OR gate 121 and supplied to the refresh address counter 7a as the set signal SET.

  In the second embodiment, when the self-refresh mode is entered, first, the self-refresh control signal (pulse signal) SR3 is output (one generation), and the set signal SET is input to the refresh address counter 7a via the OR gate 121. The minimum value (611: Am) of the refresh address held in the refresh address register 61a is set as an initial value in the refresh address counter 7a. Next, self-refreshing is started, and refresh operations are sequentially performed from the address Am. When the refresh address ADR1 output from the refresh address counter 7a reaches the maximum value (612: An) of the refresh address held in the refresh address register 61a, the comparator 12a outputs an output signal (pulse signal) CMP ( 1 occurrence). This signal CMP is input to the refresh address counter 7a as the set signal SET via the OR gate 121, the initial value (Am) is reset in the refresh address counter 7a, and the same operation is repeated thereafter. As a result, the refresh address counter 7a operates only within the address range (Am to An) set in the refresh address register 61a.

  In the second embodiment, the refresh address register 61a holds the minimum value Am (611) and the maximum value An (612) of the address of the memory cell to be self-refreshed. Alternatively, only the minimum value Am or the maximum value An may be held. That is, when only the minimum value Am (611) is stored in the refresh address register 61a, the addresses Am to Ak are subject to self-refresh, and only the maximum value An (612) is stored in the refresh address register 61a. Is stored, addresses A0 to An are subject to self-refresh.

  In the refresh operation in the active state, since the self-refresh control signal SR3 and the output signal CMP of the comparator 12a are not output, the refresh address counter 7a generates an address for refreshing all the memory cells in the DRAM core 9. become.

  FIG. 6 is a block diagram showing a third embodiment of the semiconductor memory device according to the present invention. In FIG. 6, reference numeral 6b is a mode register, 61b is a refresh address register, 611 is a register for storing the minimum value of the refresh address, 613 is a register for storing the number of refreshes, 12b is a comparator, and 122 is a counter. ing.

  In the third embodiment shown in FIG. 6, the number of refreshes (613) is used instead of the maximum value (612) of the refresh address held in the refresh address register 61 (61a) in the first and second embodiments described above. It is intended to be stored.

  That is, as shown in FIG. 6, in the third embodiment, the refresh address register 61b stores the minimum value of the refresh address (611: Am) and the number of refreshes (613). The counter 122 counts the number of refreshes (613).

  That is, in the third embodiment, in the self-refresh mode, the refresh address counter 7 counts up to generate the refresh address ADR1, and the comparator 12b has the refresh address ADR1 and the minimum value (611 of the refresh address). : Am) and if it matches, the output signal CMP is generated. The counter 122 receives the signal CMP, generates a high level “H” output signal C1, and starts counting the number of times the refresh control signal REF2 that is the output of the refresh control circuit 4 is generated. If it matches the information (613), the signal C1 is lowered to a low level “L”. Thus, the signal REF2 is supplied to the RAS control circuit 8 and the selector 10 as the refresh control signal REF1 only during the period when the signal C1 is at the high level “H”. The other configuration is the same as that of the first embodiment of FIG.

  The refresh address register 61b is configured to store the maximum value instead of the minimum value (611) of the refresh address, and the self-refresh is performed for a predetermined number of refresh times (613) from the maximum value of the refresh address. It can also be configured to do.

  FIG. 7 is a block diagram showing a fourth embodiment of the semiconductor memory device according to the present invention. In the fourth embodiment shown in FIG. 7, the block address in the DRAM core 9 to be refreshed is stored in the refresh address register 61c of the mode register 6c.

  For example, when the DRAM core 9 is composed of a plurality of memory cell blocks, it is effective to self-refresh only a part of the memory cell blocks of the DRAM core 9. The refresh address register 61c stores the block selection address to be self-refreshed, and the refresh address counter 7b uses the upper bit HB used for block selection and the lower bit used for word line selection within the block. The output is divided into bits LB.

  That is, the selector 14 selects the block selection address of the refresh address register 61c in the self-refresh mode by the self-refresh control signal SR2 from the refresh control circuit 4, and supplies it to the selector 10, otherwise, the selector 14 is higher in the refresh address counter 7b. The bit HB is selected and supplied to the selector 10.

  Here, in the first to fourth embodiments of the present invention described above, the number of memory cells to be self-refreshed is variable by setting the refresh address register 61 (61a, 61b, 61c). That is, in the first embodiment and the second embodiment, it can be changed by setting the minimum value and the maximum value. In the third embodiment, the number of times may be changed, and in the fourth embodiment, refresh is performed. It suffices if a plurality of target block addresses can be set.

  Further, each memory cell to be self-refreshed needs to be refreshed once within a predetermined time. In the first and third embodiments, the refresh address counter 7 is set to a predetermined value in the self-refresh mode. The oscillator 5 may be designed so as to make a round in time. However, in the second and fourth embodiments, if the number of memory cells to be self-refreshed increases, the self-refresh is performed for a specific memory cell. The time interval at which refresh is performed becomes long. Therefore, when the number of memory cells to be self-refreshed increases, the frequency of generation of the refresh control signal REF1 is increased (when the number of memory cells to be self-refreshed decreases, the refresh control signal REF1 To reduce the frequency of occurrence). An embodiment corresponding to this (fifth embodiment) is shown in FIG.

  FIG. 8 is a block diagram showing a fifth embodiment of the semiconductor memory device according to the present invention. Reference numeral 51 indicates a frequency divider.

  As shown in FIG. 8, in the fifth embodiment, the output of the oscillator 5 is frequency-divided by the frequency divider 51 and supplied to the refresh control circuit 4. The refresh address register 61c stores information on the number of memory cell blocks to be self-refreshed, and the frequency division ratio of the frequency divider 51 is changed accordingly. Specifically, for example, when the number of memory cell blocks to be self-refreshed is 4, 2, and 1, the output (frequency) of the frequency divider 51 is based on the case where the number of memory cell blocks is 4. Assuming (1 times), when the number of memory cell blocks is two and one, they are set to be 1/2 times and 1/4 times the reference frequency, respectively. As a result, it is possible to further reduce the power consumption by driving the refresh address counter 7 and the like at the necessary minimum frequency.

  In the above description, a DRAM (SDRAM) has been described as an example of a semiconductor memory device. However, the present invention provides a periodic refresh operation for storing and storing memory cells such as a sync link DRAM and a Rambus DRAM (RDRAM). The present invention can also be applied to other various semiconductor memory devices that require the above.

It is a block diagram which shows an example of the conventional semiconductor memory device. 1 is a block diagram showing a first embodiment of a semiconductor memory device according to the present invention. FIG. 3 is a diagram for explaining a self-refresh operation in the semiconductor memory device of FIG. 2. It is a block diagram which shows the 2nd Example of the semiconductor memory device based on this invention. FIG. 5 is a diagram for explaining a self-refresh operation in the semiconductor memory device of FIG. 4. It is a block diagram which shows the 3rd Example of the semiconductor memory device based on this invention. It is a block diagram which shows 4th Example of the semiconductor memory device based on this invention. It is a block diagram which shows 5th Example of the semiconductor memory device based on this invention.

Explanation of symbols

1 Clock buffer (CLK buffer)
2 Command decoder 3 Address buffer 4 Refresh control circuit 5 Oscillator (OSC)
6, 6a, 6b, 6c, 6d Mode register 7, 7a, 7b Refresh address counter 8 RAS control circuit 9 DRAM core 10, 14 selector 11 Address latch 12, 12a, 12b Comparator 13 AND gate 51 Divider 61, 61a, 61b, 61c, 61d Refresh address register 121 OR gate 122 counter

Claims (6)

A semiconductor memory device that needs to be refreshed periodically for memory retention of a memory cell,
A first refresh mode for refreshing all memory cells;
A second refresh mode for refreshing at least some of the memory cells;
A refresh address register for storing address information of a memory cell to be refreshed in the second refresh mode,
2. The semiconductor memory device according to claim 1, wherein the refresh address register holds address information of a cell serving as a starting point of refresh and information on the number of occurrences of a refresh command. A semiconductor memory device that needs to be refreshed periodically for memory retention of a memory cell,
A first refresh mode for refreshing all memory cells;
A second refresh mode for refreshing at least some of the memory cells;
A refresh address register for storing address information of a memory cell to be refreshed in the second refresh mode;
A refresh address counter for generating a refresh address;
A comparator for comparing the refresh address and the information stored in the refresh address register,
In the first refresh mode, refresh is performed for each refresh address generated by the refresh address counter,
In the second refresh mode, the semiconductor memory device performs refresh according to the comparison result of the comparator. A semiconductor memory device that needs to be refreshed periodically for memory retention of a memory cell,
A first refresh mode for refreshing all memory cells;
A second refresh mode for refreshing at least some of the memory cells;
A refresh address register for storing address information of a memory cell to be refreshed in the second refresh mode;
A refresh address counter for generating a refresh address,
In the first and second refresh modes, refresh is performed for each refresh address generated by the refresh address counter,
In the second refresh mode, the count range of the refresh address counter is limited according to information stored in the refresh address register. The semiconductor memory device according to claim 2 or 3,
A refresh address generator includes a selector that selectively outputs an output of the address counter excluding the part and information stored in the refresh address register according to a refresh mode. Storage device. The semiconductor memory device according to any one of claims 2 to 4,
A part of the output of the refresh address counter is a low-order bit. The semiconductor memory device according to claim 1,
The second refresh mode is a mode for executing a self-refresh operation in a power-down state of the semiconductor memory device.

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