JP2007273490A - Manufacturing method of semiconductor integrated circuit device - Google Patents

Abstract

A technique capable of improving the uniformity of the film thickness distribution in a wafer surface of a film formed by a sputtering method is provided.
A main body 116 of a collimator 115 is gradually thinned from a central portion to a peripheral portion, and an aspect ratio of a large number of control holes 117 provided in the main body 116 is continuously reduced from the center to the outer side of the collimator 115. After this collimator 115 is installed between the wafer and the target, a cobalt film having a thickness of about 10 nm is deposited on the wafer heated to 300 ° C. or higher, and then a silicon nitride film is deposited on the cobalt film. Then, a cobalt disilicide layer is formed by a silicide reaction.
[Selection] Figure 5

Description

  The present invention relates to a manufacturing technique of a semiconductor integrated circuit device, and more particularly to a technique effective when applied to a salicide (SALICIDE: Self Aligned Silicide) process using a metal film formed by a sputtering method.

Cobalt is silicified at the interface between cobalt and silicon by depositing while heating the silicon substrate at a temperature lower than the temperature at which cobalt disilicide (CoSi ₂ ) is formed, or by performing vacuum annealing without breaking the vacuum. Japanese Patent Application Laid-Open No. 9-69497 (Patent Document) discloses a technique of forming a cobaltous disilicide (CoSi ₂ ) film by forming a cobaltous (Co ₂ Si) film or a cobalt monosilicide (CoSi) film and then performing a heat treatment. 1). There is a corresponding US Pat. No. 5,780,361 (Patent Document 2).

  Further, the temperature of the substrate including the silicon region is adjusted to any temperature from 200 ° C. to 400 ° C., and a collimate sputtering method or a long throw sputtering method is used on the upper surface of the silicon region. Japan has a technology in which a metal film is formed and a protective film is continuously formed on the upper surface of the metal film, and then a heat treatment is performed on the metal film, the protective film, and the silicon region to form a silicide film on the silicon region. It describes in Unexamined-Japanese-Patent No. 2003-158091 (patent document 3). There is a corresponding US Patent Application Publication No. 2003/096491 (Patent Document 4).

  In addition, in the sputtering method for forming a metal film, a collimator with the cell partition walls inclined is installed between the target and the substrate installed in parallel with each other, and the angle approaches the peripheral part from the central part of the collimator. Japanese Patent Application Laid-Open No. 10-121234 (Patent Document 5) describes a technique for eliminating the asymmetry of film formation by increasing the size accordingly.

  Furthermore, in a general sputtering technique, a technique for changing the aperture of the collimator in the radial direction in order to ensure the flatness of film formation is disclosed in Japanese Patent Laid-Open No. 11-200029 (Patent Document 6). .

Japanese Patent Laid-Open No. 08-031769 (Patent Document 7) discloses a technique of using a sputtering apparatus having a collimator for forming cobalt silicide.
Japanese Patent Laid-Open No. 9-69497 US Pat. No. 5,780,361 JP 2003-158091 A US Patent Application Publication No. 2003/096491 JP-A-10-121234 Japanese Patent Laid-Open No. 11-200029 Japanese Patent Laid-Open No. 08-031769

  Regarding the formation of a refractory metal silicide compound, there are various technical problems described below.

  The refractory metal film is formed on a semiconductor wafer (hereinafter simply referred to as a wafer) by, for example, a collimated sputtering method. In collimated sputtering, a plate called a collimator with a large number of control holes is placed between the target and the wafer, and only the components perpendicular to the wafer of sputtered particles that have jumped out of the target in various directions are extracted. It is a film forming technique, and damage to the wafer due to electron charging can be reduced.

  However, when a refractory metal film such as a cobalt (Co) film is formed by a collimated sputtering method, the film thickness distribution of the cobalt film in the wafer surface is thick at the center of the wafer due to the influence of the collimator. In this case, there is a problem that the film becomes non-uniform due to the tendency to become thin and the variation becomes large.

  The thickness of the cobalt silicide film formed by the silicide reaction largely depends on the thickness of the cobalt film before the silicide reaction. For this reason, the nonuniformity of the cobalt film thickness distribution appears as the nonuniform cobalt silicide film thickness distribution, and the cobalt silicide film thickness distribution in the wafer surface is thick at the center of the wafer. It becomes thinner at the periphery. However, in the central portion of the wafer on which the cobalt silicide film is formed thick, the distance between the cobalt silicide film and the interface of the pn junction is shortened, causing an increase in leakage current at the pn junction.

  Although the thickness of the cobalt film formed on the wafer is reduced and the distance between the cobalt silicide film and the interface of the pn junction is sufficiently maintained even in the central portion of the wafer. However, an increase in resistance is observed due to a decrease in the thickness of the cobalt silicide film, and the advantage of low resistance using the cobalt silicide film cannot be utilized.

  An object of the present invention is to provide a technique capable of improving the film thickness distribution uniformity in a wafer surface of a film formed by a sputtering method.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  One aspect of the present invention is that a collimator provided with a plurality of control holes is installed between a substrate and a target, the target is sputtered, and the first film is formed on the main surface of the relatively high temperature substrate. The aspect ratio of a large number of control holes is changed corresponding to the film thickness distribution of the first film in one collimator.

Other features of the invention disclosed in the present application will be briefly described as follows.
1. A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) A collimator provided with a large number of control holes is installed between a substrate and a target, and the target is sputtered to deposit a first film on the main surface of the substrate at a relatively high temperature. Process
Here, the collimator has:
(I) The aspect ratio of the plurality of control holes is changed corresponding to the film thickness distribution of the first film.
2. In the method of manufacturing a semiconductor integrated circuit device according to the item 1, the aspect ratio of the plurality of control holes continuously changes.
3. In the method for manufacturing a semiconductor integrated circuit device according to the item 1 or 2, an aspect ratio of the plurality of control holes continuously decreases from a central portion to a peripheral portion of the collimator.
4). In the method for manufacturing a semiconductor integrated circuit device according to the item 1 or 2, the aspect ratio of the plurality of control holes continuously increases from the center to the periphery of the collimator.
5). 5. In the method of manufacturing a semiconductor integrated circuit device according to any one of Items 1 to 4, when the smallest aspect ratio of the plurality of control holes is 1, the largest aspect ratio of the plurality of control holes is This is a peripheral range having a central value of 1.25.
6). 5. In the method of manufacturing a semiconductor integrated circuit device according to any one of Items 1 to 4, when the smallest aspect ratio of the plurality of control holes is 1, the largest aspect ratio of the plurality of control holes is The range is from 1.15 to 1.35.
7). 5. In the method of manufacturing a semiconductor integrated circuit device according to any one of Items 1 to 4, when the smallest aspect ratio of the plurality of control holes is 1, the largest aspect ratio of the plurality of control holes is It is in the range of 1.05 to 1.5.
8). In the method of manufacturing a semiconductor integrated circuit device according to any one of Items 1 to 7, a value obtained by dividing the smallest aspect ratio of the plurality of control holes by the largest aspect ratio of the plurality of control holes is: , 0.8 as a central range.
9. In the method of manufacturing a semiconductor integrated circuit device according to any one of Items 1 to 7, a value obtained by dividing the smallest aspect ratio of the multiple control holes by the largest aspect ratio of the multiple control holes is: , 0.7 to 0.9.
10. In the method of manufacturing a semiconductor integrated circuit device according to any one of Items 1 to 7, a value obtained by dividing the smallest aspect ratio of the multiple control holes by the largest aspect ratio of the multiple control holes is: 0.65 to 0.95.
11. 11. The method for manufacturing a semiconductor integrated circuit device according to any one of Items 1 to 10, wherein the temperature of the substrate is 300 ° C. or higher.
12 11. The method for manufacturing a semiconductor integrated circuit device according to any one of Items 1 to 10, wherein the temperature of the substrate is 350 ° C. or higher.
13. 11. The method for manufacturing a semiconductor integrated circuit device according to any one of Items 1 to 10, wherein the temperature of the substrate is 400 ° C. or higher.
14 14. The method for manufacturing a semiconductor integrated circuit device according to any one of Items 1 to 13, wherein the collimator is made of aluminum, aluminum alloy, stainless steel or titanium, or stainless steel whose surface is coated with aluminum or aluminum alloy. Steel or titanium.
15. 15. The manufacturing method of a semiconductor integrated circuit device according to any one of Items 1 to 14, wherein the sputtering is a highly directional sputtering method.
16. The method for manufacturing a semiconductor integrated circuit device according to any one of Items 1 to 15 further includes the following steps:
(B) After the step (a), by performing a first heat treatment on the main surface of the substrate at a first temperature, the substrate and the first film are reacted;
(C) After the step (b), a step of removing an unreacted portion of the first film;
(D) After the step (c), performing a second heat treatment on the main surface of the substrate at a second temperature higher than the first temperature.
17. The method for manufacturing a semiconductor integrated circuit device according to Item 16 further includes the following steps:
(E) A step of performing a third heat treatment on the main surface of the substrate at a third temperature lower than the first temperature before the step (b).
18. 18. In the method for manufacturing a semiconductor integrated circuit device according to any one of Items 1 to 17, the first film is a cobalt film.
19. 19. In the method of manufacturing a semiconductor integrated circuit device according to any one of Items 1 to 18, a thickness of the first film deposited on the substrate is in a range of 7 nm to 10 nm.
20. 19. In the method of manufacturing a semiconductor integrated circuit device according to any one of Items 1 to 18, the thickness of the first film deposited on the substrate is in the range of 5 nm to 15 nm.
21. 19. In the method for manufacturing a semiconductor integrated circuit device according to any one of Items 1 to 18, the film thickness of the first film deposited on the substrate is in the range of 3 nm to 20 nm.
22. In the method of manufacturing a semiconductor integrated circuit device according to any one of Items 1 to 21, the first film is a nickel film or a nickel cobalt alloy film.
23. Item 17. The method for manufacturing a semiconductor integrated circuit device according to Item 16, further including the following steps:
(F) A step of depositing a second film having an antioxidant function on the first film before the step (b).
24. 24. In the method for manufacturing a semiconductor integrated circuit device according to the item 23, the second film is a titanium nitride film, a tungsten nitride film, or a tantalum nitride film.
25. Item 17. The method for manufacturing a semiconductor integrated circuit device according to Item 16, further including the following steps:
(G) A step of sequentially depositing a second film and a third film having an antioxidant function on the first film before the step (b).
26. 26. In the method for manufacturing a semiconductor integrated circuit device according to Item 25, the second film is a titanium nitride film, and the third film is a titanium film.

Further, if other features of the invention disclosed in the present application are simply described in sections, they are as follows.
1. A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) forming an element isolation region on the first main surface of the wafer to partition a silicon active region surrounded by the device isolation region;
(B) a step of partitioning the source / drain regions by forming gate electrodes having sidewall spacers on both sides via a gate insulating film on the silicon active region;
(C) The element isolation region and the source of the first main surface of the wafer by collimated sputtering in which a mechanical collimator having a large number of openings with non-uniform aspect ratio is interposed between the wafer and the cobalt target. The silicon surface of the drain region, the sidewall spacer of the gate electrode, and the polysilicon surface constituting the upper surface of the gate electrode (polymetal gate having a refractory metal layer on the polysilicon gate electrode, and the source drain) In a damascene gate, a replacement gate, etc. that form a gate insulating film and a gate electrode after heat treatment, silicidation on polysilicon is not essential or unnecessary), and the temperature of the first main surface of the wafer is Dies on the silicon surface and the polysilicon surface First silicide layer is formed to Baltic silicide (Co ₂ Si) as a main component, substantially controlled within a first temperature range where the silicide film is not formed to cobalt monosilicide the (CoSi) as a main component A step of forming a cobalt film under the same condition (the same is true in the case of the nickel silicide process);
(D) a step of converting the first silicide film into a second silicide film containing cobalt monosilicide as a main component by a first heat treatment;
(E) After the step (d), a step of removing an unreacted portion of the cobalt film;
(F) After the step (e), a step of converting the second silicide film into a third silicide film containing cobalt disilicide (CoSi ₂ ) as a main component by a second heat treatment.
2. In the method for manufacturing a semiconductor integrated circuit device according to Item 1, the first temperature range is not less than 300 degrees Celsius and less than 450 degrees Celsius.
3. In the method of manufacturing a semiconductor integrated circuit device according to Item 1, the first temperature range is 350 degrees centigrade or more and less than 450 degrees centigrade.
4). In the method of manufacturing a semiconductor integrated circuit device according to Item 1, the first temperature range is not less than 400 degrees Celsius and less than 450 degrees Celsius.
5). In the method for manufacturing a semiconductor integrated circuit device according to Item 1, the first temperature range is not less than 300 degrees Celsius and less than 400 degrees Celsius.
6). Item 6. The method of manufacturing a semiconductor integrated circuit device according to any one of Items 1 to 5, wherein the collimator is substantially rotationally symmetric (when referring to the symmetry of the collimator as a whole, the upper and lower profiles, that is, the contour shape, Yes, except for other internal structures, that is, the shape of the opening, the shape of the partition wall, etc. The same applies to the other portions of the present application), and is substantially plane symmetric with respect to the plane of symmetry perpendicular to the axis of rotation. (The collimating sputtering technique using a mechanical collimator has a problem that the collimator is deformed due to thermal strain or stress imbalance as a result of cobalt being concentrated on the target side of the collimator. By making the profile of the upper and lower surfaces symmetrical and rotationally symmetric with respect to the vertical rotation axis, The collimator can be used upside down each time the amount of adhesion is near the strain limit, so that the aperture ratio of the collimator decreases as the amount of adhesion increases after being used several times alternately. Therefore, it is necessary to clean or recycle the collimator itself, that is, from the standpoint of preventing dust generation and wear of the base metal from being removed by blasting the cobalt on the surface of the stainless steel together with the underlying aluminum. In addition, when the base material titanium is used, it is possible to reduce dust generation even without an aluminum coating.Titanium has a merit that it is more resistant to deformation than stainless steel. May be coated).
7). Item 7. The method for manufacturing a semiconductor integrated circuit device according to any one of Items 1 to 6, wherein the plurality of openings are regular hexagons having substantially the same opening area, and form a substantially hexagonal close-packed lattice. Aligned (to ensure uniform deposition characteristics and high aperture ratio at a distance that is micro, ie, about the size of the open cell, the two-dimensional geometry of the open cell can be filled. A square, rectangle, square, rhombus, regular hexagon, etc., but a hexagonal close-packed lattice-like structure mainly composed of regular hexagons is most preferable in terms of strength and microscopic uniformity).
8). Item 8. The manufacturing method of a semiconductor integrated circuit device according to any one of Items 1 to 7, wherein an aspect ratio change rate of the collimator is less than 98% and 50% or more.
9. Item 9. The method for manufacturing a semiconductor integrated circuit device according to any one of Items 1 to 8, wherein the partition walls of the plurality of openings of the collimator are substantially parallel to a straight line connecting the center of the wafer and the center of the cobalt target. (Effective for securing a high aperture ratio).
10. Item 10. The manufacturing method of a semiconductor integrated circuit device according to any one of Items 1 to 9, wherein an aperture ratio of a portion of the collimator facing the wafer is 85% or more.
11. Item 11. The method for manufacturing a semiconductor integrated circuit device according to any one of Items 1 to 10, wherein the collimator has a coating layer whose main material is other than aluminum and whose surface is mainly composed of aluminum. .
12 Item 12. The method for manufacturing a semiconductor integrated circuit device according to any one of Items 1 to 11, wherein the base material of the collimator is stainless steel.
13. Item 13. The method for manufacturing a semiconductor integrated circuit device according to any one of Items 1 to 12, wherein an aspect ratio change rate of the collimator is less than 95% and 65% or more.
14 Item 13. The manufacturing method of a semiconductor integrated circuit device according to any one of Items 1 to 12, wherein an aspect ratio change rate of the collimator is less than 90% and 70% or more.
15. Item 13. The method for manufacturing a semiconductor integrated circuit device according to any one of Items 1 to 12, wherein the aspect ratio change rate of the collimator is less than 85% and 75% or more.
16. Item 16. The method for manufacturing a semiconductor integrated circuit device according to any one of Items 1 to 15, wherein the thickness of the partition wall of the collimator is less than 3 mm and 0.3 mm or more (the strength against deformation of the collimator and a high aperture ratio). Effective to secure).
17. Item 16. The method for manufacturing a semiconductor integrated circuit device according to any one of Items 1 to 15, wherein a thickness of the partition wall of the collimator is less than 2 mm and 0.5 mm or more.
18. Item 15. The method for manufacturing a semiconductor integrated circuit device according to any one of Items 1 to 15, wherein a thickness of the partition wall of the collimator is less than 1.5 mm and 0.7 mm or more.
19. Item 19. The method for manufacturing a semiconductor integrated circuit device according to any one of Items 1 to 18, wherein the size of the plurality of openings is (a size of the openings is a distance between opposing partition walls. Is a distance between sides), less than 20 mm, and 5 mm or more (to ensure a cobalt deposition rate of 10 nm / min or more generally required for mass production, and to ensure microscopic deposition uniformity. (It does not exclude the deposition rate below this).
20. Item 19. The method for manufacturing a semiconductor integrated circuit device according to any one of Items 1 to 18, wherein the plurality of openings have a size of less than 15 mm and 7 mm or more.
21. Item 21. The manufacturing method of a semiconductor integrated circuit device according to any one of Items 1 to 20, wherein a contour of a main surface of the collimator is a second-order or higher-order curved surface (including one approximated by a large number of linear portions). (A linear profile may not compensate for uneven film thickness distribution with sufficient accuracy. On the other hand, a linear profile from the center to the periphery has the advantage that the collimator can be easily processed.) .
22. A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) forming an element isolation region on the first main surface of the wafer to partition a silicon active region surrounded by the device isolation region;
(B) a step of partitioning the source / drain regions by forming gate electrodes having sidewall spacers on both sides via a gate insulating film on the silicon active region;
(C) The element isolation region and the source of the first main surface of the wafer by collimated sputtering in which a mechanical collimator having a large number of openings with non-uniform aspect ratio is interposed between the wafer and the cobalt target. The temperature of the first main surface of the wafer is set to 300 ° C. or more and 450 ° C. on the silicon surface of the drain region, the side wall spacer of the gate electrode, and the polysilicon surface constituting the upper surface of the gate electrode. Forming a cobalt film in a controlled state within a first temperature range of less than
(D) After the step (c), a first heat treatment is performed in a state where the temperature of the first main surface of the wafer is controlled within a second temperature range of 400 degrees Celsius or more and less than 600 degrees Celsius. Process;
(E) After the step (d), a step of removing an unreacted portion of the cobalt film;
(F) After the step (e), a second heat treatment is performed in a state where the temperature of the first main surface of the wafer is controlled within a third temperature range of 600 degrees Celsius or more and less than 850 degrees Celsius. Process.
23. Item 23. The manufacturing method of a semiconductor integrated circuit device according to Item 22, wherein the first temperature range is 350 degrees centigrade or more and less than 450 degrees centigrade.
24. Item 23. The manufacturing method of a semiconductor integrated circuit device according to Item 22, wherein the first temperature range is not less than 400 degrees Celsius and less than 450 degrees Celsius.
25. Item 23. The manufacturing method of a semiconductor integrated circuit device according to Item 22, wherein the first temperature range is not less than 300 degrees Celsius and less than 400 degrees Celsius.
26. 26. In the method of manufacturing a semiconductor integrated circuit device according to any one of Items 22 to 25, the collimator is substantially rotationally symmetric and is substantially plane symmetric with respect to a symmetry plane perpendicular to the axis of the rotation target. It is.
27. 27. In the method of manufacturing a semiconductor integrated circuit device according to any one of Items 22 to 26, the plurality of openings are regular hexagons having substantially the same opening area so as to form a substantially hexagonal close-packed lattice. It is arranged.
28. Item 28. The method for manufacturing a semiconductor integrated circuit device according to any one of Items 22 to 27, wherein an aspect ratio change rate of the collimator is less than 98% and 50% or more.
29. 29. The manufacturing method of a semiconductor integrated circuit device according to any one of Items 22 to 28, wherein the partition walls of the plurality of openings of the collimator are substantially parallel to a straight line connecting the center of the wafer and the center of the cobalt target. It is.
30. 30. The manufacturing method of a semiconductor integrated circuit device according to any one of Items 22 to 29, wherein an aperture ratio of a portion of the collimator facing the wafer is 85% or more.
31. Item 31. The method of manufacturing a semiconductor integrated circuit device according to any one of Items 22 to 30, wherein the collimator has a coating layer whose main material is other than aluminum and whose surface is mainly composed of aluminum. .
32. Item 32. The method for manufacturing a semiconductor integrated circuit device according to any one of Items 22 to 31, wherein the base material of the collimator is stainless steel.
33. Item 33. The method for manufacturing a semiconductor integrated circuit device according to any one of Items 22 to 32, wherein an aspect ratio change rate of the collimator is less than 95% and 65% or more.
34. Item 33. The method for manufacturing a semiconductor integrated circuit device according to any one of Items 22 to 32, wherein an aspect ratio change rate of the collimator is less than 90% and 70% or more.
35. Item 33. The method for manufacturing a semiconductor integrated circuit device according to any one of Items 22 to 32, wherein an aspect ratio change rate of the collimator is less than 85% and 75% or more.
36. Item 36. The method for manufacturing a semiconductor integrated circuit device according to any one of Items 22 to 35, wherein the collimator has a partition wall thickness of less than 3 mm and greater than or equal to 0.3 mm.
37. Item 36. The method for manufacturing a semiconductor integrated circuit device according to any one of Items 22 to 35, wherein the collimator has a partition wall thickness of less than 2 mm and 0.5 mm or more.
38. Item 36. The manufacturing method of a semiconductor integrated circuit device according to any one of Items 22 to 35, wherein a thickness of the partition wall of the collimator is less than 1.5 mm and 0.7 mm or more.
39. 39. In the method of manufacturing a semiconductor integrated circuit device according to any one of Items 22 to 38, the size of the plurality of openings is (a size of the opening is a distance between opposing partition walls. Is a distance between sides), less than 20 mm, and 5 mm or more.
40. 39. In the method for manufacturing a semiconductor integrated circuit device according to any one of Items 22 to 38, the size of the plurality of openings is less than 15 mm and 7 mm or more.
41. Item 41. The manufacturing method of a semiconductor integrated circuit device according to any one of Items 22 to 40, wherein a contour of a main surface of the collimator is a second-order or higher-order curved surface.
42. A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) A mechanical collimator having a large number of apertures with a non-uniform aspect ratio, the base material of which has a coating layer whose main component is other than aluminum and whose main component is aluminum. By means of collimated sputtering interposed between the wafer and a target containing cobalt or nickel as a main component, cobalt or nickel is mainly used on the element isolation region of the first main surface of the wafer and the silicon surface of the source / drain region. A step of forming a metal film as a component.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  By using a cobalt film formed by a collimated sputtering method, it is possible to form a silicide layer with low leakage current at the pn junction and low resistance.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  Further, in the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments, but they are not irrelevant to each other unless otherwise specified. The other part or all of the modifications, details, supplementary explanations, and the like are related.

  Further, in the present application, for the sake of convenience, a wafer having a diameter (diameter) of about 200 mm will be described. However, it goes without saying that the present invention can be applied to a wafer having a diameter of about 300 mm and a wafer having a larger or smaller diameter.

  Also, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), particularly when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  In the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and clearly considered essential in principle. Needless to say.

  Similarly, in the following embodiments, when referring to the shape and positional relationship of components and the like, it is substantially formed unless specifically stated or otherwise considered in principle. And the like are included. For example, a regular hexagon includes not only a geometrically perfect shape but also an approximation thereof. The same applies to the above numerical values and ranges.

  For the sake of convenience, the positional relationship will be described on the premise of the arrangement shown in FIG. 4. For example, “upper or upper surface” does not mean the opposite direction of gravity, but conceptually. The direction of the device surface of the wafer (mainly a semiconductor integrated circuit or a main surface on which a semiconductor element is formed) is the top. Accordingly, in this context, the term “perpendicular” refers to an axial direction substantially perpendicular to the main surface of the wafer and substantially the same, unless otherwise specified and in principle considered to be essential in principle. It shall mean the same direction (for example, it goes without saying that when sputtering, the device surface of the wafer is directed downward, lateral or oblique, it will not be in the opposite direction of gravity).

  In addition, the term “semiconductor integrated circuit device” as used herein refers not only to those made on a silicon single crystal wafer, but to those made on an SOI (Silicon On Insulator) substrate, unless otherwise specified. In addition, those made on other substrates such as TFT (Thin Film Transistor) liquid crystal are also included. Similarly, the term “wafer” refers to not only a silicon single crystal wafer but also a substantially disk-like or rectangular integrated circuit substrate for producing an SOI substrate, TFT liquid crystal, etc. unless otherwise specified. Shall be included.

  In addition, with respect to the silicon substrate surface portion or so-called polysilicon electrode, when silicon is referred to, silicon with impurities introduced as needed is included unless otherwise specified or otherwise clearly stated. And a silicon base member whose performance has been improved as an alloy by adding germanium or the like to silicon (such as a substrate surface region converted to SiGe or a polycrystalline silicon electrode converted to SiGe).

  In addition, the term “polysilicon” includes not only typical polycrystalline silicon but also amorphous surface silicon and microcrystalline silicon unless otherwise specified or otherwise clearly stated. . In general, polysilicon may also be amorphous at the beginning of formation, and this is generally changed to narrowly defined polysilicon by a subsequent heat treatment, but at what point it was changed to narrowly defined polysilicon. This is because it is difficult to specify.

  In addition, when referring to the component of a member (for example, member X consisting of A), it is not excluded to include other components unless specifically stated otherwise or otherwise clearly stated. . The same applies to atmospheric gases. For example, even if it is a cobalt target, it does not exclude additives and other contained substances added for various reasons.

  Needless to say, a gate insulating film is not limited to an oxide film even if it is a CMOS (Complementary Metal Oxide Semiconductor) type integrated circuit. For example, a silicon nitride film that is a non-oxide inorganic insulating film is used as a gate insulating film. The same applies to “metal” and “semiconductor”.

  In the following embodiments, only the device that directly silicidizes the device surface of the silicon single crystal wafer has been described as an example. However, the present invention is not limited thereto, and an epitaxial silicon layer is selectively formed on the source / drain region. The elevated source / drain method for forming the above and the like is also included. On the other hand, there is an advantage that the process can be greatly simplified by forming it substantially directly as in the embodiment. Note that “directly” does not exclude a processing layer, an intervening layer, or the like having a minute thickness.

  Further, a MIS • FET (Metal Insulator Semiconductor Field Effect Transistor) representing a field effect transistor may be abbreviated as MIS, a p-channel type MIS • FET may be abbreviated as pMIS, and an n-channel type MIS • FET may be abbreviated as nMIS. .

  The present embodiment is applied to a CMOS type integrated circuit (including a non-silicon oxide high-k gate insulating film), and the manufacturing method will be described in the order of steps with reference to FIGS. To do.

  First, as shown in FIG. 1, an element isolation trench 2 is formed in a semiconductor substrate (hereinafter referred to as a substrate or a wafer) 1 made of p-type single crystal silicon having a specific resistance of, for example, about 1 to 10 Ωcm. The element isolation trench 2 is formed by etching the substrate 1 in the element isolation region, and then a silicon oxide film 3 is deposited on the substrate 1 including the inside of the element isolation trench 2 by a CVD (Chemical Vapor Deposition) method. Then, the unnecessary silicon oxide film 3 outside the element isolation trench 2 is polished and removed by a CMP (Chemical Mechanical Polishing) method.

  Next, after boron (B) is ion-implanted into a part of the substrate 1 and phosphorus (P) is ion-implanted into the other part, the p-type well 4 and the n-type well 5 are formed. The gate oxide film 6 is formed on the surface of each of the p-type well 4 and the n-type well 5 by steam oxidation.

  Next, as shown in FIG. 2, a gate electrode 7 is formed on each of the p-type well 4 and the n-type well 5 (a so-called dual gate CMOS or CMIS (Complementary Metal Insulator Semiconductor) integrated circuit). ). In order to form the gate electrode 7, for example, a polycrystalline silicon film is formed on the gate oxide film 6 by a CVD method (in practice, it is often in an amorphous state at the time of deposition, but is polycrystallized by any one of the subsequent heat treatments. Therefore, for the sake of convenience, except for specific cases, these are also referred to as “polycrystalline silicon”), and after that, phosphorus is ion-implanted into the polycrystalline silicon film above the p-type well 4 and n After boron is ion-implanted into the polycrystalline silicon film above the mold well 5, the polycrystalline silicon film is patterned by dry etching using the resist pattern as a mask.

Next, phosphorus or arsenic (As) is ion-implanted into the p-type well 4 to form a low impurity concentration n ⁻ -type semiconductor region 8, and boron is ion-implanted into the n-type well 5 to reduce the impurity concentration. A p ⁻ type semiconductor region 9 is formed.

Next, as shown in FIG. 3, the silicon nitride film deposited on the substrate 1 by the CVD method is anisotropically etched to form the sidewall 10 on the side wall of the gate electrode 7 and the substrate 1 (n ^{The surface of the −} type semiconductor region 8 and the p ⁻ type semiconductor region 9) is exposed. Subsequently, phosphorus or arsenic is ion-implanted into the p-type well 4 to form a high impurity concentration n ⁺ -type semiconductor region (source, drain) 11, and boron is ion-implanted into the n-type well 5 to increase the high impurity concentration. A p ⁺ type semiconductor region (source, drain) 12 having a concentration is formed. n ⁺ -type pn junction of the semiconductor regions 11 (n ⁺ -type semiconductor region 11 and the p-type well 4 are in contact with the interface) junction depth (the substrate 1 from the surface of the substrate 1 to the pn junction thickness direction of the depth) and the p ⁺ -type pn junction of the semiconductor region 12 (p ⁺ -type semiconductor region 12 and the n-type well 5 are in contact with the interface) junction depth is approximately the range of 50nm to 300 nm.

Next, after the surface of the substrate 1 is batch-cleaned with buffered hydrofluoric acid (the cleaning is performed in order to remove the natural oxide film on the silicon surface or when the ion implantation is performed through a CVD oxide film or the like, the oxide film). The cobalt silicide layer is formed on the respective surfaces of the gate electrode 7 and the source and drain (n ⁺ type semiconductor region 11 and p ⁺ type semiconductor region 12) by the following method. This is a so-called salicide method, in which silicidation on the gate electrode and on the source and drain is performed in a self-aligning manner by utilizing the separation action of the side wall of the gate electrode. This method has an advantage that the gate electrode can be silicided simultaneously and the resistance can be reduced. On the other hand, in the case of a polymetal gate electrode (or metal electrode), the resistance on the gate electrode is further reduced by the metal, so it is not subject to silicidation. Therefore, before depositing the cobalt film, Must be covered with an insulating film.

  FIG. 4 is a schematic cross-sectional view of a DC magnetron sputtering apparatus used for forming a cobalt film.

  The sputtering apparatus 100 includes a vacuum container 102 constituting a sputtering chamber 101, and the sputtering chamber 101 is evacuated by a vacuum pump such as a cryopump or a dry pump. A loading / unloading port 103 for loading / unloading the wafer 1 is provided in the sputtering chamber 101, and the loading / unloading port 103 is configured to be opened and closed by a gate valve 104. In addition, a gas supply pipe 106 for supplying an argon (Ar) gas 105 as a discharge gas that is inert and has a large mass for generating ions is inserted into the sputtering chamber 101.

  A backing plate 107 is provided at the upper opening of the vacuum vessel 102 so as to seal the sputtering chamber 101, and a target 108 is mounted in contact with the backing plate 107 so as to be replaceable. As will be described later, the target 108 is sputtered by argon ions to eject the composition, and forms a sputtering film on the wafer 1 that is a substrate to be processed, and is formed into a disk shape from cobalt. . Further, the cobalt purity of the target 108 is 99.99% by weight or more, more preferably 99.999% by weight or more, excluding non-metallic impurities. In addition, about a cobalt target, there is description in the international patent publication WO98 / 42009 pamphlet of Nishihara et al. There is a corresponding US Pat. No. 6,693,001 (issued on Feb. 17, 2004).

  A lift 109 is installed vertically upward at the bottom of the vacuum vessel 102, and an electrostatic chuck 110 having a heating mechanism is supported on the lift 109 so as to be raised and lowered. The electrostatic chuck 110 is configured to heat the wafer 1 while holding the wafer 1 on the upper surface. A power supply device for applying a DC voltage or a high-frequency voltage is electrically connected between the electrostatic chuck 110 and the backing plate 107.

  A lower shield 111 is installed on the lower side of the electrostatic chuck 110, and an upper shield 112 is disposed above the sputtering chamber 101 so as to surround a region immediately below the target 108, so that an upper end opening of the vacuum vessel 102 is provided. Is held in. The lower shield 111 and the upper shield 112 are made of stainless steel, aluminum, or the like, and are configured to prevent particles sputtered from the target 108 from adhering to the inner wall of the sputtering chamber 101 by surrounding the target 108. Has been.

  On the other hand, a disc-shaped magnet plate 113 for holding plasma is disposed above the backing plate 107 in a concentric horizontal manner with respect to the sputtering chamber 101, and the magnet plate 113 is a rotating shaft disposed on the center line of the sputtering chamber 101. 114 is configured to be rotated.

  A collimator 115 is installed at a height position having a predetermined distance from the target 108 and the wafer 1 so as to cross horizontally.

  FIG. 5A is a schematic plan view of the collimator, and FIG. 5B is a schematic cross-sectional view taken along the line aa ′ in FIG.

  The collimator 115 includes a main body 116 formed in a disk shape larger than that of the wafer 1. The main body 116 has a number of hexagonal hole-shaped control holes 117 penetrating in the thickness direction, and the opening area covers the entire surface. The control holes 117 are arranged so as to be substantially uniform, and all the control holes 117 are provided substantially parallel to each other at a predetermined interval. Many control holes 117 are formed by cutting or the like. As a material of the collimator 115, a refractory metal film or metal alloy such as aluminum, aluminum alloy, stainless steel, or titanium can be used. In addition, the base material is a high melting point metal such as stainless steel or titanium or a metal alloy, and the surface is blasted (blasting material is blown onto the base material with compressed air or continuously projected with a rotary blade, (Surface treatment technology to remove dirt) and then thermal spray treatment using aluminum or aluminum alloy (coating technology to make a film by spraying metal, ceramic, etc. melted by a heat source such as combustion gas, arc, plasma, etc.) The collimator 115 may be used.

  Further, the main body 116 of the collimator 115 is gradually thinned from the central part to the peripheral part. For example, like the convex lens, the upper surface and the lower surface of the main body 116 have outwardly convex shape surfaces in a vertically symmetrical manner. As a result, the aspect ratio (hole depth d / hole diameter w) of the large number of control holes 117 continuously decreases from the center to the periphery of the collimator 115. Assuming that the aspect ratio of the control hole 117 located on the outermost side of the main body 116 is 1, the aspect ratio of the control hole 117 located in the center of the main body 116 is considered to be within a suitable range, for example, 1.05 to 1.5 ( Of course, it is not limited to this range depending on other conditions). Further, a range suitable for mass production is considered to be 1.15 to 1.35, but a peripheral range having a central value of 1.25 is considered most suitable. A value (Ap / Ac) obtained by dividing the aspect ratio Ap of the control hole 117 positioned on the outermost side of the main body 116 by the aspect ratio Ac of the control hole 117 positioned on the center of the main body 116 is, for example, 0.65 to 0. .95 is considered an appropriate range (although not limited to this range depending on other conditions). Further, a range suitable for mass production is 0.7 to 0.9, but a peripheral range centered on 0.8 is considered most suitable.

  In the collimated sputtering method, the oblique component cobalt atoms collide with the inner peripheral surface of the collimator control hole and are trapped, and only the vertical component cobalt atom reaches the wafer, so the deposition rate is higher than that of the sputtering method without using a collimator. The rate of slowing depends on the aspect ratio of the control hole provided in the collimator. That is, as the aspect ratio of the control hole provided in the collimator increases, the film formation rate decreases. Therefore, by making the aspect ratio of the control hole provided in the central part of the collimator larger than the aspect ratio of the control hole provided in the peripheral part of the collimator, the deposition rate of the cobalt film in the wafer surface is substantially uniform. Can be. That is, since the aspect ratio of the control hole located in the peripheral part of the collimator is smaller than that in the central part, the amount of cobalt atoms passing through the control hole located in the peripheral part is controlled by the control hole located in the central part. Therefore, the film thickness distribution of the cobalt film in the wafer surface can be controlled uniformly over the entire wafer. The aspect ratio of the many control holes of the collimator that is insufficient at the periphery of the wafer is set so as to eliminate the film thickness non-uniformity in the wafer surface of the cobalt film deposited on the wafer in the collimator.

  For example, if the thickness of the center of the main body 116 is 12.5 mm and the hole diameter (interval between the opposite sides) w of the control hole 117 is 10 mm, the hole depth d is 12.5 mm. The ratio Ac is 1.25 (= 12.5 / 10). Further, if the thickness of the main body 116 in which the outermost connection hole 117 is formed is 10 mm, the hole depth d is 10 mm, so the aspect ratio Ap of the outermost connection hole 117 is 1 (= 10/10). Thus, the aspect ratio of the large number of control holes 117 provided in the collimator 115 continuously changes from 1 to 1.25 from the outside to the center of the collimator 115.

  This type of collimator is called a biconvex lens collimator. This is almost symmetrical in the top, bottom, left and right (note that it is not limited to such a target shape). This is done for the following reason. By repeating sputtering, a cobalt film is rapidly deposited on the target side surface of the collimator. This is because the collimator is deformed as it is, so that the upper and lower volume films are balanced, so that the collimator is turned over and used for each sputtering process. In addition, if the target is kept upside down alternately, the aperture ratio (the value obtained by dividing the area of the aperture by the area of the upper surface of the wafer in the orthogonal projection of the collimator onto the wafer surface or a percentage thereof) Therefore, when the deposited cobalt film thickness is about 0.2 mm, it is desirable to clean the collimator and remove the deposited cobalt film. Generally, sputtering using a collimator, that is, collimated sputtering, reduces the deposition rate from 1/6 to 1/8 compared to sputtering without collimator, that is, non-collimated sputtering. Therefore, in order to achieve a deposition rate of 10 nm / min or more normally required for cobalt (in this embodiment, about 40 nm / min), the partition wall of the opening is made substantially vertical and the aperture ratio of the collimator is 80% or more. It is desirable to set it to about 91% in this embodiment. Moreover, in order to achieve such a high aperture ratio, a hexagonal close-packed lattice arrangement in which the shape of the unit opening is substantially a regular hexagon (in consideration of the uniformity of the deposition as a whole, the shape of the opening is the same, Desirably, the sizes should be approximately the same) (the above is true for nickel silicide as well).

Hereinafter, the relationship of the dimension of the member used for the present Example is demonstrated. The diameter of the wafer is about 200 mm, the diameter of the target is about 330 mm, the diameter of the entire collimator opening (control hole) is about 315 mm, and the minimum distance between the target surface and the collimator is 46 mm. Needless to say, the dimensions are not limited to these values. The thickness of the control hole, that is, the partition wall that divides each opening, is preferably about 1 mm on an average basis. Moreover, when considering deformation during use, 0.7 mm or more is suitable for mass production. A value (or a percentage thereof) obtained by dividing the aspect ratio (A _P ) of the outermost opening by the aspect ratio (A _C ) of the opening near the center is referred to as an aspect ratio change rate (M _A ).

  A collimating sputtering technique using a collimator with non-uniform aspect and the like is described in Japanese Patent Application No. 2002-336620 (filed on November 20, 2002) by Suzuki et al. There is a corresponding PCT application PCT / JP03 / 014792 (international filing date November 20, 2003).

  Next, a process for forming a cobalt film and a cobalt salicide layer will be described. An example of the temporal change in wafer temperature, argon gas flow rate, and DC power when forming a cobalt film by sputtering is shown in the process sequence diagram of FIG. The time on the horizontal axis of each parameter in the process sequence diagram is common.

  First, the wafer 1 is cleaned, and then the wafer 1 is heated to, for example, 200 ° C. in a processing chamber different from the sputtering chamber 101 of the sputtering apparatus 100. Subsequently, the wafer 1 is loaded into the sputtering chamber 101 of the sputtering apparatus 100 from the loading / unloading port 103 and transferred to the upper surface of the electrostatic chuck 110. At this time, the sputtering chamber 101 is previously evacuated to a predetermined pressure. Subsequently, the electrostatic chuck 110 is raised by the lift 109, and the wafer 1 placed on the upper surface of the electrostatic chuck 110 is set at a preset height.

  Next, an argon gas 105 as a discharge gas is supplied from the gas supply pipe 106 to the sputtering chamber 101 until the sputtering chamber 101 reaches a predetermined pressure. The flow rate of the argon gas 105 is, for example, 15 to 150 sccm. At this time, the temperature of the wafer 1 gradually increases and is set to a predetermined temperature, for example, 420 ° C.

  Further, when the sputtering chamber 101 reaches a predetermined pressure and the wafer 1 reaches a predetermined temperature, a DC voltage or a high-frequency voltage is applied between the target 108 and the wafer 1 by the power supply device via the backing plate 107 and the electrostatic chuck 110. At the same time, the magnet plate 113 is rotated by the rotating shaft 114. The DC power when the DC voltage is applied is set to 500 to 2000 W, for example, and the flow rate of argon gas is set to 15 to 40 sccm. The pressure in the argon atmosphere is, for example, 0.4 to 2 Pa (not limited to this range), and the target distance (the shortest distance between the target 108 and the wafer 1 during operation) is, for example, 90 mm.

  With the excitation of the plasma formed around the target 108 by these operations, the target 108 is sputtered by argon ions, and cobalt particles are sputtered from the target 108 as particles to be sputtered. The cobalt particles struck out from the target 108 fly in the direction of the wafer 1, pass through the numerous control holes 117 of the collimator 115, and adhere to the wafer 1. As a result, as shown in FIG. 7, a cobalt film (first film) 13 is deposited on the main surface (integrated circuit formation surface) of the substrate (wafer) 1.

  The appropriate thickness of the cobalt film 13 is, for example, 3 nm to 20 nm (not limited to this range depending on other conditions). Further, a range suitable for mass production is 5 nm to 15 nm, and a peripheral range of 7 nm to 10 nm with 8.5 nm as the central value is considered most preferable. If the thickness of the cobalt film 13 is less than 3 nm, the thickness of the cobalt silicide layer formed by the silicide reaction is as thin as about 10.5 nm, and the effect of reducing resistance cannot be sufficiently obtained. Further, when the thickness of the cobalt film 13 is made larger than 20 nm, the thickness of the cobalt silicide layer formed by the silicide reaction becomes about 70 nm, and the junction depth of the pn junction part, for example, deeper than 50 nm, the leakage current is increased. May increase.

  Further, the cobalt film 13 is deposited at a temperature of 300 ° C. or higher, preferably 350 ° C. or higher, more preferably 400 ° C. or higher (and a temperature of less than 450 ° C.). In the present embodiment, the temperature of the wafer 1 is 420 ° C. The temperature here means the surface temperature of the wafer 1 in the sputtering chamber 101 (main surface on the integrated circuit formation side).

  FIG. 8 shows an example of the relationship between the sheet resistance defect rate of the polycrystalline silicon film on which the cobalt silicide layer is formed and the surface temperature of the wafer when the cobalt film is deposited. In all samples, the cobalt silicide layer is formed under the same conditions, and an n-type impurity having the same concentration is added to the polycrystalline silicon film. The thickness of the cobalt film is 7, 9 and 11 nm, and the width of the polycrystalline silicon film is 55 nm.

  As the surface temperature of the wafer increases, the sheet resistance defect rate of the silicided polycrystalline silicon film decreases, and is approximately 20% or less at 400 ° C. or higher. Thus, when the cobalt film is formed at a relatively high temperature, the cobalt and the silicon in the source / drain region (polycrystalline silicon) react with each other while the cobalt film is formed, and the cobalt film and the silicon in the source / drain region (polycrystalline silicon film). ) Can be flattened, so that the sheet resistance defect of the cobalt silicide layer formed by the subsequent silicide reaction can be reduced. The same applies to the reaction between cobalt and single crystal silicon. When the cobalt film is formed at a relatively high temperature, the interface between the cobalt film and the single crystal silicon (wafer) can be flattened. The defect of the sheet resistance of the silicide layer can be reduced.

  In the present embodiment, an electrostatic chuck 110 is used for holding and heating the wafer 1. Since the electrostatic chuck 110 has good adhesion to the wafer 1, it has good temperature control and temperature distribution characteristics. However, even if the electrostatic chuck 110 is used, a temperature difference of about 30 ° C. occurs between the surface temperature of the wafer 1. For example, in order to set the surface temperature of the wafer 1 to about 420 ° C., the electrostatic chuck 110 It is necessary to set the temperature to about 450 ° C. The chuck is not limited to the electrostatic chuck 110, and other types of chucks such as a mechanical clamp may be used. However, even if a mechanical clamp is used, a temperature difference of about 70 to 80 ° C. occurs between the surface temperature of the wafer 1 and the surface temperature of the wafer 1 is set to about 420 ° C., for example, as with the electrostatic chuck 110. Therefore, it is necessary to set the temperature of the mechanical clamp to about 490 to 500 ° C.

Next, the above-described sputtering operation is stopped, and the heat treatment (hold annealing; third heat treatment) of the wafer 1 is performed in an argon atmosphere. As a result, as shown in FIG. 9, the interface between the source and drain (n ⁺ type semiconductor region 11, p ⁺ type semiconductor region 12) and the cobalt film 13 formed on the substrate 1, and the gate made of the polycrystalline silicon film. A dicobalt silicide (Co ₂ Si) layer 16a is formed at the interface between the electrode 7 and the cobalt film 13, respectively.

In this heat treatment, the silicide reaction rapidly proceeds at the interface between the source / drain (n ⁺ type semiconductor region 11, p ⁺ type semiconductor region 12) and the cobalt film 13 and at the interface between the gate electrode 7 and the cobalt film 13. A low temperature (third temperature) at which the silicide layer mainly composed of the silicide (Co ₂ Si) layer 16a is not converted into a silicide layer mainly composed of cobalt monosilicide (CoSi) or cobalt disilicide (CoSi ₂ ). For example, in a temperature range of 300 ° C. or higher and lower than 450 ° C. (surface temperature of the wafer 1). In the present embodiment, the heat treatment was performed with the argon gas flow rate set to 15 to 40 sccm while maintaining the surface temperature of the wafer 1 at 420 ° C., for example. This heat treatment may be performed after unloading from the sputtering chamber 101 or may be omitted.

  When a cobalt film 13 having a desired thickness is formed on the wafer 1 and the hold annealing is completed, the wafer 1 is naturally cooled. Thereafter, the lift 109 is lowered, and the wafer 1 held by the electrostatic chuck 110 is returned to the loading / unloading position. Subsequently, the film-formed wafer 1 is unloaded from the sputtering chamber 101. Thereafter, the substrate is cooled to approximately 50 ° C. or lower in a processing chamber different from the sputtering chamber 101 and is carried out of the sputtering apparatus 100.

  FIG. 10A is a film thickness distribution table in the wafer surface showing the film thickness distribution in the wafer surface of the cobalt film formed on the dummy wafer (wafer on which an actual integrated circuit pattern is not formed). FIG. 2B is a schematic plan view showing the measurement position on the wafer. FIG. 10A shows a cobalt film formed by using a collimator (uniform aspect collimator) in which the aspect ratio of a large number of control holes according to the present embodiment is set from 1 to 1.25 from the outside to the center. The wafer surface of the cobalt film formed by using a collimator (uniform aspect collimator) in which the film thickness distribution in the wafer surface and the aspect ratio of the large number of control holes investigated by the present inventors are uniformly set throughout. The film thickness distribution is shown. The cobalt film is formed by the sputtering apparatus 100 described above.

  In the collimator studied by the present inventors, the film thickness of the cobalt film in the central portion of the wafer tends to be thicker than that in the peripheral portion, and the uniformity of the film thickness distribution in the wafer surface becomes ± 3.1%. On the other hand, in the collimator according to the present embodiment, the tendency of increasing the film thickness of the cobalt film in the central portion of the wafer is eliminated, and the uniformity of the film thickness distribution in the wafer surface is improved to ± 0.8%. The

  11A is a wafer surface thickness distribution table showing the film thickness distribution in the wafer surface of the cobalt silicide layer formed by the silicide reaction. FIG. 11B shows the measurement position on the wafer. It is a schematic plan view shown. In FIG. 11A, a cobalt film is formed by using a collimator (vertical symmetrical convex lens type collimator) in which the aspect ratio of a large number of control holes according to this embodiment is set from 1 to 1.25 from the outside to the center. Using a collimator in which the film thickness distribution in the wafer surface of the cobalt silicide layer formed by the silicidation reaction using this and the aspect ratio of the numerous control holes investigated by the present inventors were uniformly set throughout. The film thickness distribution in the wafer surface of the cobalt silicide layer formed by the silicide reaction using the cobalt film is shown. The cobalt film is formed by the sputtering apparatus 100 described above. In all the samples, a cobalt silicide layer is formed on the polycrystalline silicon film under the same conditions, and n-type impurities or p-type impurities having the same concentration are added to the polycrystalline silicon film.

  In the collimator investigated by the present inventors, the film thickness of the cobalt silicide layer in the central portion of the wafer tends to be thicker than that in the peripheral portion, and the uniformity of the film thickness distribution in the wafer surface becomes ± 6.11%. . On the other hand, in the collimator (vertically symmetrical convex lens type collimator) according to the present embodiment, the tendency of increasing the thickness of the cobalt silicide layer in the central portion of the wafer is eliminated, and the uniformity of the film thickness distribution in the wafer surface is eliminated. Improved to ± 2.6%. 10 and 11 that the thickness of the cobalt film is directly reflected in the thickness of the cobalt silicide layer.

  Next, as shown in FIG. 12, a titanium nitride (TiN) film (second film) 14 having a thickness of about 10 to 20 nm is deposited on the cobalt film 13. The titanium nitride film 14 is used as an oxidation barrier film that prevents the surface of the cobalt film 13 from being oxidized in the process of forming the cobalt silicide layer. In addition to the titanium nitride film 14, a metal nitride compound film such as a tungsten nitride (WN) film or a tantalum nitride (TaN) film can also be used as the oxidation barrier film. The titanium nitride film 14 is deposited at a low temperature so that the silicide reaction between the substrate 1 and the cobalt film 13 deposited on the surface thereof does not proceed rapidly.

  As shown in FIG. 13, a titanium (Ti) film (third film) 15 having a thickness of about 5 to 10 nm may be deposited on the titanium nitride film 14. Since the titanium nitride film 14 becomes columnar crystals by heat treatment, it is presumed that the function as an antioxidant film is insufficient due to permeation of oxygen, and the cobalt film 13 is slightly oxidized. Therefore, the titanium film 15 is formed on the surface of the titanium nitride film 14 and the oxygen trap effect of the titanium film 15 is used to improve the oxidation preventing effect of the cobalt film 13.

  In some cases, the titanium nitride film 14 (or the laminated film of the titanium nitride film 14 and the titanium film 15) is not deposited. For example, when the film formation of the cobalt film 13 and the heat treatment to be described later are continuously performed using a single wafer type multi-chamber sputtering apparatus, the wafer 1 can be moved without being exposed to the outside air. The functioning titanium nitride film 14 (or a laminated film of the titanium nitride film 14 and the titanium film 15) is not necessarily required.

Next, by performing heat treatment (first annealing; first heat treatment) on the wafer 1 in a non-oxidizing gas atmosphere, the dicobalt silicide (Co ₂ Si) layer 16a is mainly formed as shown in FIG. The silicide layer as a component is converted into a cobalt monosilicide (CoSi) layer 16b. In this heat treatment, the silicide reaction rapidly proceeds at the interface between the source / drain (n ⁺ type semiconductor region 11, p ⁺ type semiconductor region 12) and the cobalt film 13 and at the interface between the gate electrode 7 and the cobalt film 13. A temperature (first temperature) at which the side (CoSi) layer is converted into the silicide layer 16b having the main component and cobalt disilicide (CoSi ₂ ) is not substantially generated, specifically 400 ° C. As described above, it is desirable to carry out in a temperature range below 600 ° C. (surface temperature of the wafer 1). In this embodiment, the surface temperature of the wafer 1 is set to, for example, 450 ° C. as a nitrogen gas atmosphere, and RTA (Rapid Thermal Anneal) type heat treatment is performed, for example, for 90 seconds.

Next, as shown in FIG. 15, the wafer 1 is wet-etched using a mixed solution of ammonia (NH ₃ ) and hydrogen peroxide (H ₂ O ₂ ) to form a titanium nitride film 14 (or titanium nitride film 14 and titanium film). Then, the unreacted cobalt film 13 is removed by wet etching using a mixture of hydrochloric acid (HCl) and hydrogen peroxide. When the titanium nitride film 14 (or the laminated film of the titanium nitride film 14 and the titanium film 15) is not deposited on the cobalt film 13, a mixed acid (phosphoric acid (H ₃ PO ₄ ), nitric acid (HNO ₃ ), and acetic acid ( The unreacted cobalt film 13 is removed by wet etching using a mixed solution of CH ₃ COOH)) and hydrogen peroxide.

Next, by performing a heat treatment (second annealing; second heat treatment) on the wafer 1 in a non-oxidizing gas atmosphere, the cobalt monosilicide (CoSi) layer 16b as a main component is formed as shown in FIG. The silicide layer to be converted is converted into a cobalt disilicide (CoSi ₂ ) layer 16. This heat treatment is desirably performed at a temperature (second temperature) higher than that of the first annealing, specifically, a temperature range of 600 ° C. or higher and lower than 850 ° C. (surface temperature of the wafer 1). In this embodiment, the surface temperature of the wafer 1 is set to, for example, 745 ° C. as a nitrogen gas atmosphere, and RTA heat treatment is performed, for example, for 30 seconds. A process for forming a silicide layer in which cobalt is deposited at a relatively low temperature is described in Japanese Patent Application No. 2002-361700 (filed on Dec. 13, 2002) by Ichinose et al. There is a corresponding US application Ser. No. 10 / 733,377 (US filing date 12/12/2003).

The thickness of the cobalt disilicide layer formed by the silicide reaction is approximately 3.5 times the thickness of the cobalt film (Silicon VLSI Technology, James D. Plummer et. Al, Department of Electrical Engineering Stanford University (Table 11- See 5)). When the thickness of the cobalt film 13 is 10 nm, the thickness of the cobalt disilicide layer 16 is about 35 nm. In this embodiment, the junction depth of the pn junction of the source and drain (n ⁺ type semiconductor region 11 and p ⁺ type semiconductor region 12) is about 50 to 300 nm, and the cobalt silicide layer 16 is formed at the pn junction. Not reach.

  In order to prevent the occurrence of leakage current at the pn junction, it is necessary to separate the cobalt disilicide layer 16 from the pn junction by about 10 nm or more. As described above, when the thickness of the cobalt film 13 is not uniform, the thickness of the cobalt disilicide layer 16 is also not uniform. For this reason, in the region where the cobalt film 13 is formed thick, the cobalt disilicide layer 16 becomes thicker than the design value, and approaches or contacts the pn junction to generate a leakage current. However, in this embodiment, since the film thickness uniformity in the wafer surface of the cobalt film 13 is improved, the cobalt disilicide layer 16 having a uniform thickness is formed in the wafer surface. The distance from 16 to the pn junction can be secured, and the occurrence of leakage current at the pn junction can be prevented.

Through the steps so far, the interface between the source and drain (n ⁺ type semiconductor region 11 and p ⁺ type semiconductor region 12) formed on the substrate 1 and the cobalt film 13, and the gate electrode 7 made of a polycrystalline silicon film and cobalt A silicide layer mainly composed of a cobalt disilicide (CoSi ₂ ) layer 16 is formed at the interface with the film 13 to complete nMISQn and pMISQp.

Thereafter, as shown in FIG. 17, a silicon nitride film 17 and a silicon oxide film 18 are deposited on the substrate 1 by the CVD method, and then the source and drain (n ⁺ type semiconductor region 11 and p ⁺ type semiconductor region 12) are formed. After each of the upper silicon oxide film 18 and silicon nitride film 17 is dry-etched to form a contact hole 19, a tungsten (W) wiring 20 is formed on the silicon oxide film 18 including the inside of the contact hole 19.

  Furthermore, a wiring plug for filling the contact hole is formed by using a dry etching method or a CMP method. Subsequently, a titanium film and a titanium nitride film are sequentially deposited by a sputtering method, and aluminum / copper (a metal containing aluminum as a main component) in an inert atmosphere such as nitrogen at a temperature of about 300 ° C., for example. Wiring material) is formed, an aluminum alloy film is formed as a wiring metal film between the semiconductor elements, and a laminated wiring layer is formed.

  As described above, according to the present embodiment, in the collimated sputtering method, the aspect ratio of the large number of control holes 117 provided in the collimator 115 is continuously increased from the peripheral part to the central part of the collimator 115, thereby 115, the amount of cobalt atoms passing through the control hole 117 located in the peripheral portion of the 115 can be controlled more than the cobalt atoms passing through the control hole 117 located in the central portion. The thickness distribution can be made uniform throughout. As a result, the leakage current of the pn junction generated when the cobalt disilicide layer 16 is formed thicker than necessary can be reduced.

  Further, in the collimated sputtering method with the non-uniform aspect ratio, the cobalt film 13 is formed on the wafer 1 at a temperature range of 300 ° C. or more, and at the same time, the interface between the cobalt film 13 and the substrate 1 and the cobalt film 13 are formed. By flattening the interface with the gate electrode 7, the thickness of the cobalt disilicide layer 16 formed by the silicide reaction in the wafer surface can be made more uniform, and the leakage current of the pn junction can be increased. Can be prevented.

  Further, by forming a titanium nitride film 14 or a laminated film of the titanium nitride film 14 and the titanium film 15 on the cobalt film 13 formed by the collimated sputtering method, oxidation of the cobalt film 13 is prevented in the subsequent heat treatment. In addition, the low resistance cobalt disilicide layer 16 can be formed by a silicide reaction.

  Further, in the collimated sputtering method, by setting the thickness of the cobalt film 13 in the range of 3 nm to 20 nm, the effect of reducing the resistance by the cobalt disilicide layer 16 formed by the silicide reaction can be obtained, and the cobalt disilicide is also provided. The thickness of the layer 16 can be made shallower than the pn junction, and an increase in leakage current can be prevented.

  In the present embodiment, the shape of the collimator 115 is thick at the center and gradually thins from the central part to the peripheral part, and the aspect ratio of the large number of control holes 117 is continuous from the central part to the peripheral part of the collimator 115. Although the film thickness distribution in the wafer surface of the cobalt film 13 formed on the wafer 1 is uniformly controlled by reducing the thickness, the film in the wafer surface of the cobalt film 13 formed on the wafer 1 is controlled. The aspect ratio may be set according to the tendency of the thickness distribution.

  For example, when the film thickness distribution of the cobalt film 13 in the wafer surface is thick at the peripheral portion of the wafer 1 and becomes non-uniform because it tends to be thin at the central portion of the wafer 1, the shape of the collimator 115 is thin at the center and from the central portion. The thickness is gradually increased toward the periphery, and the upper surface and the lower surface of the main body 116 are vertically symmetric, for example, like a concave lens, so as to be vertically symmetric (vertically symmetric concave lens collimator). As a result, the aspect ratio of the large number of control holes 117 continuously increases from the central portion to the peripheral portion of the collimator 115, and the film thickness distribution in the wafer surface of the cobalt film 13 formed on the wafer 1 is made uniform. Can be controlled.

  FIG. 18 shows sectional views of the lens-type collimator according to the present embodiment and various collimators studied by the present inventors.

  The uniform aspect collimator 130 examined by the present inventors shown in FIG. 18C has a substantially uniform thickness and includes a large number of control holes 131 having an aspect ratio of 1, for example. On the other hand, the collimator 115 according to the present embodiment is thick at the center and gradually thins from the central part to the peripheral part as shown in FIG. A large number of control holes 117 changing continuously from 1 to 1.25 are provided. Further, the collimator 120 according to the present embodiment is thin at the center, and gradually increases from the center to the periphery, so that the aspect ratio continuously changes from 1.25 to 1, for example, from the outside to the center. Each control hole 121 is provided.

  Further, the aspect ratio of the large number of control holes 117 is not continuously reduced or increased from the central portion to the peripheral portion of the collimator 115, but is adjusted to the film thickness of the cobalt film 13 required on the wafer 1, The aspect ratio of the region may be decreased or increased, or may be continuously decreased or increased from a part of the region to the periphery thereof.

  For example, since the surface of the target 108 is shaved unevenly by sputtering, the film thickness distribution or deposition rate of the cobalt film 13 in the wafer surface gradually changes as sputtering is continued. Therefore, a plurality of collimators 115 having a large number of control holes 117 whose aspect ratios are adjusted according to the scraped state of the target 108 are prepared, and sputtering is performed by exchanging the collimator 115 according to the scraped state of the target 108. Good. As a result, fluctuations in the film thickness distribution in the wafer surface or the film formation speed of the cobalt film 13 caused by the target 108 being scraped can be suppressed.

  For example, a collimator 115 having a large number of control holes 117 whose aspect ratio is adjusted in accordance with the temperature distribution of the heat treatment (for example, the first annealing) may be used (that is, the temperature distribution in the wafer during the first annealing is canceled out). Use a non-uniform aspect ratio collimator to give such a cobalt deposition distribution). Although the film thickness of the cobalt film 13 formed on the wafer 1 in the wafer surface is not uniform, the thickness of the cobalt disilicide layer 16 formed by the silicide reaction can be made uniform.

In this embodiment, the cobalt film 13 is used to form the silicide layer. However, the present invention is not limited to this. For example, a nickel (Ni) film or a cobalt nickel (CoNi) alloy film may be used. . The nickel film becomes a nickel monosilicide (NiSi) layer by a silicide reaction, and the thickness of the nickel disilicide layer is about 2.3 times the thickness of the nickel film. The cobalt nickel film becomes a cobalt disilicide (CoSi ₂ ) layer by a silicide reaction. The cobalt nickel film can use, for example, a Co content of 98% and a Ni content of 2%, but nickel is slightly contained in the cobalt disilicide layer as an impurity. Regarding the nickel addition technology, there is PCT International Publication Specification WO00 / 17939 (International Publication Date March 30, 2000) by Shimadzu et al.

  In the present embodiment, the first annealing and the second annealing are performed using an RTA apparatus other than the sputtering apparatus 100. However, continuous processing may be performed using, for example, a single wafer multi-chamber sputtering apparatus. In this apparatus, the wafer 1 can be moved between the chambers without being exposed to the outside air. Therefore, an oxidation resistant barrier film (a titanium nitride film 14 or a laminated film of the titanium nitride film 14 and the titanium film 15) is indispensable. Absent. In general, it is said that the processing at different processing temperatures has a higher throughput when performed in another apparatus or in another chamber of the same apparatus. Conversely, when processing in the same chamber of the same apparatus, there is an advantage that many wafers can be processed with a small number of apparatuses.

  In the present embodiment, a DC magnetron sputtering apparatus has been exemplified. However, the present invention is not limited to this, and other collimation sputtering apparatuses may be used.

  Further, a technique for making the deposited film distribution uniform by devising control of the magnet of the magnetron sputtering apparatus (magnetic field change control) may be used.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in this embodiment, the case where the present invention is applied to a method for manufacturing a CMOS integrated circuit has been described. However, the present invention can be applied to any method for manufacturing a semiconductor integrated circuit device having a silicide layer formed by a salicide process. Furthermore, the present invention can be applied to film forming techniques in general, such as when forming a film on a printed wiring board, when forming a film on a liquid crystal panel, or when forming a film on a magnetic disk or a compact disk.

  The method for manufacturing a semiconductor integrated circuit device of the present invention is suitable for application to a salicide process in which a silicide layer is formed using a metal film formed by sputtering.

It is principal part sectional drawing of the semiconductor substrate which shows an example of the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows an example of the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows an example of the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is a schematic sectional drawing of the sputtering device used for formation of the cobalt film which is one embodiment of this invention. The collimator used for the sputtering device which is one embodiment of this invention is shown, (a) is a schematic plan view, (b) is a schematic sectional drawing in the aa 'line | wire of the same figure (a). . It is a process sequence diagram which shows an example of the time change of the wafer temperature at the time of forming the cobalt film which is one embodiment of this invention by sputtering method, argon gas flow volume, and DC power. It is principal part sectional drawing of the semiconductor substrate which shows an example of the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is a figure which shows the relationship between the sheet resistance defect rate of the polycrystalline silicon film in which the cobalt silicide layer was formed, and the surface temperature of the wafer at the time of depositing a cobalt film. It is principal part sectional drawing of the semiconductor substrate which shows an example of the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. (A) is a film thickness distribution table in the wafer surface showing the film thickness distribution in the wafer surface of the cobalt film formed on the dummy wafer, and (b) is a schematic plan view showing the measurement position on the wafer. . (A) is a film thickness distribution table in the wafer surface showing the film thickness distribution in the wafer surface of the cobalt silicide layer formed by the silicide reaction, and (b) is a schematic plan view showing the measurement position on the wafer. is there. It is principal part sectional drawing of the semiconductor substrate which shows an example of the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the other example of the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows an example of the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows an example of the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows an example of the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows an example of the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. (A) And (b) is sectional drawing of the collimator which is one embodiment of this invention, (c) is sectional drawing of the collimator which the present inventors examined.

Explanation of symbols

1 Semiconductor substrate (semiconductor wafer)
2 element isolation trench 3 silicon oxide film 4 p-type well 5 n-type well 6 gate oxide film 7 gate electrode 8 n ⁻ type semiconductor region 9 p ⁻ type semiconductor region 10 sidewall 11 n ⁺ type semiconductor region (source, drain)
12 p ⁺ type semiconductor region (source, drain)
13 Cobalt film 14 Titanium nitride film 15 Titanium film 16a Dicobalt silicide layer 16b Cobalt monosilicide layer 16 Cobalt disilicide layer 17 Silicon nitride film 18 Silicon oxide film 19 Contact hole 20 Tungsten wiring 100 Sputtering apparatus 101 Sputtering chamber 102 Vacuum vessel 103 Carrying in Unloading port 104 Gate valve 105 Argon gas 106 Gas supply pipe 107 Backing plate 108 Target 109 Lift 110 Electrostatic chuck 111 Lower shield 112 Upper shield 113 Magnet plate 114 Rotating shaft 115 Collimator 116 Main body 117 Control hole 120 Collimator 121 Control hole 130 Collimator 131 Control hole Qn n-channel MIS • FET
Qp p-channel MIS • FET

Claims (20)

A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) forming an element isolation region on the first main surface of the wafer to partition a silicon active region surrounded by the device isolation region;
(B) a step of partitioning the source / drain regions by forming gate electrodes having sidewall spacers on both sides via a gate insulating film on the silicon active region;
(C) The element isolation region and the source of the first main surface of the wafer by collimated sputtering in which a mechanical collimator having a large number of openings with non-uniform aspect ratio is interposed between the wafer and the cobalt target. The temperature of the first main surface of the wafer is set to the silicon surface and the polysilicon on the silicon surface of the drain region, the sidewall spacer of the gate electrode, and the polysilicon surface constituting the upper surface of the gate electrode. A first temperature range in which a first silicide film having dicobalt silicide (Co ₂ Si) as a main component is formed on the surface and a silicide film having cobalt monosilicide (CoSi) as a main component is substantially not formed. Forming a cobalt film in a controlled state;
(D) a step of converting the first silicide film into a second silicide film containing cobalt monosilicide as a main component by a first heat treatment;
(E) After the step (d), a step of removing an unreacted portion of the cobalt film;
(F) After the step (e), a step of converting the second silicide film into a third silicide film containing cobalt disilicide (CoSi ₂ ) as a main component by a second heat treatment.   2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the first temperature range is not less than 300 degrees Celsius and less than 450 degrees Celsius.   2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the first temperature range is 350 degrees centigrade or more and less than 450 degrees centigrade.   2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the first temperature range is not less than 400 degrees Celsius and less than 450 degrees Celsius.   2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the first temperature range is not less than 300 degrees Celsius and less than 400 degrees Celsius.   2. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the collimator is substantially rotationally symmetric and is substantially plane symmetric with respect to a symmetry plane perpendicular to the axis of rotation.   2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the plurality of openings are regular hexagons having substantially the same opening area, and are arranged so as to form a substantially hexagonal close-packed lattice.   2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein an aspect ratio change rate of the collimator is less than 98% and 50% or more.   2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the partition walls of the plurality of openings of the collimator are substantially parallel to a straight line connecting the center of the wafer and the center of the cobalt target.   2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein an aperture ratio of a portion of the collimator facing the wafer is 85% or more. A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) forming an element isolation region on the first main surface of the wafer to partition a silicon active region surrounded by the device isolation region;
(B) a step of partitioning the source / drain regions by forming gate electrodes having sidewall spacers on both sides via a gate insulating film on the silicon active region;
(C) The element isolation region and the source of the first main surface of the wafer by collimated sputtering in which a mechanical collimator having a large number of openings with non-uniform aspect ratio is interposed between the wafer and the cobalt target. The temperature of the first main surface of the wafer is set to 300 ° C. or more and 450 ° C. on the silicon surface of the drain region, the side wall spacer of the gate electrode, and the polysilicon surface constituting the upper surface of the gate electrode. Forming a cobalt film in a controlled state within a first temperature range of less than
(D) After the step (c), a first heat treatment is performed in a state where the temperature of the first main surface of the wafer is controlled within a second temperature range of 400 degrees Celsius or more and less than 600 degrees Celsius. Process;
(E) After the step (d), a step of removing an unreacted portion of the cobalt film;
(F) After the step (e), a second heat treatment is performed in a state where the temperature of the first main surface of the wafer is controlled within a third temperature range of 600 degrees Celsius or more and less than 850 degrees Celsius. Process.   12. The method of manufacturing a semiconductor integrated circuit device according to claim 11, wherein the first temperature range is 350 degrees centigrade or more and less than 450 degrees centigrade.   12. The method of manufacturing a semiconductor integrated circuit device according to claim 11, wherein the first temperature range is not less than 400 degrees Celsius and less than 450 degrees Celsius.   12. The method of manufacturing a semiconductor integrated circuit device according to claim 11, wherein the first temperature range is not less than 300 degrees Celsius and less than 400 degrees Celsius.   12. The method of manufacturing a semiconductor integrated circuit device according to claim 11, wherein the collimator is substantially rotationally symmetric and is substantially plane symmetric with respect to a symmetry plane perpendicular to the axis to be rotated.   12. The method of manufacturing a semiconductor integrated circuit device according to claim 11, wherein the plurality of openings are regular hexagons having substantially the same opening area, and are arranged so as to form a substantially hexagonal close-packed lattice.   12. The method of manufacturing a semiconductor integrated circuit device according to claim 11, wherein an aspect ratio change rate of the collimator is less than 98% and 50% or more.   12. The method of manufacturing a semiconductor integrated circuit device according to claim 11, wherein the partition walls of the plurality of openings of the collimator are substantially parallel to a straight line connecting the center of the wafer and the center of the cobalt target.   12. The manufacturing method of a semiconductor integrated circuit device according to claim 11, wherein an aperture ratio of a portion of the collimator facing the wafer is 85% or more. A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) A mechanical collimator having a large number of apertures with a non-uniform aspect ratio, the base material of which has a coating layer whose main component is other than aluminum and whose main component is aluminum. By means of collimated sputtering interposed between the wafer and a target containing cobalt or nickel as a main component, cobalt or nickel is mainly used on the element isolation region of the first main surface of the wafer and the silicon surface of the source / drain region. A step of forming a metal film as a component.

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