JP2007258578A - Group III nitride compound semiconductor p-type method, insulation isolation method, group III nitride compound semiconductor, and transistor using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for making a p-type semiconductor out of a group III nitride compound semiconductor and an element having the p-type region. <P>SOLUTION: Magnesium (Mg) is partially injected into a group III nitride compound semiconductor on a plane surface, and thereafter, the magnesium is thermally diffused in a horizontal direction on the plane surface and in a direction vertical to the plane surface, thus making the diffused region a p-type region. Then, silicon (Si) is added to the injected area to form an n-type region. This can exclude an injected area of high resistance. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

The present invention relates to a p-type method for a group III nitride compound semiconductor, a group III nitride compound semiconductor having a p-type region, and a transistor having the p-type region.
The present invention also relates to an insulation separation method for a group III nitride compound semiconductor device.

  As a method for converting a group III nitride compound semiconductor into a p-type, when a group III nitride compound semiconductor is vapor-phase grown by MOCVD, the organic layer containing Mg is introduced into the semiconductor layer in which Mg is grown while flowing. There is a way. In this method, it is necessary to activate Mg by releasing heat by performing heat treatment at 600 ° C. to 800 ° C. in a nitrogen atmosphere in a subsequent step. That is, a post-process for p-type conversion was necessary.

  In addition, as shown in Patent Document 1 below, in a GaN substrate having a surface perpendicular to the c-axis as a main surface, Mg is ion-implanted uniformly in the plane and thermally diffused in the depth direction perpendicular to the c-axis. A method of forming a p-type layer below the ion-implanted layer is known.

  Further, as a method for insulating isolation of a group III nitride compound semiconductor device, a method of forming a high resistance region by ion implantation of a group II atom having an atomic number of 20 or more as described in Patent Document 2 below. It has been known. In this method, lattice defects are generated at a high density by ion implantation of heavy atoms to increase the probability of capturing electrons, thereby making the ion implantation region a high resistance region. In addition, a method of obtaining high resistance by capturing electrons by annealing after ion implantation of group II atoms, substituting the group II atoms with Ga and Al atoms, and generating acceptors is shown.

  Further, in Patent Document 3 below, Mg is ion-implanted uniformly in a GaN substrate having a surface perpendicular to the c-axis as a main surface, and is thermally diffused in a depth direction perpendicular to the c-axis. A method is disclosed in which a p-type layer is formed below the implantation layer, and the upper ion implantation layer is removed by etching. The reason why the direction perpendicular to the c-axis is the ion implantation direction is that the diffusion coefficient in that direction is large.

JP-A-2004-288754 JP 2004-95640 A JP-A-2004-288754

  According to the method of Patent Document 1, a lower layer than the ion-implanted layer is a p-type layer, and the ion-implanted layer has poor crystallinity and high resistance and cannot be used as a layer for forming a current path or an electrode. Etching is removed. However, the group III nitride compound semiconductor has a problem that it is difficult to etch, and in reality, it is difficult to remove the ion-implanted layer. Forcibly, when etching is performed with a KOH solution heated at 600 ° C., K ions adhere to the surface, causing current leakage in the surface insulating film.

  Further, according to the method of Patent Document 1, a p-layer can be formed uniformly in a plane, but a partial region in the layer cannot be a p-type region. That is, it is difficult to manufacture a device that requires a fine p-type region such as a transistor.

  In the method of Patent Document 2 described above, if the lattice defect density is too high, the resistivity decreases due to hopping conduction conducted through the defect center. Therefore, in order to avoid this, the defect density is reduced by annealing. Further, if annealing is performed excessively, the lattice defect density is excessively lowered and the resistance is decreased. Thus, an acceptor is generated by annealing, thereby increasing the electron capture density and increasing the resistance.

  In Patent Document 2, ion implantation of Mg is excluded. Since Mg forms a shallow acceptor level by annealing, it cannot be used for insulation isolation as described above in order to make it p-type by going through the reduction of n-type resistance. There is no suggestion.

  On the other hand, Patent Document 3 discloses a method of ion-implanting Mg and thermally diffusing Mg below the region to make it p-type. However, there is a suggestion regarding insulation isolation of a semiconductor device. Absent.

The present invention has been made to solve the above-described problems, and is to make a group III nitride compound semiconductor p-type without etching.
Another object of the invention is to be able to provide a device such as a transistor by making it partially p-type.
Another object of the invention is to realize a group III nitride compound semiconductor device having a fine p-type region.
Another object of the present invention is to provide a method of effectively insulating and isolating a group III nitride compound semiconductor device and a group III nitride compound semiconductor device that is insulated and separated.

  According to a first aspect of the present invention, there is provided a method for converting a group III nitride compound semiconductor to a p-type, wherein magnesium (Mg) is partially ion-implanted into a group III nitride compound semiconductor on a plane. Thereafter, magnesium (Mg) is thermally diffused in a horizontal direction on the plane and in a direction perpendicular to the plane, thereby converting the diffusion region into a p-type, and a method for converting the group III nitride compound semiconductor into a p-type It is.

  Here, it is desirable that magnesium (Mg) ions be implanted in a lattice island shape, a lattice shape, or a stripe shape on a plane in a region to be p-type. The present invention is characterized in that Mg is ion-implanted partially in a certain region and then thermally diffused, so that the region to be ion-implanted is discrete on the surface so that it can also be diffused in the horizontal direction. As long as it is formed, the shape of the region is not limited. However, by ion-implanting Mg into stripes, lattice islands, or lattices, the high-resistance region into which the Mg is implanted is made into a micro-region or a mesh with respect to the p-type region. The influence of can be eliminated.

  Further, an n-type region may be formed by adding a donor impurity to a region where magnesium (Mg) is partially ion-implanted or a portion including the region. That is, since the region into which Mg ions are implanted becomes a high resistance region, the high resistance region can be eliminated by adding a donor impurity to this region and converting it to n-type. In addition, this portion can be a region such as a source, an emitter, a drain, or a collector in a transistor.

According to a fourth aspect of the present invention, in the method for converting a group III nitride compound semiconductor to p-type, magnesium (Mg) is ion-implanted into the group III nitride compound semiconductor, and then the magnesium (Mg) is heated. The group III nitride compound semiconductor is characterized in that it is diffused to make the diffusion region p-type, and thereafter, a donor impurity is added to the ion-implanted region or a portion including the region to make it n-type. It is a method of typing.
That is, in the present invention, Mg ion implantation may be arbitrarily diffused in the plane direction but is not essential. That is, Mg ion implantation may be performed uniformly on a plane and thermally diffused only in the depth direction to form a p-type region below the implanted region. Then, a donor impurity is added to the implantation region to form an n-type region. Thereby, a pn junction layer composed of a p-type layer on the lower side and an n-type layer on the upper side can be formed.

According to a fifth aspect of the present invention, in the method for converting a group III nitride compound semiconductor to p-type, magnesium (Mg) is ion-implanted into a first layer made of a group III nitride compound semiconductor, and the first A second layer made of a group III nitride compound semiconductor is grown on the layer, and magnesium (Mg) in the first layer is thermally diffused into the second layer to make the second layer p-type. Is a method for converting a group III nitride compound semiconductor to p-type.
In this method, the layer (upper side) for crystal growth later than the ion-implanted layer is made p-type. That is, Mg is ion-implanted into the crystal growth layer, another group III nitride compound semiconductor is crystal-grown on the layer, and Mg is thermally diffused to be p-type. For example, even if the layer into which Mg is ion-implanted remains as a layer exhibiting high resistance, the layer close to the substrate can be used for a device having the upper layer of the substrate as an element region. In this case, it is not necessary to perform etching.

  Note that magnesium (Mg) ion implantation is desirably performed in the form of lattice islands, lattices, or stripes on the plane of the first layer.

Further, the invention of claim 7 is directed to a diffusion region in which magnesium (Mg) is partially ion-implanted on a plane, and magnesium (Mg) is thermally diffused from the implantation region in a horizontal direction on the plane and in a direction perpendicular to the plane. Then, a p-type region converted into p-type, an injection region in which magnesium (Mg) is partially ion-implanted, and a p-type region converted into p-type by thermally diffusing magnesium (Mg) from the injected region. It is a group III nitride compound semiconductor characterized by having.
That is, the present invention is a semiconductor having a planar p-type region and an implantation region into which Mg that is partially present therein is ion-implanted in a horizontal sectional view.

The invention according to claim 8 is the group III nitride according to claim 7, wherein the p-type region forms a planar layer and has an n-type layer formed on the layer. A compound semiconductor.
The invention according to claim 9 is the group III nitride according to claim 7 or 8, wherein the implanted region or a region including the implanted region is an n-type region to which a donor impurity is added. It is a physical compound semiconductor.
The invention of claim 10 includes an implantation region into which magnesium (Mg) is ion-implanted, a p-type region in which magnesium (Mg) is thermally diffused from the implantation region, and a p-type region, and an implantation region or an implantation thereof. A group III nitride compound semiconductor comprising an n-type region doped with a donor impurity in a region including the region and made into an n-type region.
That is, a semiconductor in which an n-type region is formed in a p-type region, with the implantation region being an n-type region.

Furthermore, the invention of claim 11 is a transistor made of a group III nitride compound semiconductor, which is an implantation region into which magnesium (Mg) is partially ion-implanted, and is an n-type emitter / doped emitter impurity. A source region, a p-type base / channel region formed around the emitter / source region and made into p-type by thermally diffusing magnesium (Mg) from the implantation region; A transistor having an n-type collector / drain region formed.
As the transistor, an arbitrary transistor having a p-type region or an n-type region such as a horizontal or vertical field effect transistor such as HEMT, MESFET, or MOSFET, or a vertical IGBT, horizontal or vertical junction type transistor, or the like is used. be able to.

  Furthermore, the invention of claim 12 for solving the above-mentioned problem is a method for insulating and isolating a group III nitride compound semiconductor device, wherein the isolation region in the n-type group III nitride compound semiconductor is provided with magnesium (Mg). Is a method for insulating and separating a group III nitride compound semiconductor device, characterized in that a pn junction surface is formed by thermally implanting ions into the periphery and subsequently forming a p-type region by annealing. .

  The isolation region of the present invention is formed around the element region if it is used for element isolation. Therefore, it is desirable that Mg is uniformly ion-implanted in a partition region having a certain width on the surface of the substrate. However, since the p-type region is formed by thermal diffusion, Mg may be ion-implanted in a lattice island shape, a lattice shape, or a stripe shape in this partition region. In addition, in the case of insulating separation in the depth direction, a separation region is formed in a planar shape parallel to the substrate surface. Also in this case, the ion implantation of Mg may be performed uniformly on the substrate plane, or may be performed in a lattice island shape, a lattice shape, or a stripe shape.

  Further, the invention of claim 14 is directed to a group III nitride compound semiconductor device in which a magnesium (n-type group III nitride compound semiconductor and magnesium formed in a separation region of an n type group III nitride compound semiconductor ( Mg) ion-implanted regions, and p-type regions formed by thermally diffusing magnesium (Mg) in the implanted regions into the surrounding n-type group III nitride compound semiconductor, The group III nitride compound semiconductor device is characterized in that it is insulated and separated by a pn junction comprising a group III nitride compound semiconductor and a p-type region.

  That is, according to the present invention, Mg is ion-implanted into an n-type Group III nitride compound semiconductor and thermally diffused to form a p-type region and form a pn junction surface. This is a group III nitride compound semiconductor device having a structure.

  The invention of claim 15 is the group III nitride compound semiconductor device according to claim 14, wherein the implantation region is formed in a lattice island shape, a lattice shape, or a stripe shape. .

  In a first invention for solving the above problem, magnesium (Mg) is partially ion-implanted on a plane, and then magnesium (Mg) is thermally diffused in a horizontal direction on the plane and in a direction perpendicular to the plane. Since the diffusion region is made p-type, the ion-implanted high resistance region is formed dispersed in the diffusion region. For this reason, the presence of the high resistance region does not affect the element characteristics, and it is not necessary to remove the high resistance region. Moreover, an etching process becomes unnecessary.

In the invention of claim 2, since the ion implantation of magnesium (Mg) is performed in a lattice island shape, a lattice shape, or a stripe shape on a plane, the p-type is formed by thermal diffusion after the ion implantation. In the region, the high resistance region can be effectively dispersed.
In the invention of claim 3, since an n-type region is formed by adding a donor impurity to a region in which magnesium (Mg) is partially ion-implanted or a portion including the region. The resistance region can be eliminated. In other words, the high resistance region can be eliminated by forming the pn junction by converting the ion implantation region to n-type.

  In the invention of claim 4, magnesium (Mg) is ion-implanted into a group III nitride compound semiconductor, and then magnesium (Mg) is thermally diffused to make the diffusion region p-type. Since a donor impurity is added to the implanted region or a portion including the region to make it n-type, a pn junction layer having a p-type layer from the lower side and a n-type layer thereon on the group III nitride compound semiconductor Can be formed.

  According to the invention of claim 5, a second layer made of a group III nitride compound semiconductor is grown on the first layer into which magnesium (Mg) has been ion-implanted, and the second layer includes By thermally diffusing magnesium (Mg), the second layer is made p-type, whereby a p-type layer can be formed on the high resistance region. In other words, if the layer on the surface side of the element is a functional layer, the element can be realized even if there is a high resistance layer below the element. Therefore, the p-type is used for this type of element without using etching. The present invention can be used to form layers.

  Further, according to the invention of claim 6, since the ion implantation of Mg is performed in the form of lattice islands, lattices, or stripes on the plane of the first layer, the high resistance region can be dispersed, The influence on the element can be eliminated.

  According to the invention of claim 7, the magnesium (Mg) is ion-implanted partially on the plane, and the magnesium (Mg) is heated from the implantation area in the horizontal direction on the plane and in the direction perpendicular to the plane. Since it has a p-type region that has been diffused into a p-type, the influence of the presence of the high-resistance injection region on the device can be reduced.

According to the invention of claim 8, the p-type region forms a planar layer and has an n-type layer formed on the layer, whereby various devices can be formed.
According to the invention of claim 9, an element having a pn junction is obtained by eliminating the high resistance region by making the implanted region or the region including the implanted region an n-type region to which a donor impurity is added. Can be formed.

  According to the invention of claim 10, an implantation region into which magnesium (Mg) is ion-implanted, a p-type region in which magnesium (Mg) is thermally diffused from the implantation region to form a p-type, and an implantation region or an implantation region thereof Since the n-type region is formed by adding a donor impurity to the region including n-type region, a semiconductor having a p-type layer on the lower side and a pn junction layer on which the n-type layer is arranged on the upper side, Can be used for devices.

  According to the eleventh aspect of the present invention, an implantation region into which magnesium (Mg) is partially ion-implanted includes an n-type emitter / source region to which a donor impurity is added, and an emitter / source region. A p-type base / channel region in which magnesium (Mg) is thermally diffused from an implantation region formed in the substrate, and an n-type collector / drain region formed outside the base / channel region. Thus, a transistor using a group III nitride compound semiconductor can be realized.

  According to the inventions of claims 12 and 14, magnesium (Mg) is ion-implanted into the isolation region in the n-type group III nitride compound semiconductor, and thereafter, thermal diffusion is performed by annealing to form a p-type region. By doing so, a pn junction surface can be formed, and insulation can be isolated by the pn junction surface. In addition, since the Mg ion implantation region inside the p-type region remains high in resistance, this portion also contributes to insulation isolation. In this way, insulation isolation can be realized in a group III nitride compound semiconductor without using a technique such as etching.

  According to the thirteenth and fifteenth aspects of the present invention, Mg ion implantation is performed in small sections discretely arranged in the separation region, so that thermal diffusion of Mg by subsequent annealing can be effectively performed.

Hereinafter, the present invention will be described based on specific examples.
However, the embodiments of the present invention are not limited to the following examples.
The group III nitride compound semiconductor includes binary, ternary, or quaternary “Al _1-xy Ga _y In _x N; 0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1”. Semiconductors having an arbitrary mixed crystal ratio represented by the general formula are included. From the viewpoint of crystallinity, it is most desirable to use GaN for the p-type region. In the group III nitride compound semiconductor, in the above composition formula, at least a part of the group III element (Al, Ga, In) is substituted with boron (B), thallium (Tl), or the like. Alternatively, at least part of nitrogen (N) may be substituted with phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi), or the like.

As the crystal growth substrate, a substrate made of sapphire, Si, SiC, GaAs, GaN, other group III nitride compound semiconductor, or the like can be used. When the substrate is a group III nitride compound semiconductor, a group III nitride compound semiconductor is hetero-growth or formed by ELO growth on the above substrate by MOCVD, HVPE, LPE, etc. By removing the substrate, a group III nitride compound semiconductor substrate can be obtained. In addition, a group III nitride compound semiconductor substrate may be obtained by a flux method in which Ga metal is melted in a flux and liquid phase growth is performed while supplying a gas containing nitrogen.
The energy of Mg ion implantation can be in the range of 10 to 200 eV. Moreover, the temperature of the thermal diffusion by annealing can employ | adopt the range of 600-1500 degreeC. Nitrogen gas or inert gas can be used for the annealing atmosphere. An atmosphere containing hydrogen atoms is undesirable in order to remove H bonded to Mg in the crystal. Hereinafter, although demonstrated based on an Example, this invention is not limited to an Example.

FIG. 1 shows a p-type conversion method according to this embodiment. A GaN substrate was used as the substrate 11. A SiO ₂ film was formed on the surface of the substrate 11 to a thickness of 500 nm by sputtering. A photoresist was uniformly coated on the SiO ₂ film, exposed and developed to form a photoresist in a lattice shape having a width of 800 nm and a spacing of 800 nm. Thereafter, using the lattice-shaped photoresist as a mask, the SiO ₂ film in the window was etched to form a SiO ₂ film in a lattice shape having a width of 800 nm and an interval of 800 nm. As a result, the window 13 is formed in an 800 nm square lattice island shape.

Next, using the SiO ₂ film 12 formed in the lattice shape as a mask, ion implantation (implantation) was performed by accelerating Mg ions to 30 eV from above the substrate 11. The energy of this ion implantation can be in the range of 10 to 200 eV. The injection amount is 3 × 10 ¹⁵ / cm ² . As a result, an injection region 14 having an Mg density of 1 × 10 ¹⁹ / cm ³ was formed in a lattice island shape of 800 nm square in the region of the substrate 11 below the window 13.

Next, the SiO ₂ film 12 was removed by etching with an HF solution. Next, a SiO ₂ film having a thickness of 300 nm was uniformly formed on the surface of the substrate 11 by sputtering, and annealed at 1100 ° C. for 1 hour in a nitrogen atmosphere. Thereby, Mg in the implantation region 14 was diffused in the horizontal direction (x-axis direction) and the depth direction (y-axis direction). The reason why the SiO ₂ film is used is to prevent GaN nitrogen from leaving the substrate 11 in the annealing process. In this way, a p-type region 15 having a thickness of 500 nm and a hole concentration of 4 × 10 ¹⁶ / cm ³ was formed.

  Thus, this embodiment is characterized in that after ion implantation of Mg, the p-type region is formed by thermal diffusion, and it is not necessary to etch the high-resistance implantation region later. In addition, although the injection region 14 is a high resistance region, since it is formed in a lattice island shape, the functional influence as an element can be reduced. In addition, although the implantation region 14 is 800 nm square and the interval is 800 nm, for example, the implantation region 14 may be 200 nm square and the interval may be 800 nm. That is, the implantation region 14 may be made sufficiently smaller than the p-type region 15 that is the diffusion region so that the length of one side of the implantation region 14 is, for example, ¼ of the interval. By doing in this way, the influence of the high resistance implantation region 14 on the element can be further eliminated. The ion implantation region may be formed in a lattice island shape or may be formed in an arbitrarily dispersed dot island shape. Further, it may be formed in a stripe shape or a lattice shape.

As shown in FIG. 3, Mg is uniformly ion-implanted from the surface of a substrate 11 made of GaN to form an implantation region 16 as a first layer. Next, the second layer is formed by growing GaN on the implantation region 16 by MOCVD. Next, the surface is covered with a SiO ₂ film in the same manner as in Example 1, and then annealed at 1100 ° C. to thermally diffuse Mg in the implantation region 16 into the second layer 17 to form a p-type layer. Next, after removing the SiO ₂ film, next, n-type GaN doped with Si is grown on the second layer 17 to form the n layer 18. In this way, a pn junction having a p layer and an n layer from the side close to the substrate 11 can be formed. Since the element region is formed on the surface side of the substrate, even if the high resistance injection region 16 exists on the bottom side of the element, the function of the element is not affected.

The thermal diffusion may be performed in the next step. After forming the implantation region 16, a GaN layer is formed on the implantation region 16, and a GaN layer to which Si is added is further formed thereon. Thereafter, the surface may be covered with a SiO ₂ film, annealed at 1100 ° C., and Mg may be thermally diffused into the upper GaN layer to form the second layer 17 in the p-type region. Thereby, a pn junction may be formed by the p-type layer of the second layer 17 and the n-type layer thereon.
In addition, although the injection | pouring area | region 16 injected Mg uniformly, you may form it in the shape of a grid island, a grid | lattice form, a stripe form, and other dispersed dots like Example 1.

FIG. 4 shows a vertical field effect transistor. A SiO ₂ film is uniformly formed on the surface of the substrate 20 made of n-type GaN to which Si is added, and a mask having a window in an ion implantation region is formed by photolithography. Mg was ion-implanted using this SiO ₂ with an ion energy of 30 eV. Thereby, the implantation region 21 was formed. Next, the surface of the substrate 20 is uniformly covered with a SiO ₂ film, and annealed at a temperature of 1100 ° C., so that the Mg in the implantation region 21 is placed around the direction parallel to the plane of the substrate 20 and the direction perpendicular thereto. The p-type region 22 was formed so as to include the implantation region 21 by thermal diffusion.

Next, Si was ion-implanted in a range narrower than the implantation region 21 and annealed at 1100 ° C. to make the entire implantation region 21 n-type GaN. Next, a protective film 23 made of SiO ₂ is formed on the surface of the substrate 20 as in a normal vertical transistor, a window is formed at the position of the implantation region 21, and Al is evaporated to form a source electrode 25. did. Further, a gate electrode 24 made of polycrystalline silicon was formed on the protective film 23, and was further covered with the protective film 23 to form the gate electrode 24 in the protective film 23. In addition, the drain electrode 26 was formed by evaporating Al on the back surface of the substrate 20.

  Thus, the implantation region 21 becomes an n-type source region, the p-type region 22 which is a diffusion region becomes a channel region, and the substrate 20 made of n-type GaN becomes a drain region. In this manner, an n-channel vertical FET having a channel on the substrate surface portion of the p-type region 22 and immediately below the gate electrode 24 can be configured. GaN is used as the semiconductor, but naturally, a group III nitride compound semiconductor having an arbitrary composition and composition ratio can be used.

  In the present invention, the donor impurity is added to the implanted region to form the n-type region of the transistor, so that it can be used for a lateral FET and a HEMT structure as well as a vertical FET.

  As shown in FIG. 5, Mg was ion-implanted uniformly from the surface of a substrate 30 made of n-type GaN with an energy of 30 eV to form an implantation region 31. Thereafter, the substrate 30 was annealed at 1100 ° C., and Mg was thermally diffused downward to form a p-type region 32 as a diffusion region. Next, Si was ion-implanted shallowly only in the implantation region 31 on the upper surface, and annealing was performed to make the entire implantation region 31 into n-type GaN. Thereby, an element having a p-type layer below and an n-type layer above can be formed.

  Of course, Mg is uniformly implanted in the implantation region 31, but it may be formed in the form of lattice islands, lattices, stripes, or other dispersed dots as in the first embodiment. Then, Si may be added to a layer having a predetermined thickness including the implantation region 31, and the layer may be an n-type layer.

FIG. 6 shows an insulation separation method according to the fifth embodiment. An n-type GaN substrate 50 was used as the substrate. An n-type AlGaN layer 51 epitaxially grown by MOCVD is formed on the upper surface of the substrate 50. This embodiment is an example used for insulating isolation between elements of a HEMT that forms a two-dimensional electron gas at the interface between the GaN substrate 50 and the AlGaN layer 51. A SiO ₂ film was formed on the surface of the AlGaN layer 51 to a thickness of 500 nm by sputtering. A photoresist was uniformly applied on the SiO ₂ film, exposed, and developed to form a photoresist mask having windows formed at positions corresponding to the separation regions A and B. Thereafter, using the photoresist as a mask, the SiO ₂ film in the window portion was etched to form the SiO ₂ film 52 in which the window 13 was formed at positions corresponding to the separation regions A and B.

Next, using the SiO ₂ film 52 as a mask, ion implantation (implantation) was performed by accelerating Mg ions to 30 eV from above the AlGaN layer 51. The energy of this ion implantation can be in the range of 10 to 200 eV. The injection amount is 3 × 10 ¹⁵ / cm ² . As a result, an implantation region 54 having an Mg density of 1 × 10 ¹⁹ / cm ³ was formed in the region between the n-type AlGaN layer 51 and the n-type GaN substrate 50 below the window 53.

Next, the SiO ₂ film 52 was removed by etching with an HF solution. Next, a SiO ₂ film having a thickness of 300 nm was uniformly formed on the surface of the AlGaN layer 51 by sputtering, and annealed at 1100 ° C. for 1 hour in a nitrogen atmosphere. Thereby, Mg in the implantation region 54 was diffused in the horizontal direction (x-axis direction) and the depth direction (y-axis direction). The reason why the SiO ₂ film is used is to prevent detachment of nitrogen from the GaN substrate 50 and the AlGaN layer 51 in the annealing process. In this manner, a p-type region 55 having a width of 500 nm and a hole concentration of 4 × 10 ¹⁶ / cm ³ was formed outside the injection region 54.

  In this manner, the pn junction surface Q is formed between the p-type region 55, the surrounding n-type GaN substrate 50, and the n-type AlGaN layer 51. Then, the p-type region 55 is grounded (negative potential), so that isolation between elements is performed. In addition, a high-resistance injection region 54 is formed inside the p-type region 55. The resistance of the implanted region 54 does not decrease even by annealing. Therefore, this implantation region 54 also contributes to the isolation of the element.

  In this embodiment, Mg is ion-implanted uniformly in the region of the window 53, but this may be ion-implanted in a lattice island shape, a lattice shape, or a stripe shape. Thereafter, Mg is thermally diffused to form a p-type region in the depth direction in the window 53 part.

As shown in FIG. 7, an implantation region 66 is formed by uniformly ion-implanting Mg from the surface of a substrate 60 made of n-type GaN. The injection amount is 3 × 10 ¹⁵ / cm ² . Next, an n-type semiconductor layer 67 is formed by growing n-type GaN to a thickness of 500 nm on the implantation region 66 by MOCVD. Next, after covering the surface with a SiO ₂ film in the same manner as in Example 1, annealing is performed at 1100 ° C., and Mg in the implantation region 66 is thermally diffused into the n-type semiconductor layer 67 to form a p-type having a thickness of 100 nm. Layer 68 is formed. Thus, by forming the pn junction surface S with the p-type layer 68 and the n-type semiconductor layer 67, the planar inter-element isolation region S can be formed. At this time, since the implantation region 66 maintains high resistance even if annealing is performed, it contributes to insulation isolation together with the pn junction surface S.
In this embodiment, Mg is uniformly ion-implanted in the implantation region 66, but this may be ion-implanted in a lattice island shape, a lattice shape, or a stripe shape. Thereafter, the p-type layer 68 can be formed upward by thermally diffusing Mg.

  You may combine Example 5 and Example 6. FIG. That is, after obtaining the substrate having the configuration shown in FIG. 7 as in Example 6, the n-type AlGaN layer 51 epitaxially grown by the MOCVD method is formed on the n-type semiconductor layer 67 made of n-type GaN. . Thereafter, the n-type semiconductor layer 67 of FIG. 8 is regarded as the n-type GaN substrate 50 of FIG. 6 of the fifth embodiment, and a device is formed by the same method as that of the fifth embodiment. The p-type region 55 performs thermal diffusion of Mg so as to be connected to the p-type layer 68. In this way, the periphery and bottom surface of the element D can be insulated and separated at the pn junction surface.

  The Mg implantation region 54 may be formed deeply up to the implantation region 66. Then, a high resistance region (implantation regions 54 and 66) surrounding the periphery of the element D is further formed outside the pn junction surface, and the insulation is further improved.

  The present invention relates to a method of making a group III nitride compound semiconductor p-type, an element having a p-type region or an n-type region, a method of insulating isolation of a group III nitride compound semiconductor, and an isolated group III nitride system It can be applied to a compound semiconductor device.

Sectional drawing of the board | substrate which showed the manufacturing process which concerns on the specific Example 1 of this invention. Sectional drawing of the board | substrate which showed the manufacturing process which concerns on the Example 1. FIG. The top view of the board | substrate which showed the manufacturing process of the Example 1. FIG. FIG. 6 is a cross-sectional view showing a configuration of a semiconductor according to Example 2. FIG. 9 is a cross-sectional view illustrating a structure of a transistor according to Example 3; Sectional drawing of the semiconductor which concerns on Example 4. FIG. Sectional drawing which showed the structure of the semiconductor device which concerns on the specific Example 5 of this invention. Sectional drawing which showed the structure of the semiconductor device which concerns on the specific Example 6 of this invention. Sectional drawing which showed the structure of the semiconductor device based on the specific Example 7 of this invention.

Explanation of symbols

11 ... substrate 12 ... SiO ₂ film 13 ... window 14 ... injection region 15 ... p-type region 16 ... injection region 17 ... second layer 18 ... n layer 20 ... substrate 21 ... injection region 22 ... p-type region 23 ... insulating film 24 ... Gate electrode 25 ... Source electrode 26 ... Drain electrode 50 ... n-type GaN substrate 51 ... n-type AlGaN layer 52 ... SiO ₂ film 53 ... window 54 ... injection region 55 ... p-type region 60 ... substrate 66 ... injection region 67 ... n-type semiconductor layer 68 ... p-type layer

Claims (15)

In a method for converting a group III nitride compound semiconductor to p-type,
Magnesium (Mg) is partially ion-implanted in a plane on the group III nitride compound semiconductor,
Thereafter, the magnesium (Mg) is thermally diffused in a horizontal direction on the plane and in a direction perpendicular to the plane, thereby converting the diffusion region into a p-type, and a method for converting the group III nitride compound semiconductor into a p-type . 3. The group III according to claim 1, wherein the ion implantation of magnesium (Mg) is performed in a lattice island shape, a lattice shape, or a stripe shape on a plane in a region to be p-type. A method of converting a nitride-based compound semiconductor to p-type. 3. The n-type region is formed by adding a donor impurity to a region where the magnesium (Mg) is partially ion-implanted or a portion including the region. 4. A method of converting a group III nitride compound semiconductor to p-type. In a method for converting a group III nitride compound semiconductor to p-type,
Magnesium (Mg) is ion-implanted into the Group III nitride compound semiconductor,
Thereafter, the magnesium (Mg) is thermally diffused to make the diffusion region p-type,
A method of converting a group III nitride compound semiconductor into a p-type by adding a donor impurity to an ion-implanted region or a portion including the region and then converting the n-type into a n-type. In a method for converting a group III nitride compound semiconductor to p-type,
Magnesium (Mg) is ion-implanted into the first layer made of a group III nitride compound semiconductor,
A second layer made of a group III nitride compound semiconductor is grown on the first layer,
A method of converting a Group III nitride compound semiconductor to p-type by thermally diffusing magnesium (Mg) in the first layer into the second layer, thereby converting the second layer into p-type . 6. The group III nitride system according to claim 5, wherein the magnesium (Mg) ion implantation is performed in a lattice island shape, a lattice shape, or a stripe shape on the plane of the first layer. A method of converting a compound semiconductor to p-type. An implantation region in which magnesium (Mg) is partially ion-implanted on a plane;
A group III nitride compound semiconductor comprising: a p-type region obtained by thermally diffusing magnesium (Mg) in a horizontal direction on a plane and in a direction perpendicular to the plane from the implanted region. 8. The group III nitride compound semiconductor according to claim 7, wherein the p-type region forms a planar layer and has an n-type layer formed on the layer. 9. The group III nitride compound semiconductor according to claim 7, wherein the implanted region or a region including the implanted region is an n-type region to which a donor impurity is added. An implantation region in which magnesium (Mg) is ion-implanted;
A p-type region in which magnesium (Mg) is thermally diffused from the implanted region into a p-type,
A group III nitride compound semiconductor comprising: an n-type region which is made n-type by adding a donor impurity to the implanted region or a region including the implanted region. In a transistor comprising a group III nitride compound semiconductor,
An implantation region in which magnesium (Mg) is partially ion-implanted, and an n-type emitter / source region doped with a donor impurity;
A p-type base / channel region formed around the emitter / source region and made into p-type by thermally diffusing magnesium (Mg) from the implantation region;
And a n-type collector / drain region formed outside the base / channel region. In a method for insulating and separating a group III nitride compound semiconductor device,
Magnesium (Mg) is ion-implanted into the isolation region in the n-type group III nitride compound semiconductor, and then the p-type region is formed by thermal diffusion to the periphery by annealing to form a pn junction surface. A method for insulating and separating a group III nitride compound semiconductor device. 13. The group III according to claim 12, wherein the ion implantation of magnesium (Mg) is performed in a lattice island shape, a lattice shape, or a stripe shape on a plane in a region to be p-type. Insulating separation method for nitride compound semiconductor device. In group III nitride compound semiconductor devices,
an n-type group III nitride compound semiconductor;
An implanted region of magnesium (Mg) ions implanted in the isolation region of the n-type Group III nitride compound semiconductor;
And a p-type region formed by thermally diffusing magnesium (Mg) in the implanted region into a surrounding n-type group III nitride compound semiconductor, and the n-type group III nitride compound semiconductor and the p-type region A group III nitride compound semiconductor device characterized by being isolated by a pn junction comprising a mold region. 15. The group III nitride compound semiconductor device according to claim 14, wherein the implantation region is formed in a lattice island shape, a lattice shape, or a stripe shape.

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