JP2007258390A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having a copper wiring embedded structure that offers fine conductivity and yet sufficiently prevents the diffusion of copper, and to provide a manufacturing method for the semiconductor device. <P>SOLUTION: According to the semiconductor device 27, copper wiring 17a is embedded in a wiring trench 13a formed on a first insulating film 13 via a diffusion preventive layer 15, and copper wiring 26a is embedded in a wiring trench 24a and a connection hole 22a formed on a second insulating film 22 and a third insulating film, respectively, via a diffusion preventive layer 25. The diffusion preventive layers 15 and 25 are made of a ruthenium carbide (RuCx), a ruthenium silicide (RuSix), or a ruthenium alloy (RuTa). <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device in which a copper-containing conductive pattern is embedded in a groove pattern such as a connection hole or a wiring groove formed in an interlayer insulating film, and a manufacturing method thereof.

  In the silicon LSI of the 0.18 μm generation and later, the delay due to the CR component of the wiring is no longer negligible for the higher speed of the transistor, so instead of the conventional Al (specific resistance 3 μΩ · cm), a lower resistance Cu ( Studies are underway to use a copper alloy containing a specific resistance of 1.7 μΩ · cm) or Cu as a main component as a wiring material. In this specification, a wiring made of copper or a copper alloy is referred to as a copper wiring.

  FIG. 5 shows a cross-sectional view of a semiconductor device using copper wiring. In the semiconductor device shown in this figure, a semiconductor substrate 100 on which a MOS transistor and other semiconductor elements are formed is covered with a base insulating film 101. A wiring groove 101 a is provided on the surface side of the base insulating film 101, and a copper wiring 103 is embedded in the wiring groove 101 a through a barrier metal layer 102. Further, on the base insulating film 101, a first silicon nitride film 104, a second insulating film 105, a second silicon nitride film 106, and a third insulating film 107 are stacked in this order. A groove 17a is provided. The second silicon nitride film 106, the second insulating film 105, and the first silicon nitride film 104 are provided with a connection hole 105a that reaches the copper wiring 103 from the bottom of the wiring groove 107a. A copper wiring 109 is buried in the wiring groove 107a and the connection hole 105a through a barrier metal layer.

  In the above configuration, the barrier metal layers 102 and 108 are layers for preventing copper constituting the copper wirings 103 and 109 from diffusing into the insulating films 101, 105, and 107. For example, tantalum (Ta) or the like. It consists of In recent years, conductivity is lost even when oxidized, such as ruthenium (Ru) or iridium (Ir), in order to prevent an increase in resistance of the copper wiring due to oxidation of the barrier metal layer made of tantalum. There has been proposed a structure in which a barrier metal layer is formed using no metal or these metal oxides (see, for example, Patent Document 1 below).

JP 2002-75994 A

  However, in the above-described semiconductor device, the barrier property of ruthenium (Ru) and iridium (Ir) constituting the barrier metal layer against copper is not sufficient. For this reason, when the miniaturization of the wiring further progresses, further thinning of the barrier metal layer is required. However, the barrier metal layer made of the above-described metal or metal oxide is reduced in copper by thinning. It becomes difficult to sufficiently prevent the diffusion of wiring, and this becomes a factor that hinders the miniaturization of wiring.

  Accordingly, an object of the present invention is to provide a semiconductor device having a copper wiring buried structure capable of sufficiently preventing copper diffusion while having good conductivity, and a method for manufacturing the same.

  In order to achieve such an object, the present invention provides a semiconductor device in which a copper-containing conductive pattern is embedded in a groove pattern formed in an insulating film via a diffusion prevention layer. It is characterized by being made of silicide, ruthenium carbide, or ruthenium alloy.

  The present invention is also a method for manufacturing a semiconductor device having the above-described configuration according to the present invention. First, a groove pattern is formed in an insulating film, and ruthenium silicide, ruthenium color bite, Alternatively, a diffusion prevention layer made of a ruthenium alloy is formed, and a copper-containing conductive material film is formed on the insulating film so that the inside of the groove pattern is embedded through the diffusion prevention layer, and then conductive only in the groove pattern. The conductive material film and the diffusion prevention layer on the insulating film are polished and removed so as to leave the conductive material film and the diffusion prevention layer.

  In the semiconductor device having such a configuration, the ruthenium carbide, ruthenium silicide, or ruthenium alloy constituting the diffusion prevention layer has good conductivity and is an amorphous or microcrystalline material. The barrier property against the metal material is good.

  As described above, according to the semiconductor device and the manufacturing method thereof of the present invention, the conductivity is improved by providing the diffusion prevention layer using ruthenium carbide, ruthenium silicide, or ruthenium alloy having good conductivity and barrier property against copper. A copper wiring structure capable of sufficiently preventing the diffusion of copper while being good is obtained, whereby further miniaturization of the copper wiring structure can be achieved.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In each embodiment, the semiconductor device manufacturing method and the semiconductor device formed thereby will be described in this order.

<First Embodiment>
1 and 2 are cross-sectional process diagrams illustrating a first embodiment of the present invention. The details of the manufacturing method according to the first embodiment and the semiconductor device obtained thereby will be described below with reference to this drawing.

First, as shown in FIG. 1A, a base insulating film 11 made of, for example, silicon oxide (SiO ₂ ) is formed on a semiconductor substrate 10 on which MOS transistors and other semiconductor elements are formed. Then, a connection hole 11a reaching the element formed in the semiconductor substrate 10 is formed in the base insulating film 11, and a plug 12 made of tungsten (W) or the like is formed therein.

  Next, a first insulating film 13 made of a material having a lower dielectric constant than silicon oxide, such as an organic material such as carbon-containing silicon oxide (SiOC) or polyaryl ether, is formed on the plug 12 and the base insulating film 11. Form a film.

  Then, a wiring groove 13a is formed as a groove pattern in the first insulating film 13 with the upper surface of the plug 12 exposed. At this time, for example, the first insulating film 13 is etched using a resist pattern not shown here as a mask.

  After the formation of the wiring trench 13a, a degassing process is performed at 300 ° C. for 60 seconds in an inert atmosphere, for example, an argon (Ar) atmosphere or a vacuum atmosphere.

Next, as shown in FIG. 1B, a diffusion prevention layer 15 characteristic of the present invention is formed on the first insulating film 13 in a state of covering the inner wall of the wiring groove 13a. This diffusion prevention layer 15 is characterized in that it is composed of a) ruthenium carbide (RuCx), b) ruthenium silicide (RuSix), or c) ruthenium alloy (Ru alloy). Here, in particular, the single-layer structure is made of ruthenium carbide (RuCx), ruthenium silicide (RuSix), or a ruthenium alloy (Ru alloy). Examples of the Ru alloy include an alloy of ruthenium and tantalum (Ru _x Ta _y ), an alloy of ruthenium and titanium (Ru _x Ti _y ), an alloy of ruthenium and zirconium (Ru _x Zr _y ), and ruthenium and tungsten. An alloy of (Ru _x W _y ) and an alloy of ruthenium and vanadium (Ru _x V _y ) are exemplified.

  The diffusion prevention layer 15 made of these materials is formed by, for example, atomic layer deposition (ALD method). In the case of the ALD method, a thermal ALD method, a plasma ALD method, and other ALD methods are applied. For example, it is performed as follows.

  a) The diffusion prevention layer 15 made of ruthenium carbide (RuCx) is formed as follows. First, a semiconductor substrate on which a film formation process is performed is cleaned and stored in a film formation chamber, and a gas in the film formation chamber is replaced with nitrogen.

Next, as a first step, an organometallic compound containing ruthenium (Ru) (that is, a Ru precursor) is supplied into the film forming chamber together with a carrier gas, whereby the Ru precursor is chemically monomolecularly formed on the film forming surface. Adsorb. As the Ru precursor, for example, Ru (EtCp) ₂ [ruthenium diethylcyproene] is used as a material that can be supplied in a gaseous state, and for example, argon (Ar) is used as the carrier gas.

Next, as a second step, ammonia (NH ₃ ) gas, ammonia gas plasma, hydrogen gas plasma, hydrogen radicals are introduced into the film forming chamber, and organic components in the Ru precursor adsorbed on the film forming surface are removed. Remove unnecessary organic components, leaving a certain amount.

  Thereafter, the diffusion prevention layer 15 made of ruthenium carbide (RuCx) is formed on the film formation surface by repeatedly performing the first step and the second step. At this time, the first step and the second step are repeatedly performed until the diffusion prevention layer 15 has a desired film thickness. In addition, the amount of carbon (C) in ruthenium (Ru) is controlled by adjusting the exposure time of the film formation surface to nitrogen gas in the second step.

b) The formation of the diffusion prevention layer 15 made of ruthenium silicide (RuSix) is performed in the second step in the formation of the diffusion prevention layer made of ruthenium carbide (RuCx) described above by replacing silane (SiH ₄₎ with nitrogen gas or the like. ) A gas is flowed to sufficiently replace organic components in the Ru precursor adsorbed on the film formation surface with silicon (Si). Then, the first step and the second step of flowing silane (SiH ₄ ) gas may be repeated.

In addition to this, after the organic component in the Ru precursor is sufficiently removed in the second step in the formation of the diffusion preventing layer made of ruthenium carbide (RuCx), the silane (SiH ₄ ) gas is used as the third step. The silicon (Si) is bonded to the Ru monomolecular film by performing the process of flowing the. And the method of repeating a 1st step-a 3rd step may be sufficient.

  c) The formation of the diffusion prevention layer 15 made of a ruthenium alloy (Ru alloy) is the first step in the formation of the diffusion prevention layer made of ruthenium carbide (RuCx), and is made of tantalum (Ta) or the like together with the Ru precursor. An organometallic compound containing metal (that is, a Ta precursor) may be supplied into the deposition chamber. Then, the first step for flowing the Ru precursor and the Ta precursor and the second step for removing the organic components in the precursor may be repeated.

  In addition to this, after performing the first step and the second step after flowing the Ru precursor in the formation of the diffusion prevention layer made of ruthenium carbide (RuCx), the first step and the subsequent step of flowing the Ta precursor are performed. The second step may be performed, and these may be alternately repeated.

  The diffusion prevention layer 15 made of a) ruthenium carbide (RuCx), b) ruthenium silicide (RuSix), or c) ruthenium alloy (Ru alloy) is formed by the above-described atomic layer deposition (ALD) method. It is not limited to a film, and other film forming methods such as a CVD method may be applied.

  Thereafter, as shown in FIG. 1C, a copper seed layer 16 made of a copper film is formed on the diffusion prevention layer 15 by sputtering. Next, a copper plating layer 17 is formed on the copper seed layer 16 in a state where the wiring groove 13a is completely embedded by electrolytic plating. Note that the process from the degassing process after forming the wiring trench 13a to the formation of the copper seed layer 16 is performed in a continuously controlled atmosphere without opening the semiconductor substrate 10 to the atmosphere.

  Next, in order to grow the crystal grains in the copper plating layer 17, the copper plating layer 17 is subjected to heat treatment (for example, at a temperature of about 150 ° C. for about 1 hour). Thereby, the copper seed layer 16 and the copper plating layer 17 are integrated. The copper plating layer 17 may be formed directly on the diffusion prevention layer 15 by the electrolytic plating method without providing the copper seed layer 16.

  Next, as shown in FIG. 1 (4), the copper plating layer 17 (including the integrated copper seed layer 16) is polished and removed from the upper surface side by, for example, chemical mechanical polishing (CMP). Further, the diffusion preventing layer 15 is polished and removed to expose the first insulating film 13, and the diffusion preventing layer 15 and the copper plating layer 17 are left only in the wiring groove 13a. As a result, the first copper wiring 17 a made of the copper plating layer 17 is formed through the diffusion prevention layer 15 by connecting to the plug 12 exposed at the bottom of the wiring groove 13 a.

  Thereafter, as shown in FIG. 2 (5), the first silicon nitride film 21, the second insulating film 22, the second silicon nitride film 23, and the first silicon nitride film 21, the first silicon nitride film 23, and the first silicon nitride film 23 are formed on the first insulating film 13 including the first copper wiring 17a. Three insulating films 24 are sequentially deposited. Here, like the first insulating film 13, the second insulating film 22 and the third insulating film 24 are more dielectric than silicon oxide such as carbon-containing silicon oxide (SiOC) or an organic material such as polyaryl ether. Made of low rate material. In addition, the first silicon nitride film 21 and the second silicon nitride film 23 only have to have a thickness that can provide a barrier property against copper.

  Next, a wiring groove 24 a is formed as a groove pattern in the third insulating film 24. In addition, the second silicon nitride film 23, the second insulating film 22, and the first silicon nitride film 21 have a connection hole 22a as a groove pattern in a state where the upper portion of the first copper wiring 17a is exposed from the bottom of the wiring groove 24a. Form.

  The wiring groove 24a and the connection hole 22a are formed by etching using a resist pattern (not shown) as a mask, and either the wiring groove 24a or the connection hole 22a may be formed first.

  Next, as shown in FIG. 2 (6), a diffusion prevention layer 25 characteristic of the present invention is formed on the third insulating film 24 in a state of covering the inner walls of the wiring grooves 24 a and the connection holes 22 a. This diffusion prevention layer 25 is similar to the diffusion prevention layer 15 described with reference to FIG. 1 (2), (a) ruthenium carbide (RuCx), (b) ruthenium silicide (RuSix), or (c). It is characteristic that it is composed of a ruthenium alloy (Ru alloy). The formation of the diffusion preventing layer 25 is performed in the same manner as the formation of the diffusion preventing layer 15. The diffusion preventing layer 15 and the diffusion preventing layer 25 are not limited to being made of the same material.

  After the above, as described with reference to FIGS. 1 (3) and 1 (4), a copper seed layer and a copper plating layer are formed on the diffusion prevention layer 25, and crystal grains in the copper plating layer are formed. Heat treatment for growth is performed. At this time, only the copper plating layer may be formed by electrolytic plating without providing the copper seed layer. Next, the copper plating layer and the diffusion prevention layer 25 are removed by polishing to expose the third insulating film 24, leaving the diffusion prevention layer 25 and the copper plating layer only in the wiring groove 24a and the connection hole 22a.

  As described above, as shown in FIG. 2 (7), the second copper wiring 26a is formed by embedding the copper plating layer through the diffusion prevention layer 25 in the wiring groove 24a and the connection hole 22a. The second copper wiring 26 a is connected to the first copper wiring 17 a through the diffusion prevention layer 25.

  As described above, the first copper wiring 17a is buried in the wiring groove 13a via the diffusion preventing layer 15, and the wiring groove 24a and the connection hole 22a on the first copper wiring 17a are interposed via the diffusion preventing layer 25. The semiconductor device 27 in which the second copper wiring 26a is embedded is obtained. In particular, the diffusion preventing layers 15 and 25 are configured as a single layer structure made of ruthenium carbide (RuCx), ruthenium silicide (RuSix), or a ruthenium alloy (Ru alloy).

  In the semiconductor device 27 having such a configuration, the copper wiring 17a, the diffusion layer 15 and 25 having a single layer structure made of ruthenium carbide (RuCx), ruthenium silicide (RuSix), or ruthenium alloy (Ru alloy) are provided. 26a is provided. These materials constituting the diffusion preventing layers 15 and 25 have good conductivity.

  Further, since these ruthenium carbide (RuCx), ruthenium silicide (RuSix), or ruthenium alloy (Ru alloy) is an amorphous or microcrystalline material, it has a good barrier property against a metal material such as copper. Therefore, for example, in the step described with reference to FIG. 2 (5), the diffusion prevention layer 15 and the first silicon nitride film 21 are formed with the second insulating film 22 and the upper layers 23 and 24. During the heat treatment (for example, about 400 ° C.), it is possible to sufficiently prevent the copper atoms constituting the first copper wiring 17 a from diffusing into the first insulating film 13 and the second insulating film 22.

  Therefore, the resistance of the wiring is prevented from being increased by the diffusion preventing layers 15 and 25, so that the conductivity can be maintained well, and the diffusion of copper to the insulating films 13, 22, and 24 is also achieved by the thinned diffusion preventing layers 15 and 25. It is possible to obtain a copper wiring structure capable of sufficiently preventing the above.

  As a result, according to the first embodiment of the present invention described above, further miniaturization of the copper wiring structure can be achieved.

  In particular, a film such as ruthenium carbide (RuCx), ruthenium silicide (RuSix), or ruthenium alloy (Ru alloy) constituting the diffusion prevention layers 15 and 25 applies the ALD method or the CVD method as described above. It is possible to form a film. Therefore, compared with the case where the film is formed by the sputtering method or the like, the diffusion preventing layers 15 and 25 are also formed on the side walls of the groove pattern such as the wiring groove and the connection hole with a uniform film thickness without requiring complicated process control. Can be formed. Thereby, the embedding defect of a copper plating layer can be prevented. This also prevents an increase in the oxidation resistance of the diffusion preventing layer due to degassing from the insulating film due to insufficient film thickness of the diffusion preventing layers 15 and 25 on the side walls of the groove pattern.

Second Embodiment
3 and 4 are cross-sectional process diagrams for explaining a second embodiment of the present invention. The second embodiment shown in these drawings differs from the first embodiment described above in the configuration of the upper and lower layers of the diffusion prevention layer, and the other configurations are the same. Therefore, the same code | symbol is attached | subjected to the component similar to 1st Embodiment, and the overlapping description is abbreviate | omitted.

  First, as shown in FIG. 3A, a base insulating film 11 is formed on a semiconductor substrate 10 on which a MOS transistor and other semiconductor elements are formed, and the connection hole 11a formed in the base insulating film 11 is formed. Plug 12 is formed. Next, a low dielectric constant first insulating film 13 is formed on the base insulating film 11, and a wiring groove 13 a is formed in the first insulating film 13.

  Next, as shown in FIG. 3B, a diffusion prevention layer 15 characteristic of the present invention is formed on the first insulating film 13 so as to cover the inner wall of the wiring groove 13a. That is, this diffusion prevention layer 15 is similar to the diffusion prevention layer 15 described above with reference to FIG. 1 (2), and (a) ruthenium carbide (RuCx), (b) ruthenium silicide (RuSix), or ( c) It is characteristic that it is composed of a ruthenium alloy (Ru alloy).

  Further, as a characteristic configuration of the second embodiment, a ruthenium layer 31 is formed on the diffusion prevention layer 15. The ruthenium layer 31 is formed, for example, by atomic layer deposition (ALD method). In the case of the ALD method, a thermal ALD method, a plasma ALD method, and a pulse-ALD method in which a reducing gas is allowed to flow in a gas flow at regular intervals are applied, for example, as follows.

  First, following the film formation of the diffusion preventing layer 15, the gas in the film forming chamber for performing the film forming process is replaced with nitrogen.

Next, as a first step, an organometallic compound containing ruthenium (Ru) (that is, a Ru precursor) is supplied into the film forming chamber together with a carrier gas, whereby the Ru precursor is chemically monomolecularly formed on the film forming surface. Adsorb. As the Ru precursor, for example, Ru (EtCp) ₂ [ruthenium diethylcyproene] is used as a material that can be supplied in a gaseous state, and for example, argon (Ar) is used as the carrier gas.

Next, as a second step, ammonia (NH ₃ ) gas, ammonia gas plasma, hydrogen gas plasma, and hydrogen radicals are introduced to sufficiently remove organic components in the Ru precursor adsorbed on the film formation surface.

  Thereafter, the ruthenium layer 31 is formed on the film formation surface by repeatedly performing the first step and the second step. At this time, the first step and the second step are repeatedly performed until the ruthenium layer 31 has a desired film thickness.

  The formation of the ruthenium layer 31 is not limited to the film formation by the atomic layer deposition (ALD) method described above, and other film formation methods such as the CVD method may be applied.

  After the above, the same process as in the first embodiment is performed to form the first copper wiring.

  That is, first, as shown in FIG. 3 (3), a copper seed layer 16 and a copper plating layer 17 are formed on the ruthenium layer 31, and a heat treatment for growing crystal grains in the copper plating layer 17 is performed. The copper plating layer 17 may be formed directly on the diffusion prevention layer 15 by the electrolytic plating method without providing the copper seed layer 16.

  Next, as shown in FIG. 3 (4), the copper plating layer 17 (including the copper seed layer 16), the ruthenium layer 31, and the diffusion prevention layer 15 are polished and removed to expose the first insulating film 13, and the wiring trench The diffusion preventing layer 15, the ruthenium layer 17, and the copper plating layer 17 are left only in 13a. As a result, the first copper wiring 17a made of the copper plating layer 17 is formed in the wiring groove 13a through the diffusion prevention layer 15 and the ruthenium layer 17 by being connected to the plug 12 exposed at the bottom of the wiring groove 13a. .

  Thereafter, as shown in FIG. 4 (5), on the first insulating film 13 including the first copper wiring 17a, the first silicon nitride film 21, the second insulating film 22, the second silicon nitride film 23, and the first Three insulating films 24 are sequentially deposited. Next, the wiring groove 24a is formed in the third insulating film 24, and the connection hole 22a is formed in a state where the upper portion of the first copper wiring 17a is exposed from the bottom of the wiring groove 24a.

  Next, as shown in FIG. 4 (6), as a characteristic configuration of the second embodiment, a ruthenium layer 32 is formed on the third insulating film 24 in a state of covering the inner walls of the wiring grooves 24a and the connection holes 22a. Then, a diffusion prevention layer 25 is formed, and a ruthenium layer 33 is further formed. The ruthenium layers 32 and 33 are formed in the same manner as described above with reference to FIG. Further, the diffusion prevention layer 25 is a diffusion prevention layer 25 characteristic of the present invention, and (a) ruthenium carbide (RuCx), (b) ruthenium silicide (RuSix), or (c) ruthenium alloy (Ru alloy). It is comprised using. The diffusion preventing layer 15 and the diffusion preventing layer 25 are not limited to being made of the same material.

  After the above, as described with reference to FIGS. 3 (3) and 3 (4), a copper seed layer and a copper plating layer are formed on the ruthenium layer 33, and crystal grains in the copper plating layer are grown. In addition, the copper plating layer and the diffusion prevention layer 25 are polished and removed to expose the third insulating film 24, leaving the diffusion prevention layer 25 and the copper plating layer only in the wiring groove 24a and the connection hole 22a. .

  As described above, as shown in FIG. 4 (7), the second copper obtained by embedding the copper plating layer in the wiring groove 24a and the connection hole 22a through the diffusion preventing layer 25 sandwiched by the ruthenium layers 32 and 33. A wiring 26a is formed. The second copper wiring 26 a is connected to the first copper wiring 17 a through the diffusion prevention layer 25 sandwiched between the ruthenium layers 32 and 33.

  As described above, the first copper wiring 17a is embedded in the wiring groove 13a via the diffusion prevention layer 15 and the ruthenium layer 31, and the ruthenium layer 32 is formed in the wiring groove 24a and the connection hole 22a on the first copper wiring 17a. , 33, the semiconductor device 34 in which the second copper wiring 26a is embedded through the diffusion prevention layer 25 is obtained.

  In the semiconductor device 34 having such a configuration, the diffusion prevention layers 15 and 25 having a single layer structure made of ruthenium carbide (RuCx), ruthenium silicide (RuSix), or a ruthenium alloy (Ru alloy), the copper wirings 17a and 26a, Ruthenium layers 31, 32, and 33 are provided between them. The ruthenium layers 31, 32, and 33 are films having better adhesion to a metal material (especially copper) than the material constituting the diffusion prevention layers 15 and 25. For this reason, the diffusion prevention layers 15 and 25 sufficiently prevent the diffusion of copper into the insulating films 13, 22, and 24, while ensuring the adhesion between the diffusion prevention sparse 15 and 25 and the copper wirings 17a and 26a. Thus, it is possible to obtain a copper wiring structure that is improved in resistance to stress mailation and electromigration.

  The ruthenium layers 31, 32 and 33 can also be formed by applying the ALD method or the CVD method as described above. Therefore, it is possible to prevent an increase in the oxidation resistance of the diffusion preventing layer due to degassing from the insulating film due to poor filling of the copper plating layer and insufficient film thickness of the ruthenium layers 31, 32, 33.

  In the second embodiment, the diffusion prevention layer 15 formed using (a) ruthenium carbide (RuCx), (b) ruthenium silicide (RuSix), or (c) ruthenium alloy (Ru alloy), The configuration in which the ruthenium layers 31, 32, 33 are provided on the copper wirings 17a, 26a side in FIG. However, as another example of the second embodiment, the diffusion prevention layers 15 and 25 are made of ruthenium oxide (RuOx), and the ruthenium layers 31 and 25 are interposed between the diffusion prevention layers 15 and 25 and the copper wirings 17a and 26a. The structure provided with 32 and 33 can also be illustrated.

  For example, the diffusion prevention layer made of ruthenium oxide (RuOx) is formed by atomic layer deposition (ALD). In the case of the ALD method, a thermal ALD method, a plasma ALD method, and other ALD methods are applied. For example, it is performed as follows.

  First, nitrogen is substituted for a gas in a film forming chamber for performing a film forming process.

Next, as a first step, an organometallic compound containing ruthenium (Ru) (that is, a Ru precursor) is supplied into the film forming chamber together with a carrier gas, whereby the Ru precursor is chemically monomolecularly formed on the film forming surface. Adsorb. As the Ru precursor, for example, Ru (EtCp) ₂ [ruthenium diethylcyproene] is used as a material that can be supplied in a gaseous state, and for example, argon (Ar) is used as the carrier gas.

Next, as a second step, oxygen (O ₂ ) gas is introduced into the film forming chamber, and organic components in the Ru precursor adsorbed on the film forming surface are sufficiently removed and replaced with oxygen.

  Thereafter, the diffusion prevention layer made of ruthenium oxide (RuOx) is formed on the film formation surface by repeatedly performing the first step and the second step. At this time, the first step and the second step are repeated until a desired film thickness is obtained as the diffusion preventing layer.

  Even in other examples as described above, the same effect as in the second embodiment can be obtained.

FIG. 6 is a sectional process diagram (part 1) for describing the first embodiment; FIG. 6 is a sectional process diagram (part 2) for describing the first embodiment; It is sectional process drawing (the 1) for describing 2nd Embodiment. It is sectional process drawing (the 2) for demonstrating 2nd Embodiment. It is sectional drawing for demonstrating a prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 13 ... 1st insulating film, 13a, 23a ... Wiring groove | channel (groove pattern), 15, 25 ... Diffusion prevention layer, 17a ... 1st copper wiring (conductive pattern), 21 ... 1st silicon nitride film, 22 ... 2nd Insulating film, 22a ... connecting hole (groove pattern), 23 ... second silicon nitride film, 24 ... third insulating film, 26a ... second copper wiring, 27, 34 ... semiconductor device, 31, 32, 33 ... ruthenium layer

Claims (5)

In a semiconductor device in which a copper-containing conductive pattern is embedded in a groove pattern formed in an insulating film via a diffusion prevention layer,
The diffusion prevention layer is configured by using ruthenium carbide, ruthenium silicide, or a ruthenium alloy. The semiconductor device according to claim 1,
A ruthenium layer is provided between the diffusion preventing layer and the conductive pattern. A semiconductor device, wherein: In the semiconductor device according to claim 1,
The diffusion prevention layer is sandwiched between ruthenium layers. A semiconductor device, wherein: Forming a groove pattern in the insulating film;
Forming a diffusion prevention layer using ruthenium carbide, ruthenium silicide, or ruthenium alloy on the insulating film in a state of covering the inner wall of the groove pattern;
Forming a copper-containing conductive material film on the insulating film so as to be embedded in the groove pattern through the diffusion prevention layer;
A step of polishing and removing the conductive material film and the diffusion prevention layer on the insulating film so as to leave the conductive material film and the diffusion prevention layer only in the groove pattern. Production method. In the manufacturing method of the semiconductor device according to claim 4,
The method of manufacturing a semiconductor device, wherein the diffusion prevention layer is formed by atomic layer deposition.

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