JP2007257748A - Nonvolatile storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile storage device which can reduce an apparent variation in threshold voltage due to capacitive coupling among nonvolatile memory cells. <P>SOLUTION: The nonvolatile storage device is provided with a memory array, a data buffer and a control circuit. The memory array is provided with a plurality of sections (SECs) which have a plurality of erasing and writing units (BLKs) that respectively have a plurality of electrically erasable and writable nonvolatile memory cells. In response to a rewrite instruction for storage information, the erasing and writing order for the erasing and writing units in the storage section to be rewriten is controlled in one direction to the arrangement order of the erasing and writing units. Thus, an influence of capacitive coupling on the variation of threshold voltage can be limited to only influence from adjacent one direction. Since a previous unit adjacent to the unit in one direction is erased first, the influence from the adjacent one direction can be limited only for writing. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a technique for suppressing fluctuations in threshold voltage due to capacitive coupling between floating gates of adjacent nonvolatile memory cells. For example, the invention relates to a flash memory capable of storing four-value information in one nonvolatile memory cell. It is related to effective technology.

  Due to demands for large capacity and low bit cost for flash memory, the information storage form of flash memory cells has shifted from binary to multilevel, represented by four values. In the quaternary method, four types of threshold voltages are narrowed and distributed in a predetermined voltage range. A certain margin is ensured between the threshold voltage distribution and the read word line level, so that a read malfunction does not occur for slight threshold voltage fluctuations. Patent Document 1 is an example of a document that describes a flash memory that performs four-value storage.

JP-A-10-106276

  In the case of a floating gate type non-volatile memory cell, conductive floating gates are insulated from each other by silicon oxide or the like, but floating gates adjacent to each other in front, rear, left, and right are capacitively coupled. Therefore, when electrons are injected into the floating gate in the write operation and the threshold voltage is changed, the potential change of the floating gate caused thereby changes the potential of another floating gate that is capacitively coupled thereto. This apparently changes the threshold voltage of the nonvolatile memory cell having the other floating gate. When the elements are miniaturized due to the increase in the degree of integration, the interval between the non-volatile memory cells in the memory array is narrowed, and thereby the capacitance between the floating gates is relatively increased, so that the capacitive cup between adjacent memory cells is increased. It has been found by the present inventor that the ring may make it impossible to control the threshold voltage of the memory cell. For example, when erasing and writing are performed in units of word lines, writing is performed in units of one word line adjacent to a certain word line, and then writing is performed in units of the other word line adjacent to the word line. If this is performed, the nonvolatile memory cells of the word lines on both sides are written back and forth, so that the threshold voltage of the nonvolatile memory cells between them is undesirably changed many times by capacitive coupling, There is a risk that the voltage will enter the threshold voltage distribution adjacent to the read word line level. In this state, as the minimum processing size is reduced, it is expected that it becomes substantially difficult to take a read margin between distributions due to such interference between adjacent memory cells.

  An object of the present invention is to provide a nonvolatile memory device that can reduce the apparent variation of the threshold voltage due to capacitive coupling between nonvolatile memory cells.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

[1] << One-way rewriting >>
The nonvolatile memory device according to the present invention includes a memory array (2), a data buffer (4), and a control circuit (11, 22). The memory array has a plurality of storage partitions (SEC) having a plurality of erase and write units (BLK) each having a plurality of electrically erasable and writable nonvolatile memory cells (MC). Nonvolatile memory cells included in the erase and write units share a word line (WL) connected to their selection terminals. In response to the rewrite instruction of the storage information, the control circuit controls the erasure and write order for the erase and write units in the storage partition to be rewritten in one direction with respect to the arrangement order of the erase and write units. When writing is performed, rewrite control is performed so that the unit adjacent to the one-way ahead of the unit to be written is erased first.

  According to the above-described means, in response to the rewrite instruction of the storage information, the order of erasure and write with respect to the erase and write unit (BLK) in the storage partition (SEC) to be rewritten is changed to the arrangement order of the erase and write unit. By controlling in one direction, it is possible to limit the influence of capacitive coupling that can vary the threshold voltage to the influence from one adjacent direction. Furthermore, when writing is performed, the unit adjacent to the one direction ahead of the unit to be written is erased first, so that the influence from the adjacent one direction can be limited to writing. This makes it possible to reduce the apparent variation of the threshold voltage due to capacitive coupling between the nonvolatile memory cells.

  <Rewriting to another partition> As a specific form of the present invention, when the control circuit performs control to set the rewriting destination as another storage partition, the storage information of the rewriting source storage partition is used as the other storage partition. Then, the address arrangement of the rewrite source storage partition and the rewrite destination storage partition is exchanged.

  <Rewriting in the same partition> As another specific form of the present invention, when the control circuit performs control to set the rewrite destination as the same storage partition as the rewrite source, the entire rewrite source storage partition is rewritten. When there is data to be stored in the unit to be erased first, the data is saved in the data buffer before the erasure, and the saved data is stored in the corresponding erasure already erased adjacent to the one-way destination. Controls writing back to the writing unit.

  << Erase and Rewrite in Write Unit >> As another specific form of the present invention, in the rewrite control, the control circuit sets a rewrite destination as another storage partition, and for each erase and write unit to be rewritten. The stored information is written in the erase and write units of another partition, and the correspondence between the logical address and the physical address of the stored information is recombined every time the erase and write units are rewritten.

  At the time of rewriting to another partition, rewriting to the same partition, erasing and rewriting in a writing unit, non-volatile memory cells in other partitions are not caused to cause threshold voltage fluctuation due to capacitive coupling due to erasing and writing. Therefore, for example, an interval wider than the word line interval in the storage partition is provided between the word lines of the storage partitions adjacent to each other. Alternatively, a dummy word line may be arranged at the end of the storage partition.

  << Storage Partition >> As another specific form of the present invention, the storage partition includes a plurality of sub bit lines (SBL) that are made conductive to the main bit line (MBL) via a selection switch (Md), A plurality of nonvolatile memory cells (MC) each having one input / output terminal coupled to each of the sub-bit lines, and a selection terminal of the nonvolatile memory cell disposed in a direction intersecting the plurality of sub-bit lines. A plurality of word lines (WL) coupled to each other and a common line (CSL) commonly connected to the other input / output terminals of the plurality of previous nonvolatile memories, and the write / erase unit is a nonvolatile memory in units of word lines Cell.

  The nonvolatile memory cell has, for example, a conductive floating gate as a charge storage region and can store data of 2 bits or more per one.

  << Flash Memory >> As another specific form of the present invention, one nonvolatile storage device is used regardless of the rewrite control mode of rewriting to another section or rewriting to the same section. It may be realized as a flash memory chip formed on the semiconductor substrate.

  << Memory Card >> As another specific form of the present invention, when the rewrite control form in which rewriting is performed in units of erasure and writing is adopted, the correspondence between the logical address and the physical address is recombined for each rewriting. In this respect, the nonvolatile memory device is realized as a memory card. That is, a flash memory chip having the memory array and the data buffer, and a memory card controller chip having the control circuit and connected to the flash memory chip, the memory card controller chip having a host interface function.

[2] << Batch rewriting to another section >>
The nonvolatile memory device of a specific form of the present invention from the viewpoint of rewriting to the separate section has a memory array (2), a data buffer (4), and a control circuit (11, 22). The memory array has a plurality of storage partitions (SEC) having a plurality of erase and write units (BLK) each having a plurality of electrically erasable and writable nonvolatile memory cells (MC). Nonvolatile memory cells included in the erase and write units share a word line (WL) connected to their selection terminals. The data buffer has a storage capacity of at least one erase and write unit. In response to an instruction to rewrite the storage information, the control circuit controls batch rewriting of information on a storage partition including an erasure and write unit to be rewritten to another storage partition. In the batch rewrite control, the storage information of the first unit is read into the data buffer with respect to the plurality of erase and write unit arrays arranged in the storage partition to be rewritten, and two units from the top in the rewrite destination partition are read. Erase and write the storage information read into the data buffer in the first unit, then read new data into the data buffer, erase and erase for the write unit, and erase and write for the write unit. Sequentially change to the next erase and write unit in the one direction, and sequentially repeat the read, erase and write processes until writing to the erase and write unit located at the end point in the one direction is completed, and store the rewrite source This is control for exchanging the address arrangement between the partition and the rewrite destination storage partition.

  In the batch batch rewriting to another partition, similarly to the above, the order of erase and write with respect to the erase and write units in the storage partition is controlled in one direction with respect to the arrangement order of the erase and write units. It is possible to limit the influence of the capacitive coupling that can be varied to the influence from one adjacent direction. Furthermore, when writing is performed, the unit adjacent to the one direction ahead of the unit to be written is erased first, so that the influence from the adjacent one direction can be limited to writing.

  As a more specific form of the present invention, the control circuit performs erasure read into the data buffer and data modification for the write target unit on the data buffer in rewrite control.

<Initial writing>
As another specific mode of the present invention, the initial writing to the storage partition may be performed by sequentially repeating erasing and writing, or writing by erasing the storage partition first.

  In the former case, in response to an initial write instruction to the storage partition, the control circuit erases two consecutive units in one direction from the beginning with respect to an array of a plurality of erase and write units arranged in the storage partition to be rewritten. Write to the first unit, and then sequentially change each target of erasing and writing to the writing unit, and writing to the erasing and writing unit to the next erasing and writing unit in the one direction, Control is performed to sequentially repeat the erasing and writing processes until the writing to the erasing and writing units located at the end point in the one direction is completed.

  In the latter case, in response to the initial write instruction to the storage partition, the control circuit erases all the erase and write units of the storage partition, and sequentially writes the erase and write target units in order from the beginning to the end. Repeat the control to perform.

[3] << Batch rewriting to the same section >>
The nonvolatile memory device of a specific form of the present invention from the viewpoint of rewriting the same section has a memory array (2), a data buffer (4), and a control circuit (11). The memory array has a plurality of storage partitions (SEC) having a plurality of erase and write units (BLK) each having a plurality of electrically erasable and writable nonvolatile memory cells (MC). Nonvolatile memory cells included in the erase and write units share a word line (WL) connected to their selection terminals. The data buffer has a storage capacity of at least three of the erase and write units. The control circuit controls batch rewriting of a storage partition including an erasure and write unit to be rewritten in response to a rewrite instruction of stored information. The batch rewrite control reads storage information of three consecutive units in one direction from the top to the plurality of erasure and write unit arrays arranged in the storage partition to be rewritten, from the top in the storage partition. The two units are erased, the first unit is written, then new data is read into the data buffer, erased and erased for the writing unit, and erased and written to the writing unit. This is a control that sequentially changes to the next erasing and writing unit in the direction and sequentially repeats the reading, erasing and writing processes until writing to the erasing and writing unit located at the end point in the one direction is completed.

  Even in the case of batch rewriting to the same partition, as described above, the order of erasing and writing with respect to the erasing and writing units in the storage partition is controlled in one direction with respect to the arrangement order of the erasing and writing units. It is possible to limit the influence of the capacitive coupling that can be varied to the influence from one adjacent direction. Furthermore, when writing is performed, the unit adjacent to the one direction ahead of the unit to be written is erased first, so that the influence from the adjacent one direction can be limited to writing.

[4] << Erasing and rewriting process in writing units >>
The nonvolatile memory device from the viewpoint of performing rewriting processing in units of erasing and writing includes a memory array (2), a data buffer (4), and a control circuit (11, 22). The memory array has a plurality of storage sections having a plurality of erase and write units each having a plurality of nonvolatile memory cells that can be electrically erased and written. Nonvolatile memory cells included in the erase and write units share a word line connected to their selection terminals. The data buffer has a storage capacity of at least one erase and write unit. In response to the rewrite instruction of the storage information, the control circuit writes the storage information for each erase and write unit to be rewritten in the erase and write unit of another partition, and the correspondence between the logical address and the physical address Control unit rewriting to recombine. In the unit rewriting control, the unit to be erased and written is read into the data buffer and modified, and the erased and written unit of the write target in the storage partition of the write destination and the next unit are erased, The modified data is written to the unit of the writing destination, and the selection order of the unit to be written in the other section is one direction from the head of the section to the end point.

  In the rewriting process in the erase and write units, as described above, the order of the erase and write in the storage partition with respect to the erase and write units is controlled in one direction with respect to the arrangement order of the erase and write units. It is possible to limit the influence of the capacitive coupling that can vary the influence from one adjacent direction. Furthermore, when writing is performed, the unit adjacent to the one direction ahead of the unit to be written is erased first, so that the influence from the adjacent one direction can be limited to writing. Since the correspondence between the logical address and the physical address is recombined every time rewriting, a new processing time is required, but the above-described batch rewriting for the storage partition is not required.

<Overall configuration of flash memory>
FIG. 2 shows a flash memory. The flash memory 1 is formed on a single semiconductor substrate such as single crystal silicon.

  The flash memory 1 is not particularly limited, but has four memory banks BNK0 to BNK3. Each of the memory banks BNK0 to BNK3 has the same configuration and can be operated in parallel. In the figure, the configuration of the memory bank BNK0 is typically illustrated in detail. The memory banks BNK0 to BNK3 include a memory array (ARY) 2, an X decoder (XDEC) 3, and a data buffer (DBUF) 4.

  The memory array 2 has a large number of nonvolatile memory cells that can electrically rewrite stored information. The nonvolatile memory cell has a stacked gate structure in which a control gate is overlapped with an insulating film on a floating gate which is a charge storage region. Although not particularly limited, each nonvolatile memory cell stores 2 bits of data. In short, information is stored in four values. The four values are, for example, four values “11”, “10”, “00”, and “01”. The stored information “11” is obtained by an erasing process that is initialization for the nonvolatile memory cell. The erasing process is not particularly limited, but the circuit ground potential is applied to the source, drain, and well of the nonvolatile memory cell, and a negative high voltage is applied to the control gate to move the electrons in the charge storage region. By doing so, the threshold voltage is lowered. The stored information “10”, “00”, “01” is obtained by program processing (write processing). The write process is not particularly limited, but a current is caused to flow from the drain to the source of the nonvolatile memory cell, hot electrons are generated on the substrate surface at the source end, and this is injected into the floating gate by the electric field generated by the high voltage of the control gate. Thus, the threshold voltage is increased. The target threshold voltage is different depending on the stored information “10”, “00”, “01”. Read processing is performed by precharging a bit line in advance, selecting a nonvolatile memory cell with a predetermined read determination level as a word line selection level, and storing information by changing a current flowing in the bit line or a voltage level appearing on the bit line. Is set to be detectable. The word line selection level differs depending on the storage information “11”, “10”, “00”, “01”. FIG. 3 illustrates the threshold voltage distribution of the nonvolatile memory cell. VRW1 to VRW3 are read word line selection levels. Above and below the read word line selection level, a predetermined voltage margin is secured between the upper and lower skirts of the threshold voltage distribution.

  The memory array 2 has a read / write circuit (not shown) connected to the bit line. The read / write circuit latches the storage information read to the bit line in the read process, and controls the bit line potential according to the write data in the write process. Although not particularly limited, the erase and write units in the memory array 2 are word line units, and the number of data bits is, for example, 1024 bits. The X decoder 3 selects a word line.

  The data buffer 4 is a temporary storage area for write data to the memory array 2 and read data from the memory array 2. Although not particularly limited, the data buffer 4 is configured by SRAM. Although not particularly limited, the interface between the data buffer 4 and the memory array 2 is performed in the number of data bits in units of the word lines, and the interface with the external input / output buffer (IOBUF) 10 is performed in units of 16 bits. Access control to the data buffer 4 is performed by an internal controller (TCNT) 11.

  The external input / output terminals I / O 1 to I / O 16 are also used as address input terminals, data input terminals, data output terminals, and command input terminals, and are connected to the external input / output buffer 10. The address, data, and command supplied to the external input / output buffer 10 are supplied to the internal controller 11.

  The control signal buffer (CSBUF) 12 is supplied with a chip enable signal / CE, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal / WE, a read enable signal / RE, and the like as external access control signals. Is done. The symbol “/” attached to the head of a signal means that the signal is low enable.

  The internal controller 11 controls the inside of the flash memory 1 according to the access control signal and data, address and command supplied thereto. The flash memory (device) 1 is made active (operable) by the low level of the chip enable signal / CE, and the flash memory 1 is made standby (operation stopped) by the high level. Data is output from the external input / output terminals I / O1 to I / O16 in synchronization with the clock change of the read enable signal / RE. The command, address, and data are taken into the flash memory 1 in synchronization with the rising edge of the write enable signal / WE. When the command latch enable signal CL is at a high level (“H”), data taken from the external input / output terminals I / O1 to I / O16 is recognized as a command in synchronization with the rising edge of / WE. When the address latch enable signal ALE is at a high level, data taken from the external input / output terminals I / O1 to I / O16 is recognized as an address in synchronization with the rising edge of / WE.

  The internal controller 11 performs interface control according to the access control signal and the like, and controls internal operations such as an erase operation, a write operation, and a read operation according to an input command or the like. The internal controller 11 includes hard wired control logic or program control logic for erasure control, read control, write control, and the like. Vcc is a power supply voltage, and Vss is a ground voltage. The high voltage required for the writing process and the erasing process is not particularly limited, but is generated by an internal booster circuit (not shown) based on the power supply voltage Vcc.

《Memory array》
FIG. 4 illustrates the configuration of the memory array 2. For example, the memory array 2 is composed of a plurality of partitions SEC (SEC_1 to SEC_n), and each partition SEC has a plurality of blocks BLK which are erase and write units. The plurality of partitions SEC share a plurality of main bit lines MBL_1 to MBL_j. Each partition SEC includes a plurality of nonvolatile memory cells MC connected in parallel in a row, for example, corresponding to each main bit line MBL_1 to MBL_j. One diffusion layer of the data input / output terminal of the nonvolatile memory cell MC forms a common drain, and the other diffusion layer forms a common source. The diffusion layer that constitutes the common drain constitutes a sub bit line SBL that is made conductive to the corresponding main bit line MBL via the selection switch Md. The diffusion layers constituting the common source are commonly connected to the common line CSL via the selection switch Ms. Here, for convenience, the names of the source and drain of the nonvolatile memory cell MC are based on the direction of the write current in the write operation. The selection switches Md and Ms are used for selecting the section SEC, and a part of the address decode signal is used for controlling the selection switches Ms and Md as in the word line.

  In the memory array 2, the control gate of the nonvolatile memory cell MC is connected to the word line WL. Although not particularly limited, it is assumed that the erase process, the write process, and the read process for the nonvolatile memory cell MC are performed in units of word lines WL.

  In the read process, after precharging the main bit line MBL, the main bit line MBL is discharged and selected if the threshold voltage of the nonvolatile memory cell MC selected by the selection of the word line WL is lower than the word line selection level. If the threshold voltage of the nonvolatile memory cell MC is higher than the selection level of the word line WL, the main bit line MBL maintains the precharge level. This change in the potential of the main bit line MBL is detected by a sense latch (not shown) of the main bit line MBL. The read / write circuit (not shown) obtains four-value storage information read from each memory cell MC through a predetermined logical operation on the information sequentially obtained in the sense latch. The storage information read from the memory array 2 in this way is stored in the data buffer 4.

  The erasing process is a process of causing the threshold voltage to fall within the threshold voltage distribution corresponding to the write data “11” by alternately applying the erase voltage and the verify process. For example, the erase voltage application process is performed by setting the selected word line WL to a negative voltage of −18V, the drain and source of the nonvolatile memory cell MC to be floating, and applying the well voltage to 0V. As a result, electrons in the floating gate are extracted, and the threshold voltage of the nonvolatile memory cell MC is lowered. The erase voltage application process is repeated until the verification process confirms that the threshold voltage has entered the desired threshold voltage distribution.

  The writing process is a process of causing the threshold voltage to fall within the threshold voltage distribution corresponding to the write data by alternately applying the write voltage and the verify process. For example, the write voltage is applied by setting the selected word line WL to 18V, the drain of the memory cell MC to 4.5V, the source to float, and the well voltage to 0V. As a result, electrons are injected into the floating gate, and the threshold voltage of the nonvolatile memory cell MC is increased. The write voltage application process is repeated until it is confirmed in the verify process that the threshold voltage has entered the desired threshold voltage distribution. Note that a method other than the hot electron writing method in which hot electrons accelerated by the channel electric field are injected into the floating gate can be used for the application process of the writing voltage.

《One-way rewriting》
A basic control mode of rewriting and initial writing of the partition SEC by the internal controller 11 will be described. In response to the rewrite of the storage information or the initial write instruction, the internal controller 11 changes the order of erasure and write in the target storage partition SEC in one direction with respect to the arrangement order of the erase and write units. When writing is performed, a unit adjacent to the one direction ahead of the unit to be written is erased first. For example, as illustrated in FIG. 1, erasing and writing for a partition having blocks BLK1 to BLK9 are taken as an example. Erasing and writing are performed in one direction from the first block BLK1 of the partition toward the end block BLK9. First, erase and write first block BLK1 and next block BLK2 are erased (Erase) (STP1). In the figure, the processing actually performed at each step is surrounded by a thick frame. Next, a writing process (Program) for the first block BLK1 is performed (STP2). Thereafter, the block to be erased is advanced to the next block BLK3 (STP3), and the block to be written is advanced to the next block BLK2 (STP4). Similarly, the process of advancing the erase process target block to the next block and the process of advancing the write process target block to the next block are repeated (STP5 to STP14), and finally the write process is performed on the block BLK9 (STP15). Terminate the process.

  FIG. 5 schematically shows a planar arrangement relationship of the nonvolatile memory cells. For example, the floating gate of the nonvolatile memory cell MC1 is capacitively coupled with the floating gates of the peripheral nonvolatile memory cells MC2 to MC9. When the state of electrons held in the floating gate of the nonvolatile memory cell MC1 is changed by erasing and writing, the potential change changes the potential of the floating gates of the peripheral nonvolatile memory cells MC2 to MC9. The threshold voltages of the memory cells MC2 to MC9 are undesirably changed. When the erasure and writing target are arbitrary blocks regardless of the control method of FIG. 1, for example, the block BLKj is affected by erasure and writing from the blocks on both sides, BLKi and BLKk. According to the control method of FIG. 1, the order of erasing and writing of blocks in the storage partition to be rewritten is controlled in one direction with respect to the arrangement order of the blocks, so that the capacitive coupling that can vary the threshold voltage It is possible to limit the influence of 1 to the influence from one adjacent direction. Furthermore, when writing, since the block adjacent to the one-way ahead of the write target block is erased first, the influence from the adjacent one direction can be limited to writing. As a result, large fluctuations in threshold voltage due to capacitive coupling between nonvolatile memory cells can be roughly halved.

《Batch rewriting to another block》
A specific rewrite operation control according to the one-way rewrite control mode will be described. First, batch rewrite control for rewriting one entire section including the rewritten block to another section when responding to a rewrite instruction for the block will be described.

  FIG. 6 illustrates a processing procedure by the batch rewriting control to another section. Here, attention is paid to sections SECm and SECn each having four blocks. The section SECm is the rewrite source and the section SECn is the rewrite destination. First, the storage information of the first block BLK1 is read into the data buffer (DBUF) 4 with respect to the array of the plurality of blocks BLK1 to BLK4 arranged in the rewrite target section SECm, and 2 from the top in the rewrite destination section SECn. The blocks BLK1 and BLK2 are erased (Erase), the storage information read into the data buffer (DBUF) 4 is written into the first block BLK1 of the partition SECn, and then new data is read into and erased from the data buffer (DBUF) 4 And writing to the block BLK4 positioned at the end point in the one direction by sequentially changing the target of the erase to the block that is the write unit and the write to the block that is the erase and write unit to the next block in the one direction. Until the above read and erase Sequentially repeating the processing of fine writing. In the example of FIG. 6, the data DATA2 of the block BLK2 in the partition SECm is to be rewritten by the external write data Wdat. The data DATA2 is changed by the external write data Wdat on the data buffer (DBUF) 4, and the rewritten data DATA2m is written into the block BLK2 of the partition SECn.

  In the batch rewriting control to another section, the data arrangement is changed in section units. For example, the internal controller 11 has a partition address table that defines the arrangement of physical addresses of each partition in a variable manner. When the data arrangement is changed in units of partitions in the batch rewrite control to another partition, the physical addresses of the rewrite source partition and the rewrite destination partition may be rearranged in the partition address table. Naturally, when the internal controller 11 responds to an external access, the internal controller 11 refers to the partition address table using the partition address included in the access address supplied from the outside, and accesses the memory array using the partition address corresponding thereto. It becomes necessary to control.

<< Batch rewriting to the same section >>
Next, batch rewriting control for rewriting one entire section including the rewritten block with the same section when responding to a rewrite instruction for the block will be described.

  FIG. 7 illustrates a processing procedure by batch rewriting control to the same section. Here, attention is paid to a partition SECm having four blocks. The data buffer (DBUF) 4 has a storage capacity capable of holding storage information of at least three blocks. First, the storage information of the three consecutive blocks BLK1 to BLK3 is read into the data buffer (DBUF) 4 in one direction from the beginning with respect to the arrangement of the plurality of blocks BLK1 to BLK4 arranged in the rewrite target partition SECm, and the partition SECm is read. The two blocks BLK1 and BLK2 from the head are erased and writing is performed on the head block BLK1. After that, reading new data to the data buffer (DBUF) 4, erasing the block that is an erase and write unit, and writing to the block that is the erase and write unit are set as the next block in the one direction. The reading, erasing and writing processes are sequentially repeated until the writing to the block BLK4 located at the end point in the one direction is completed. In the example of FIG. 7, the data DATA2 of the block BLK2 in the partition SECm is to be rewritten by the external write data Wdat. The data DATA2 is changed by the external write data Wdat on the data buffer (DBUF) 4, and the rewritten data DATA2m is written into the block BLK2 of the partition SECm.

  Since the batch rewrite control is performed on the same partition, the data arrangement is not changed on a partition basis. Accordingly, it is not essential for the flash memory 1 to have a partition address table as shown in FIG.

<Rewriting in units of blocks>
Next, a control for rewriting in units of rewrite blocks when responding to a rewrite instruction for a block will be described.

  FIG. 8 illustrates a processing procedure by rewrite control in units of blocks. Here, attention is paid to the sections SECm and SECn having four blocks. The section SECm is the rewrite source and the section SECn is the rewrite destination. Here, it is assumed that the rewrite source block and the rewrite destination block are designated from outside the flash memory. In response to the rewrite instruction of the stored information, the internal controller 11 writes the stored information to a block in another partition for each block to be rewritten. The correspondence between the logical address of the write source data and the physical address of the write destination block is managed by a memory controller or a card controller (not shown) arranged outside the flash memory. That is, the data of the block to be erased and written is read into the data buffer, the read data is rewritten with the external write data Wdata, and the block that is the erase and write unit of the write target in the write destination partition SECn and the adjacent block Are erased, and the data in the modified data buffer is written into the block which is the unit of the write destination. At this time, the same control as the one-way rewriting is performed, and the selection order of blocks that are units to be written in the write destination partition SECn is set to one direction from the head of the partition to the end point. This control is performed by a memory controller or a card controller (not shown). The rewriting source data may be data of an arbitrary block in an arbitrary section. In the example of FIG. 8, all of the rewriting source data is data of one section SECm, but is not limited thereto. In this case, since the address arrangement of the rewrite source data is changed in units of blocks, it is necessary to recombine the correspondence between the logical address and the physical address for each rewrite. It shall be entrusted to the card controller. When rewriting in units of blocks is adopted, since the correspondence between logical addresses and physical addresses is recombined every time rewriting is performed, a new processing time is required, but the time required for batch rewriting for the above-described partitions is omitted. be able to.

  In order to prevent variation in threshold voltage due to capacitive coupling in non-volatile memory cells in other sections due to erasing and writing during rewriting to another section, rewriting to the same section, and rewriting in block units For example, an interval wider than the word line interval in the storage partition is provided between the word lines of the storage partitions adjacent to each other. In the example of FIG. 6, the switch control lines of the selection switches Ms and Md extend in the word line direction at the boundary between the partitions, thereby increasing the interval between the word lines in the adjacent partitions. Alternatively, although not shown, a dummy word line may be arranged at the end of the partition.

"Memory card"
FIG. 9 shows an example of a flash memory card. The flash memory card 20 includes a flash memory 1, a card controller 22, and an interface terminal 21 on a card board. The card controller 22 performs card interface control according to the memory card specification and access control of the flash memory 1 for responding to the card command. In the access control, the card controller 22 performs control for generating management information for associating the physical address of the block of the flash memory with the logical address and holding the management information in the block. Information indicating the correspondence between logical addresses and physical addresses required every time rewriting is performed in units of blocks is held in the block as the management information. Even when a flash memory that rewrites to another partition or rewrites to the same partition is adopted, the card controller 22 generates management information for associating the physical address of the block BLK of the flash memory with the logical address to generate a block. It is necessary to perform control and the like to be held in the.

  Although not shown, the card controller can be configured on-chip together with the flash memory 1.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, although the case where the unit of the write / erase operation is the word line unit has been described, the present invention is not limited to this and may be performed in units of a plurality of word lines. Alternatively, erasing may be performed in units of a plurality of word lines and writing may be performed in units of word lines. The present invention is not limited to an AND type flash memory. NOR type and NAND type flash memories generally perform erasing in units of a plurality of word lines. For example, erasing in units of word lines is possible by using a method in which a negative voltage is applied to one word line. The present invention can also be applied to a NOR type, NAND type flash memory or the like that performs write / erase operations in units of word lines for the purpose of small-size rewriting. Further, the present invention is not limited to the flash memory, but can be widely applied to an EEPROM and other storage-type nonvolatile memories. The nonvolatile memory device according to the present invention is not limited to a memory card or a single memory, but can be widely applied to a memory on-chip in an LSI (Large Scale Integrated Circuit) such as a system LSI or a microcomputer.

It is operation | movement explanatory drawing which illustrates the process sequence by the one-way rewriting control by flash memory. It is a block diagram of a flash memory. It is explanatory drawing of the threshold voltage distribution of the non-volatile memory cell which performs quaternary storage. 3 is a circuit diagram illustrating a configuration of a memory array 2. FIG. It is a top view which illustrates the mode of capacitive coupling between the adjacent floating gates of a non-volatile memory cell. It is operation | movement explanatory drawing which illustrates the process sequence by the batch rewriting control to another division. It is operation | movement explanatory drawing which illustrates the process sequence by the batch rewriting control to the same division. It is operation | movement explanatory drawing which illustrates the process sequence by the rewriting control in a block unit. It is a block diagram which illustrates a flash memory card.

Explanation of symbols

1 Flash memory BNK0 to BNK3 Memory bank 2 Memory array (ARY)
3 X decoder (XDEC)
4 Data buffer (DBUF)
10 External I / O buffer (IOBUF)
11 Internal controller (TCNT)
12 Control signal buffer (CSBUF)
I / O1 to I / O16 External input / output terminals MC Non-volatile memory cells SEC Partition BLK block MBL Main bit line SBL Sub bit line Md, Ms Select switch WL Word line CSL Common line 20 Memory card 21 Interface terminal 22 Card controller

Claims (20)

A memory array, a data buffer, and a control circuit;
The memory array has a plurality of storage sections each having a plurality of erase and write units each having a plurality of electrically erasable and writable nonvolatile memory cells.
Non-volatile memory cells included in the erase and write unit share a word line connected to the selection terminal,
In response to the rewrite instruction of the storage information, the control circuit controls the erasure and write order for the erase and write units in the storage partition to be rewritten in one direction with respect to the arrangement order of the erase and write units. A non-volatile storage device that performs rewrite control in which when a write is performed, a unit adjacent to the one direction ahead of the write target unit is erased first.   In the rewrite control, the control circuit performs control to set the rewrite destination as another storage partition, rewrites the other storage partition in a batch using the storage information of the rewrite source storage partition, and rewrites the rewrite source storage partition. The non-volatile storage device according to claim 1, wherein the address arrangement with the previous storage partition is exchanged.   In the rewrite control, the control circuit controls the rewrite destination to be the same storage partition as the rewrite source, rewrites the entire rewrite source storage partition, and stores data to be stored in the unit to be erased first. 2. The nonvolatile memory according to claim 1, wherein when there is a data, the data is saved in the data buffer before the erasure, and the saved data is written back to a corresponding erase and write unit that has already been erased adjacent to the one-way destination. Sex memory device.   In the rewrite control, the control circuit sets the rewrite destination as another storage partition, writes the storage information for each erase and write unit to be rewritten into another erase and write unit, and sets the erase and write unit. The non-volatile storage device according to claim 1, wherein the correspondence between the logical address and the physical address of the storage information is recombined for each rewrite.   5. The nonvolatile memory device according to claim 2, wherein an interval wider than a word line interval in the storage section is provided between word lines of adjacent storage sections. The storage section includes a plurality of sub bit lines that are rendered conductive to a main bit line via a selection switch, and a plurality of nonvolatile memory cells having one input / output terminal coupled to each of the sub bit lines, A plurality of word lines arranged in a direction intersecting with the plurality of sub-bit lines, each having a selection terminal of the nonvolatile memory cell coupled thereto, and the other input / output terminals of the plurality of previous nonvolatile memories are commonly connected. Consisting of common wires,
The nonvolatile memory device according to claim 2, wherein the write / erase unit is a nonvolatile memory cell in a word line unit.   7. The non-volatile memory device according to claim 6, wherein each of the non-volatile memory cells has a conductive floating gate as a charge storage region and can store data of 2 bits or more per one.   The nonvolatile memory device according to claim 2, wherein the nonvolatile memory device is a flash memory chip formed on a single semiconductor substrate.   5. A flash memory chip having the memory array and the data buffer, and a memory card controller chip having the control circuit and connected to the flash memory chip, wherein the memory card controller chip has a host interface function. The non-volatile storage device described. A memory array, a data buffer, and a control circuit;
The memory array has a plurality of storage sections each having a plurality of erase and write units each having a plurality of electrically erasable and writable nonvolatile memory cells.
Non-volatile memory cells included in the erase and write unit share a word line connected to the selection terminal,
The data buffer has a storage capacity of at least one of the erase and write units;
In response to the instruction to rewrite the storage information, the control circuit controls batch rewriting to another storage partition for information on the storage partition including the erasure and write unit to be rewritten,
In the batch rewrite control, the storage information of the first unit is read into the data buffer with respect to the plurality of erase and write unit arrays arranged in the storage partition to be rewritten, and two units from the top in the rewrite destination partition are read. Erase and write the storage information read into the data buffer in the first unit, then read new data into the data buffer, erase and erase for the write unit, and erase and write for the write unit. Sequentially change to the next erase and write unit in the one direction, and sequentially repeat the read, erase and write processes until writing to the erase and write unit located at the end point in the one direction is completed, and store the rewrite source A non-volatile storage device which is a control for switching the address arrangement between a partition and a rewrite destination storage partition.   The nonvolatile memory device according to claim 10, wherein the control circuit performs data modification on the data buffer with respect to a unit to be erased and written into the data buffer in rewrite control.   In response to the initial write instruction for the storage partition, the control circuit erases two consecutive units in one direction from the top to the plurality of erase and write unit arrays arranged in the storage partition to be rewritten, Write to the unit, and then sequentially change each target of erasure and erase to the write unit and erase and write to the write unit to the next erase and write unit in the one direction, 12. The non-volatile memory device according to claim 11, wherein control for sequentially repeating the erasing and writing processes is performed until the writing to the erasing and writing unit located at the end point is completed. A memory array, a data buffer, and a control circuit;
The memory array has a plurality of storage sections each having a plurality of erase and write units each having a plurality of electrically erasable and writable nonvolatile memory cells.
Non-volatile memory cells included in the erase and write unit share a word line connected to the selection terminal,
The data buffer has a storage capacity of at least three of the erase and write units;
In response to a rewrite instruction for storage information, the control circuit controls batch rewriting for a storage partition including an erase and write unit to be rewritten,
The batch rewrite control reads storage information of three consecutive units in one direction from the top to the plurality of erasure and write unit arrays arranged in the storage partition to be rewritten, from the top in the storage partition. The two units are erased, the first unit is written, then new data is read into the data buffer, erased and erased for the writing unit, and erased and written to the writing unit. Non-volatile storage device which is a control that sequentially changes to the next erasing and writing unit in the direction and sequentially repeats the reading, erasing and writing processes until writing to the erasing and writing unit located at the end point in the one direction is completed .   The non-volatile memory device according to claim 13, wherein the control circuit performs data modification on the data buffer with respect to a unit to be erased and written into the data buffer in rewrite control.   In response to the initial write instruction for the storage partition, the control circuit erases two consecutive units in one direction from the top to the plurality of erase and write unit arrays arranged in the storage partition to be rewritten, Write to the unit, and then sequentially change the target of erasure and erase to the write unit, and erase and write to the write unit to the next erase and write unit in the one direction, The non-volatile memory device according to claim 14, wherein control for sequentially repeating the erasing and writing processes is performed until writing to an erasing and writing unit positioned at an end point is completed. A memory array, a data buffer, and a control circuit;
The memory array has a plurality of storage sections each having a plurality of erase and write units each having a plurality of electrically erasable and writable nonvolatile memory cells.
Non-volatile memory cells included in the erase and write unit share a word line connected to the selection terminal,
The data buffer has a storage capacity of at least one of the erase and write units;
In response to the rewrite instruction of the storage information, the control circuit writes the storage information for each erase and write unit to be rewritten in the erase and write unit of another partition, and the correspondence between the logical address and the physical address Control unit rewriting,
In the unit rewriting control, the unit to be erased and written is read into the data buffer and modified, and the erased and written unit of the write target in the storage partition of the write destination and the next unit are erased, A non-volatile storage device in which the modified data is written to a write destination unit, and the selection order of units to be written in the other partition is one direction from the start to the end of the partition.   14. The nonvolatile memory device according to claim 10, wherein the memory array, the data buffer, and the control circuit are provided in a flash memory chip formed on one semiconductor substrate.   17. A flash memory chip having the memory array and the data buffer, and a memory card controller chip having the control circuit and connected to the flash memory chip, wherein the memory card controller chip has a host interface function. The non-volatile storage device described. The storage section includes a plurality of sub bit lines that are rendered conductive to a main bit line via a selection switch, and a plurality of nonvolatile memory cells having one input / output terminal coupled to each of the sub bit lines, A plurality of word lines arranged in a direction intersecting with the plurality of sub-bit lines, each having a selection terminal of the nonvolatile memory cell coupled thereto, and the other input / output terminals of the plurality of previous nonvolatile memories are commonly connected. Consisting of common wires,
17. The nonvolatile memory device according to claim 10, 13 or 16, wherein said write / erase unit is a nonvolatile memory cell in word line unit.   The nonvolatile memory device according to claim 19, wherein each of the nonvolatile memory cells has a conductive floating gate as a charge accumulation region, and can store data of 2 bits or more per one.

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