JP2007248142A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of accurately measuring the phase difference between the reference clock signal and data to be measured and the pulse width of data to be measured, without using a high-speed timing signal. <P>SOLUTION: The semiconductor device comprises delay clock signal generating sections 30, 50, 80 and DC1-DCn for generating a plurality of delay clock signals DCK1-DCKn, by sequentially delaying the reference clock signal CK1 at a fixed interval, and the phase difference measuring sections PC1-PCn90 for comparing the plurality of delay clock signals with the data S10 to be measured, respectively, and measuring the phase difference between the reference clock signal and the data to be measured. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device.

  In an optical disc recording / reproducing apparatus, for example, when data is recorded on an optical disc, data having an appropriate pulse width is first recorded and then reproduced, and if the pulse width of the reproduced data is measured with high accuracy, data to be recorded is recorded. It is possible to record the data after optimally adjusting the pulse width.

  By the way, the pulse width of the reproduction data is measured using a clock signal. For example, the pulse width of the reproduction data is measured by counting the number of clocks in the measurement target pulse period in units of one cycle of the clock signal. .

  As described above, the accuracy in measuring the pulse width of the reproduction data depends on the frequency of the clock signal. Therefore, when the pulse width of the reproduction data changes to, for example, 1/16 by reproducing the optical disk at a high speed, the pulse width of the reproduction data is set in units of 1/16 period of the clock signal in order to maintain the measurement accuracy. In this case, a clock signal having a high frequency exceeding 3 GHz, for example, must be generated.

  When such a high-speed clock signal is generated and used, the signal waveform of the clock signal is dull due to the parasitic capacitance generated in the wiring inside the circuit, and the pulse width of the reproduction data cannot be measured with high accuracy. There was a problem.

The following is a list of literature names related to circuits for measuring the pulse width of reproduction data.
JP-A-5-81678

  The present invention provides a semiconductor device and a phase difference measurement method thereof capable of measuring a phase difference between a reference clock signal and measurement target data and a pulse width of the measurement target data with high accuracy without using a high-speed clock signal. provide.

A semiconductor device according to one embodiment of the present invention includes:
A delayed clock signal generator that generates a plurality of delayed clock signals by sequentially delaying the reference clock signal at regular intervals;
A phase difference measuring unit that compares the phase of each of the plurality of delayed clock signals and the measurement target data and measures the phase difference between the reference clock signal and the measurement target data based on the comparison result, and
The delayed clock signal generator is
A clock signal generation circuit that generates a clock signal that determines the accuracy in measuring the phase difference; and
A clock number measuring circuit that counts the number of clocks of the clock signal, which is present in one period of the reference clock signal;
A plurality of delay circuits in which a plurality of delay elements are connected in series, and switching elements are respectively connected to the output sides of the plurality of delay elements;
A delay element stage number control circuit that generates a delay element stage number control signal for controlling the number of stages of the delay elements connected to the output side in each of the plurality of delay circuits based on the clock number output from the clock number measurement circuit And.

A phase difference measurement method for a semiconductor device according to an aspect of the present invention includes:
Generating a plurality of delayed clock signals by sequentially delaying the reference clock signal at regular intervals;
Comparing the phase of each of the plurality of delayed clock signals and the measurement target data, and measuring the phase difference between the reference clock signal and the measurement target data based on the comparison result, and
Generating the delayed clock signal comprises:
Generating a clock signal that determines the accuracy in measuring the phase difference;
Counting the number of clocks of the clock signal present within one period of the reference clock signal;
Based on the number of clocks, the delay connected to the output side in each of a plurality of delay circuits in which a plurality of delay elements are connected in series and a switching element is connected to the output side of the plurality of delay elements, respectively. Generating a delay element stage number control signal for controlling the number of element stages.

  According to the semiconductor device and the phase difference measurement method of the present invention, the phase difference between the reference clock signal and the measurement target data and the pulse width of the measurement target data can be measured with high accuracy without using a high-speed clock signal. Can do.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(1) First Embodiment FIG. 1 shows a configuration of a reproduction data pulse width measuring circuit 10 according to a first embodiment of the present invention. The reproduction data pulse width measurement circuit 10 provides the provisional pulse width measurement circuit 20 with reproduction data S10 reproduced from an optical disc (not shown) and a clock signal CK1 obtained from the reproduction data S10.

  The provisional pulse width measurement circuit 20 counts the number of clocks in the measurement target pulse period in the reproduction data S10 by using one period of the clock signal CK1 as a unit (one clock), thereby reducing the pulse width of the reproduction data S10. The measured value is output to the pulse width calculation circuit 40 as temporary pulse width data S20.

  For example, as shown in FIG. 3, the provisional pulse width measurement circuit 20 has a signal level of the reproduction data S10 (FIG. 3A) of “H” at the rising timing of the clock signal CK1 (FIG. 3B). By determining whether the level is “L” or “L”, the pulse width (integer value) of the reproduction data S10 is measured. In this case, the “L” level pulse width is measured as “3”, and the “H” level pulse width is measured as “2”. Note that a half cycle of the clock signal CK1 may be used as a unit of measurement.

  The ring oscillator 50 includes a delay circuit 60 and an inverter 70, and generates a clock signal CK2 that is used to generate a plurality of clock signals having different phases (delay times) based on the clock signal CK1.

  The delay circuit 60 is formed by connecting at least one delay element (not shown) in series. The cycle of the clock signal CK2 is determined by the delay time of the delay circuit 60. Specifically, the ½ cycle of the clock signal CK2 corresponds to the delay time of the delay circuit 60.

  The clock number measurement circuit 30 is provided with the clock signals CK1 and CK2, and counts the number of clocks of the clock signal CK2 existing within one period of the clock signal CK1, with one period of the clock signal CK2 as one clock. The clock number data S30 is output to the delay element stage number control circuit 80.

  Based on the given clock number data S30, the delay element stage number control circuit 80 represents the delay element stage number representing a delay time corresponding to 1 / n period of the clock signal CK1 (a time obtained by multiplying one period of the clock signal CK2 by an integer). A selection signal SE1 is generated and output to the delay circuit DC1.

  The delay circuit DC1 is formed by serially connecting a plurality of delay elements DE having the same delay time as that of a delay element (not shown) included in the delay circuit 60, as shown in FIG. A switch SW is connected to the output side of each delay element DE.

  Based on the given delay element stage number selection signal SE1, the delay circuit DC1 selectively turns on only a desired switch SW among a plurality of switches SW, and turns off the other switches SW. A delayed clock signal DCK1 obtained by delaying the clock signal CK1 by 1 / n cycle is generated.

  Here, for example, the number of stages of delay elements (not shown) forming the delay circuit 60 of the ring oscillator 50 is 64, and 1/16 period of the clock signal CK1 (that is, one period of the clock signal CK1 is one precision). A case where the pulse width of the reproduction data S10 is measured in units of 1/16 accuracy in the case of the above will be described.

  As shown in FIG. 4, when the number of clocks of the clock signal CK2 existing in one cycle of the clock signal CK1 (FIG. 4A) is 32 (FIG. 4B), the delay circuit DC1 The delayed time is 1/16 period of the clock signal CK1, that is, the number of clocks of the clock signal CK2 is two.

  In the ring oscillator 50, assuming that the delay time of the inverter 70 is sufficiently smaller than the delay time of the delay circuit 60 and can be ignored, the “H” level is delayed to generate one clock signal CK2. After being delayed by the circuit 60, the “L” level inverted by the inverter 70 needs to be delayed by the delay circuit 60, and the delay circuit 60 needs to be operated twice.

  Therefore, in order for the delay circuit DC1 to delay the clock signal CK1 by 1/16 period, the delay element DE has 256 stages (= 64 (the number of delay elements forming the delay circuit 60) × 2 (the delay circuit 60 operates). Number of times) × 2 (the number of clocks of the clock signal CK2)). In this case, the delay circuit DC1 turns on only the switch SW connected to the output side of the 256th delay element DE from the input side.

  Similarly, delay element stage number control circuit 80 generates delay element stage number selection signals SE2 to SEn based on clock number data S30, and outputs these to delay circuits DC2 to DCn, respectively. The delay circuits DC2 to DCn are configured in the same manner as the delay circuit DC1. In the delay circuit DC2, a delay clock signal obtained by delaying the clock signal CK1 by 2 / n cycles is connected to the output side of a delay element DE having twice the number of delay elements DE connected to the output side in the delay circuit DC1. DCK2 is generated.

  Similarly, in the delay circuit DCn, the delay element DE having n stages as many as the number of stages of the delay elements DE connected to the output side in the delay circuit DC1 is connected to the output side, and the clock signal CK1 is cycled n / n. A delayed delayed clock signal DCKn is generated.

  As a result, the delayed clock signals DCK1 to DCKn that are sequentially delayed at intervals of 1 / n period of the clock signal CK1 with the clock signal CK1 as a reference are output from the delay circuits DC1 to DCn, respectively.

  The phase comparator PC1 is provided with the delayed clock signal DCK1 and the reproduction data S10, and compares the phase of the rising edge of the delay clock signal DCK1 with the rising or falling edge forming the measurement target pulse in the reproduction data S10. Then, the comparison result is output to the phase difference measuring circuit 90 as a comparison result signal CR1.

  Similarly, the phase comparators PC2 to PCn are supplied with the delayed clock signals DCK2 to DCKn and the reproduction data S10, respectively, and form rising pulses of the delayed clock signals DCK2 to DCKn and pulses to be measured among the reproduction data S10. The phases of the rising and falling edges are compared, and the comparison results are output to the phase difference measuring circuit 90 as comparison result signals CR2 to CRn.

  Here, for example, when measuring the pulse width of the reproduction data S10 in units of 1/16 period of the clock signal CK1, 16 phase comparators PC1 to PC16 are provided.

  In this case, as shown in FIG. 5, for example, the phase comparator PC4 has a rising edge of the delayed clock signal DCK4 (FIG. 5C) obtained by delaying the clock signal CK1 (FIG. 5B) by 4/16 cycles. The phase of the reproduction data S10 (FIG. 5A) is compared with the rising edge forming the measurement target pulse.

  As a result, when the rising edge of the reproduction data S10 (FIG. 5A) arrives later than the rising edge of the delayed clock signal DCK4 (FIG. 5C), the phase comparator PC4 compares the comparison result signal CR4. When the rising edge of the reproduction data S10 (FIG. 5A) arrives earlier, the “H” level is output as the comparison result signal CR4. In this case, the phase comparator PC4 outputs the “L” level as the comparison result signal CR4.

  In the same manner, for example, the phase comparator PC8, for example, causes the rising edge of the reproduction data S10 (FIG. 5 (a)) to arrive later than the rising edge of the delayed clock signal DCK8 (FIG. 5 (d)). The “L” level is output as the signal CR8.

  Further, for example, since the rising edge of the reproduction data S10 (FIG. 5A) arrives later than the rising edge of the delayed clock signal DCK12 (FIG. 5E), the phase comparator PC12 receives “ L ”level is output.

  Further, for example, the phase comparator PC16 has a rising edge of the reproduction data S10 (FIG. 5 (a)) earlier than the rising edge of the delayed clock signal DCK16 (FIG. 5 (f)). H ”level is output.

  Based on the given comparison result signals CR1 to CRn, the phase difference measuring circuit 90 has rising or falling edges that form a measurement target pulse in the reproduction data S10 in units of 1 / n period of the clock signal CK1. The phase difference (that is, the time difference) from the rising edge of the clock signal CK1 is measured, and the phase difference data S40 measured this time is output to the phase difference data holding circuit 100 and the pulse width calculation circuit 40.

  The phase difference data holding circuit 100 holds the phase difference data S40 measured last time with respect to the previous falling or rising edge that has arrived earlier than the rising or falling edge of the current measurement target. The previously measured phase difference data S50 is output to the pulse width calculation circuit 40. At this time, when the phase difference data S40 measured this time is given from the phase difference measurement circuit 90, the held phase difference data S40 is updated.

  The pulse width calculation circuit 40 generates a 1 / n period (1 / n accuracy) of the clock signal CK1 based on the temporary pulse width data S20, the phase difference data S40 measured this time, and the phase difference data S50 measured last time. ) As a unit, the pulse width of the reproduction data S10 is measured, and this is output as pulse width data S60.

  For example, as shown in FIG. 3, the pulse width calculation circuit 40 is previously measured from one cycle of the temporary pulse width data S20, the phase difference data S40 measured this time, and the clock signal CK1 (FIG. 3B). The pulse width data S60 is generated by adding the data S55 obtained by subtracting the phase difference data S50.

  As described above, according to the present embodiment, the phase difference between the reproduction data S10 and the clock signal CK1 and the pulse width of the reproduction data S10 can be measured with high accuracy without using a high-speed clock signal.

  Further, according to the present embodiment, even when the cycle of the clock signal CK1 changes due to the change in the reproduction speed of the optical disc, the delay circuits DC1 to DC1 are changed according to the change in the cycle of the clock signal CK1. The number of stages of delay elements DE connected to the output side in DCn changes. Therefore, the delayed clock signals DCK1 to DCKn that are sequentially delayed by the 1 / n cycle interval of the clock signal CK1 can be automatically generated regardless of the reproduction speed of the optical disk, and the reproduction data pulse width measuring circuit 10 can be There is no need to control from the beginning.

(2) Second Embodiment FIG. 6 shows a configuration of a semiconductor integrated circuit 110 according to a second embodiment of the present invention. In addition, the same code | symbol is attached | subjected to the same element as the element shown by FIG. 1, and description is abbreviate | omitted.

  In the present embodiment, a case will be described in the ring oscillator 50 where the delay time of the inverter 70 is sufficiently smaller than the delay time of the delay circuit 60 and is not negligible. In such a case, in order to reduce the influence of the delay time of the inverter 70 in one cycle of the clock signal CK2 generated by the ring oscillator 50, if the number of stages of delay elements (not shown) forming the delay circuit 60 is increased, the delay is increased. As the delay time of the circuit 60 increases, the cycle of the clock signal CK2 becomes longer. In this case, the number of clocks measured by the clock number measuring circuit 30 is reduced.

  For example, a case where one cycle of the clock signal CK1 is 38.2 ns, a delay time per delay element of the delay circuit 60 is 0.2 ns, and the number of delay elements of the delay circuit 60 is 64 is described.

  In this case, since one cycle of the clock signal CK2 generated in the ring oscillator 50 is 25.6 ns (= 0.2 × 64 × 2), the number of clocks measured in the clock number counting circuit 30 is 1. 49 (= 38.2 / 25.6).

  Here, it is assumed that the number of clocks measured in the clock number counting circuit 30 is 1.5, and the order of the reproduction data S10 and the clock signal CK1 is set in units of 1/32 period (1/32 accuracy) of the clock signal CK1. When measuring the phase difference, the number of stages of the delay elements DE required in the delay circuit DC1 is 6 stages (= 64 (number of stages of delay elements forming the delay circuit 60) × 2 (number of times the delay circuit 60 is operated) × 1.5 / 32 (the number of clocks of the clock signal CK2 in 1/32 period of the clock signal CK1)).

  However, the clock number measuring circuit 30 can only count the number of clocks with an integer value. Therefore, the number of clocks measured by the clock number counting circuit 30 is “1” or “2”. Therefore, for example, the number of stages of the delay elements DE connected to the output side in the delay circuit DC1 is 4 (= 64 × 2 × 1/32) or 8 (= 64 × 2 × 2/32).

  Even if the number of stages of the delay elements DE connected to the output side in the delay circuit DC1 is four or eight, an error occurs in the delay clock signal DCK1 output from the delay circuit DC1. The phase difference between the reproduction data S10 and the clock signal CK1 cannot be measured in units of 1/32 period (1/32 accuracy) of the clock signal CK1.

  Therefore, in the case of the present embodiment, after the frequency divider 120 is provided and the clock signal CK1 is divided by the frequency divider 120 to generate the clock signal CK3, the clock signal CK3 exists within one cycle of the clock signal CK3. The clock number measuring circuit 30 counts the number of clocks of the clock signal CK2.

  For example, when the clock signal CK1 is divided by 256 by the frequency divider 120 and the period is multiplied by 256, the number of clocks measured in the clock number counting circuit 30 is 384 (= 1.5 × 256). The number of stages of delay elements DE connected to the output side in the delay circuit DC1 is 6 (= 64 × 2 × 384/32/256 (frequency division number)).

  As described above, according to the present embodiment, a larger number of clocks can be counted in the clock number measuring circuit 30, and therefore the number of stages of the delay elements DE connected to the output side in the delay circuits DC1 to DCn can be accurately determined. Can be controlled. Thereby, the delayed clock signals DCK1 to DCKn can be generated with high accuracy, and therefore the phase difference between the reproduction data S10 and the clock signal CK1 and the pulse width of the reproduction data S10 can be measured with high accuracy.

  The above-described embodiment is an example and does not limit the present invention. For example, as shown in FIG. 7, a plurality of delay circuits 130 having the same configuration as the delay circuit DC1 may be prepared, and the delay clock signals DCK1 to DCKn may be generated by connecting the plurality of delay circuits 130 in series. .

1 is a block diagram showing a configuration of a reproduction data pulse width measurement circuit according to a first embodiment of the present invention. It is a block diagram which shows the structure of a delay circuit. It is a timing chart in the case of measuring the temporary pulse width of reproduction data. It is a timing chart in the case of counting the number of clocks and determining the number of delay element stages. It is a timing chart in the case of measuring the phase difference between reproduction data and a clock signal. It is a block diagram which shows the structure of the reproduction | regeneration data pulse width measuring circuit by the 2nd Embodiment of this invention. It is a block diagram which shows the structure of the delay circuit by other embodiment of this invention.

Explanation of symbols

10, 110 Playback data pulse width measurement circuit 20 Temporary pulse width measurement circuit 30 Clock number measurement circuit 40 Pulse width calculation circuit 50 Ring oscillator 60 Delay circuit 70 Inverter 80 Delay element stage number control circuit 90 Phase difference measurement circuit 100 Phase difference data holding circuit 120 frequency divider DC delay circuit PC phase comparator DE delay element SE switch

Claims (4)

A delayed clock signal generator that generates a plurality of delayed clock signals by sequentially delaying the reference clock signal at regular intervals;
A phase difference measuring unit that compares the phase of each of the plurality of delayed clock signals and the measurement target data, and measures a phase difference between the reference clock signal and the measurement target data based on the comparison result; and
The delayed clock signal generator is
A clock signal generation circuit that generates a clock signal that determines the accuracy in measuring the phase difference; and
A clock number measuring circuit that counts the number of clocks of the clock signal that is present in one cycle of the reference clock signal;
A plurality of delay circuits in which a plurality of delay elements are connected in series, and switching elements are respectively connected to the output sides of the plurality of delay elements;
A delay element stage number control circuit that generates a delay element stage number control signal for controlling the number of stages of the delay elements connected to the output side in each of the plurality of delay circuits based on the clock number output from the clock number measurement circuit A semiconductor device comprising: A temporary pulse width measuring circuit that measures the pulse width of the measurement target data by counting the number of clocks of the reference clock signal during the pulse period of the measurement target data, and outputs this as a temporary pulse width;
A pulse width calculation circuit that calculates a pulse width of the measurement target data based on the temporary pulse width output from the temporary pulse width measurement circuit and the phase difference output from the phase difference measurement unit; The semiconductor device according to claim 1, further comprising: A frequency divider for dividing the reference clock signal;
The clock number measurement circuit includes:
2. The semiconductor device according to claim 1, wherein the number of clocks of the clock signal existing within one period of the divided clock signal output from the frequency divider is counted. Generating a plurality of delayed clock signals by sequentially delaying the reference clock signal at regular intervals;
Comparing the phase of each of the plurality of delayed clock signals and the measurement target data, and measuring the phase difference between the reference clock signal and the measurement target data based on the comparison result, and
Generating the delayed clock signal comprises:
Generating a clock signal that determines the accuracy in measuring the phase difference;
Counting the number of clocks of the clock signal present within one period of the reference clock signal;
Based on the number of clocks, the delay connected to the output side in each of a plurality of delay circuits in which a plurality of delay elements are connected in series and a switching element is connected to the output side of the plurality of delay elements, respectively. Generating a delay element stage number control signal for controlling the number of element stages. A method for measuring a phase difference of a semiconductor device, comprising:

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