JP2007242888A - Method of manufacturing semiconductor package - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing an accurate semiconductor package which can reduce a cost by increasing a manufacturing efficiency and a yield, and can achieve high-level and more functions by making the package compact and thin, and manufacturing the package with a high density. <P>SOLUTION: A device substrate member 2 having a device 4 and an electrode 10 formed on a semiconductor substrate 3 is integrally formed with a rewiring layer substrate member 5 having a rewiring layer 7 formed on a light-transmitting dummy substrate 6 with a release film 24 disposed therebetween. Thereafter, the release layer 24 is heated by irradiating the resultant structure with a laser beam from the side of the dummy substrate 6 to release the dummy substrate 6 with the release layer 24 as an interface. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor package manufacturing method in which a rewiring layer is formed or packaged on a semiconductor substrate on which a device is formed.

  For example, in various electronic devices such as personal computers, mobile phones, video recorders, and audio devices, miniaturization, multi-functions, and high-functions have been achieved, and accordingly, components and substrates constituting these devices. Are becoming smaller, thinner, lighter, or denser. For example, with regard to wiring technology, in addition to technologies such as multilayering, miniaturization, or multi-pinning of the wiring layer, there are a plurality of CPS (Chip Sise Package) technologies such as flip chip mounting method that directly mounts a bare chip on a substrate and a purpose. A mounting technology such as SIP (system in package) in which three bare chips are combined and stacked three-dimensionally has been researched and developed.

  In the mounting technology, semiconductor packaging technologies such as WLP (wafer-level package) and WLCSP (wafer-level chipsize package) for forming and packaging a rewiring layer on a semiconductor substrate have been researched and developed. According to such a semiconductor packaging technology, it is possible to reduce the thickness of the entire package by eliminating the need for a mounting substrate such as an interposer substrate as in the past, and at the same time, the device and redistribution layer at the quality level of the semiconductor technology. And can be packaged. In addition, such packaging technology can connect the device and the rewiring layer in the shortest time, and it is possible to increase the speed and reduce noise.

  By the way, in the above-mentioned semiconductor packaging technology and multilayer technology, a build-up method is adopted in which wiring layers are sequentially stacked on the main surface of a semiconductor substrate or base substrate together with a device in the same manner as general multilayer wiring substrate technology. Is done. In the build-up method, interlayer connections are made by vias appropriately formed in each wiring layer, but the number of layers is limited depending on conditions such as accuracy of wiring patterns formed in each wiring layer or connection reliability by vias. In addition, the build-up method has a problem that the lithography accuracy and via formation accuracy in the wiring layer forming process are lowered due to the warpage of the substrate and the nonuniformity of the thickness of each layer as the number of stacked layers increases. Further, the build-up method has a problem that the lead time increases proportionally and the yield decreases as the number of layers increases.

  In the conventional semiconductor packaging technology, as described above, after forming the device on the substrate by the semiconductor technology, a multilayer rewiring layer covering the device is formed on the substrate by the multilayer wiring substrate technology in another process. There is a problem that the process is divided in the middle and efficiency is lowered and it is difficult to reduce the overall lead time. Further, in the conventional semiconductor packaging technology, the entire operation inspection and function inspection are performed after the semiconductor package is manufactured, but there is a problem that the yield is greatly reduced due to accumulation of defects in each process.

  Therefore, the present invention provides a semiconductor package manufacturing method for manufacturing a high-precision semiconductor package that achieves high functions and multi-functions by miniaturization, thinning, and high-density mounting in order to reduce costs by improving manufacturing efficiency and yield. The purpose is to provide.

  A semiconductor package manufacturing method according to the present invention that achieves the above-described object includes a device substrate body manufacturing process for manufacturing a device substrate body, a rewiring layer substrate body manufacturing process for manufacturing a rewiring layer substrate body in a separate process, and a rewiring process. A semiconductor package having a layer substrate body integration step, a dummy substrate peeling step, and an external connection bump formation step, wherein a rewiring layer is formed on the device and an external connection bump is provided on the uppermost layer of the rewiring layer Manufacturing. In the semiconductor package manufacturing method, the device substrate body manufacturing step includes an adhesive layer forming step of covering the device formed on the semiconductor substrate and forming an adhesive layer on the main surface of the semiconductor substrate. In the semiconductor package manufacturing method, the adhesive layer forming step of the device substrate manufacturing process forms an adhesive layer using a photosensitive or non-photosensitive insulating resin, or an insulating film material is joined to form the adhesive layer. In the semiconductor package manufacturing method, if necessary, an opening patterning step for forming an opening that allows the device electrode to face outward is performed on the adhesive layer in the device manufacturing process. The adhesive layer has a function of bonding the semiconductor substrate and the rewiring layer, and also functions as a device sealing layer.

  In the semiconductor package manufacturing method, the rewiring layer substrate body manufacturing step uses a dummy substrate having light transmission characteristics such as a glass substrate or a quartz substrate, and a release layer forming step of forming a release layer on the main surface of the dummy substrate; An insulating resin layer forming step for forming an insulating resin layer on the release layer; a wiring pattern forming step for forming a predetermined wiring pattern on the insulating resin layer; and a device connection bump opposite to the device electrode on the uppermost wiring pattern A rewiring layer substrate body having a rewiring layer of the device is manufactured. In the semiconductor package manufacturing method, in the rewiring layer substrate body manufacturing process, since the dummy substrate has a flat main surface, the thin multilayer wiring layer having a high-density and fine wiring pattern on the main surface of the dummy substrate is used. A rewiring layer is formed.

  In the semiconductor package manufacturing method, the peeling layer forming step of the rewiring layer substrate body manufacturing step is performed on the main surface of the dummy substrate, for example, thermoplastic resin such as epoxy resin, polyimide resin, phenol resin, benzocyclobutene resin, or thermosetting. A release layer having a thickness of about several μ and flatness is formed into a thin film using a functional resin. In the semiconductor package manufacturing method, in the device connection bump forming step of the rewiring layer substrate body manufacturing step, a ball bump provided by the ball bonding method or a plating bump formed by the plating method is provided on the wiring pattern.

  In the semiconductor package manufacturing method, the rewiring layer substrate body manufacturing process provides a thin film passive element such as a thin film capacitor element, a thin film inductor element or a thin film resistor element, or a functional element combining these thin film passive elements in the wiring layer. In the semiconductor package manufacturing method, in a subsequent step of the peeling layer forming step, a metal thin film layer that protects the rewiring layer in the peeling step is formed as a thin film on the peeling layer as necessary. In the semiconductor package manufacturing method, the metal thin film layer is formed, for example, on the entire surface of the release layer by sputtering or vapor deposition of titanium or aluminum.

  In the semiconductor package manufacturing method, the rewiring layer substrate body integrating step positions the rewiring layer substrate body with respect to the device substrate body by positioning opposing electrodes and connection bumps and integrating them through an adhesive layer. A rewiring layer is formed by coating the device. In the semiconductor package manufacturing method, in the rewiring layer substrate body integration step, the dummy substrate on which the rewiring layer is formed is positioned and combined with the device substrate body, for example, by applying pressure while heating through the adhesive layer. The device substrate body and the rewiring layer substrate body are integrated. In the semiconductor package manufacturing method, the device connection bumps on the rewiring layer side are connected to the device electrodes, and the device and the rewiring layer are connected.

  In the semiconductor package manufacturing method, in the dummy substrate peeling step, a laser beam is irradiated from the dummy substrate side, the peeling layer is heated by the laser light transmitted through the dummy substrate, and the dummy substrate is rewired at the interface with the peeling layer. To be peeled off. In the semiconductor package manufacturing method, the laser beam emitted from the laser device is transmitted through the dummy substrate and absorbed by the release layer, and the release layer is heated. In the semiconductor package manufacturing method, the peeling layer is peeled off from the dummy substrate due to a large difference in linear expansion coefficient from the dummy substrate, so that the dummy substrate is peeled off while leaving the rewiring layer on the device substrate body side. In the semiconductor package manufacturing method, the metal thin film layer formed as necessary shields the laser beam, thereby preventing the rewiring layer from being damaged by the laser beam. In the semiconductor package manufacturing method, the metal thin film layer can be made unnecessary by controlling the thickness of the release layer and the power of the laser beam. In the semiconductor package manufacturing method, the peeling layer remaining on the rewiring layer is removed by a dry etching method or the like as necessary, and the metal thin film layer is removed by a wet etching method or the like.

  In the semiconductor package manufacturing method, the external connection bump forming step forms the external connection bumps on the first layer wiring pattern of the rewiring layer from which the dummy substrate is peeled off. In the semiconductor package manufacturing method, the external connection bump forming step is performed by, for example, opening a necessary portion of the first layer wiring pattern and forming a resist layer with a solder resist, and then forming the resist layer by a printing method such as solder or solder ball bonding. External connection bumps for directly mounting a semiconductor package on a control board or the like mounted on an electronic device or the like are formed in the opening portion.

  In the semiconductor package manufacturing method, a large number of devices are formed on a semiconductor substrate in a device substrate body manufacturing process, and a large number of rewiring layers respectively opposed to each device are formed in a rewiring layer substrate body manufacturing process. . In the semiconductor package manufacturing method, the individual semiconductor packages having one or a plurality of devices and wiring layers are separated by a dicing process performed after the external connection bump forming process.

  According to the semiconductor package manufacturing method according to the present invention having the steps described above, the device substrate body manufacturing step and the rewiring layer substrate body manufacturing step are performed in separate steps, and the rewiring layer substrate body integration step is performed on the device substrate body. After the device is covered and the rewiring layer substrate body is integrated, the dummy substrate is peeled off by a dummy substrate peeling step to manufacture a semiconductor package. According to the semiconductor package manufacturing method, the semiconductor device is intended to reduce the cost by shortening the lead time and improving the yield by integrating the device substrate body and the rewiring layer substrate body on which the device and the rewiring layer are formed. A package can be formed. According to the semiconductor package manufacturing method, a precise and high-density redistribution layer is formed on a dummy substrate, thereby forming a semiconductor package with high functionality and multi-function by miniaturization / thinning and high-density mounting. Is possible. According to the semiconductor package manufacturing method, the dummy substrate is peeled off using the peeling layer as an interface by transmitting the light-transmitting dummy substrate and irradiating the peeling layer with laser light. As a result, damage to the rewiring layer and the device is prevented.

  Hereinafter, a method of manufacturing the semiconductor package 1 shown in the drawings as an embodiment of the present invention will be described. As shown in FIG. 1, the manufacturing method of the semiconductor package 1 is a device substrate body 2 in which a large number of devices 4 are formed on a semiconductor substrate 3 by a device substrate body manufacturing step A described in detail later. The rewiring layer substrate body 5 in which the rewiring layer 7 corresponding to each device 4 is formed on the dummy substrate 6 by the rewiring layer substrate body forming step B is manufactured. In the manufacturing method of the semiconductor package 1, after the device substrate body 2 and the rewiring layer substrate body 5 are integrated to manufacture the intermediate body 8, the intermediate body 8 is subjected to a dummy substrate peeling process by laser processing. The substrate 6 is peeled off to manufacture the semiconductor package 1 shown in FIG. The semiconductor package 1 is manufactured by subjecting the semiconductor package 1 to a dicing process as necessary to manufacture the individual semiconductor package 9 shown in FIG.

  In the semiconductor package 1, an adhesive layer 11 is formed so as to cover a large number of devices 4 and electrodes 10 formed on the main surface of the semiconductor substrate 3 as shown in FIG. The wiring layer 7 is integrated in a laminated state. In the semiconductor package 1, the rewiring layer 7 includes two insulating resin layers 12 of a first insulating resin layer 12A and a second insulating resin layer 12B, and first wiring patterns 13A to third wiring, as will be described in detail later. The wiring pattern 13 is composed of a pattern 13C and a three-layer wiring pattern 13. The vias 14A and 14B (via 14) appropriately formed in the insulating resin layer 12 connect the wiring patterns 13 of each layer to each other.

  In the semiconductor package 1, openings 15 are patterned in the adhesive layer 11 corresponding to the electrodes 10 of the device 4, and device connection bumps 16 formed on the rewiring layer 7 side are filled in the openings 15, respectively. In the semiconductor package 1, each device connection bump 16 is provided on a device connection electrode 17 formed on the third wiring pattern 13 </ b> C on the rewiring layer 7 side, and each of the devices 4 facing each other through the device connection bump 16. The electrode 10 and each device connection electrode 17 on the rewiring layer 7 side are connected.

  The device connection bumps 16 are formed by, for example, Sn-Au bonding, solder bonding, or metal-metal bonding such as Cu-Cu bonding or Au-Cu bonding by smoothing the surface. Be joined. In this case, the semiconductor package 1 is subjected to an appropriate electrode film forming process on the surface of each electrode 10.

  The semiconductor package 1 covers the first wiring pattern 13A on the rewiring layer 7 side, which is the uppermost layer, and a resist layer 18 is formed over the entire surface, and the first wiring pattern 13A is formed on the resist layer 18. An opening 20 is formed so that the external connection electrode 19 faces outward. The semiconductor package 1 has external connection bumps 21 formed in the respective openings 20 and is directly mounted on a mother board, an interposer or the like mounted on an electronic device via the external connection bumps 21 by a flip chip mounting method or the like. .

  In the semiconductor package 1 configured as described above, the device substrate body 2 is manufactured by the device substrate body manufacturing process A as described above. In the device substrate manufacturing process A, a semiconductor substrate (wafer) 3 is supplied. As shown in FIG. 1, a device forming process A-1, an adhesive layer forming process A-2, and an opening patterning are applied to the semiconductor substrate 3. The device substrate body 2 is manufactured by performing step A-3 and the like. In the device substrate manufacturing process A, a predetermined continuity inspection process A-4 is performed on the manufactured device substrate 2 and only the device substrate 2 determined to be non-defective is supplied to the next process. The device formation process A-1 is a process for manufacturing the device 4 by a conventionally well-known semiconductor technology. The device 4 and the electrode 10 having a predetermined function are formed on the main surface of the semiconductor substrate 3.

  In the adhesive layer forming step A-2, the device substrate intermediate shown in FIG. 4 is formed by covering the device 4 and the electrode 10 on the main surface of the semiconductor substrate 3 to form the adhesive layer 11 over the entire surface. 22 is made. The adhesive layer 11 functions as a function of integrally bonding the rewiring layer substrate body 5 to the device substrate body 2 and a sealing layer for the device 4 and the electrode 10 as will be described later. The adhesive layer 11 is formed by a method such as film formation using a thermosetting adhesive insulating resin or bonding of an adhesive insulating film, for example. In the adhesive layer forming step A-2, for example, when an adhesive insulating resin is used, the adhesive layer 11 having a uniform thickness is formed by a spin coat method, a laminate method, or the like.

  In the opening patterning step A-3, the device substrate body 2 shown in FIG. 5 is manufactured by forming the openings 15 that allow the electrodes 10 of the device 4 to face the adhesive layer 11 outward. In the opening patterning step A-3, when the adhesive layer 11 is formed using a photosensitive adhesive insulating resin or adhesive insulating film, the opening 15 is patterned by a known lithography technique. In the opening patterning step A-3, when the adhesive layer 11 is formed using a non-photosensitive adhesive insulating resin or adhesive insulating film, the opening 15 is patterned by a known dry etching technique such as a plasma etching method. Form.

  The opening patterning step A-3 eliminates the need for the opening 15 in the rewiring layer substrate body integration step C-1 in which the device substrate body 2 and the rewiring layer substrate body 5 are integrated as will be described later. Needless to say, this is not implemented when the device connection bumps 16 formed on the rewiring layer substrate body 5 break through the adhesive layer 11 to be connected to the electrode 10.

  In the manufacturing process of the semiconductor package 1, the rewiring layer substrate body 5 is manufactured by the rewiring layer substrate body manufacturing process B which is a separate process from the device substrate body manufacturing process A described above. In the redistribution layer substrate body manufacturing process B, a dummy substrate 6 is supplied. As shown in FIG. 1, a peeling layer forming process B-1 and a metal thin film layer forming process B-2 are performed on the dummy substrate 6. The rewiring layer substrate body 5 shown in FIG. 9 is obtained through the insulating resin layer forming step B-3, the wiring pattern forming step B-4, the via forming step B-5, the device connection bump forming step B-6, and the like. To manufacture.

  In the rewiring layer substrate body manufacturing process B, only the rewiring layer substrate body 5 determined to be non-defective by performing a predetermined continuity inspection process B-7 on the manufactured rewiring layer substrate body 5 is supplied to the next process. . In the manufacturing process of the semiconductor package 1, a non-defective device substrate body 2 manufactured by a separate device substrate body manufacturing process A and a non-defective rewiring layer substrate body 5 manufactured by a rewiring layer substrate body manufacturing process B are integrated. Therefore, it is possible to form a semiconductor package that is reduced in cost by improving yield.

  In the rewiring layer substrate body manufacturing process B, it is possible to form the rewiring layer 7 with high accuracy by having the main surface flattened with relatively high accuracy as the dummy substrate 6, and will be described later. In the dummy substrate peeling step C-2, a substrate having high light transmission characteristics, such as a glass substrate or a quartz substrate, which can efficiently transmit the laser beam R emitted from the laser device 23 is used. As described later, the dummy substrate 6 is separated from the rewiring layer substrate body 5 after the rewiring layer substrate body 5 is integrated with the device substrate body 2 by the rewiring layer substrate body integrating step C-1. Although it is peeled off, it is reused by performing a cleaning process or the like.

  In the release layer forming step B-1, as shown in FIG. 6, a release layer 24 having a thickness and flatness of about several microns is formed on the entire main surface of the dummy substrate 6 by spin coating or the like. Form over. The release layer 24 is formed into a thin film with a thermoplastic resin such as an epoxy resin, a polyimide resin, a phenol resin, a benzocyclobutene resin, or a thermosetting resin that has a linear expansion coefficient that is greatly different from that of the dummy substrate 6. The peeling layer 24 functions as a peeling sacrificial layer in a dummy substrate peeling step C-2 described later, and remains on the rewiring layer 7 but is removed by a dry etching method or the like.

  In the metal thin film layer forming step B-2, as shown in FIG. 7, the metal thin film layer 25 is formed over the entire surface of the release layer 24 described above by, for example, sputtering or vapor deposition. The metal thin film layer 25 is formed of, for example, a titanium layer or an aluminum layer. The rewiring layer 7 is formed as an upper layer by blocking the laser light R irradiated from the dummy substrate 6 side in a dummy substrate peeling process C-2 described later. Functions as a barrier metal to prevent damage. The metal thin film layer 25 can be made unnecessary by controlling the thickness of the release layer 24 and the power of the laser beam R, for example. The metal thin film layer 25 is removed by a wet etching method or the like after the peeling layer 24 is removed from the rewiring layer 7 after a dummy substrate peeling step C-2 described later.

  The rewiring layer substrate body manufacturing process B includes an insulating resin layer forming process B-3, a wiring pattern forming process B-4, and via formation on the metal thin film layer 25 (or release layer 24) by a general multilayer wiring technique. The rewiring layer 7 is formed by the process B-5. As described above, the rewiring layer substrate body manufacturing process B includes a thin multilayer wiring layer having high density and fine wiring patterns 13 by using the dummy substrate 6 having a flat main surface as a substrate, and has a high accuracy. It is possible to form the rewiring layer 7 in which the thin film passive element is formed.

  In the rewiring layer substrate body manufacturing process B, a predetermined pattern is formed by a copper plating wiring technique in which a plating resist layer is patterned on the metal thin film layer 25 in the first wiring pattern forming process B-4-1 and then copper plating is performed. A first wiring pattern 13A is formed. As will be described later, the first wiring pattern 13A constitutes the uppermost layer of the rewiring layer 7 by peeling off the dummy substrate 6, and the external connection electrode 19 is formed together with the wiring pattern.

  In the rewiring layer substrate body manufacturing process B, in the first insulating resin layer forming process B-3-1, the same insulating resin as that of the release layer 24 described above, for example, epoxy resin, polyimide resin, phenol resin, benzocyclobutene The first insulating resin layer 12A is formed on the metal thin film layer 25 on which the first wiring pattern 13A is formed using a thermoplastic resin such as a resin or a thermosetting resin. In the rewiring layer substrate body manufacturing process B, a via hole is formed at a predetermined position of the first insulating resin layer 12A by a first via forming process B-5-1 by a wet etching process by lithography technology or a dry etching process such as plasma etching. At the same time, the first via 14A is formed by forming a via hole lid and conducting the internal conductivity.

  The rewiring layer substrate body manufacturing process B is predetermined by a copper plating wiring technique in which a plating resist layer is patterned on the first insulating resin layer 12A in the second wiring pattern forming process B-4-2 and then copper plating is performed. A second wiring pattern 13B of the pattern is formed. In the second wiring pattern forming step B-4-2, the second wiring pattern 13B and the first wiring pattern 13A are made conductive by forming a copper plating layer also on the first via 14A. . Although details are omitted, a thin film passive element such as a thin film capacitor, a thin film resistor, or a thin film inductor is formed in the second wiring pattern 13B.

  In the rewiring layer substrate body manufacturing process B, the second insulating resin layer 12B is formed by covering the second wiring pattern 13B in the second insulating resin layer forming process B-3-2. In the rewiring layer substrate body manufacturing process B, a via hole is formed at a predetermined position of the second insulating resin layer 12B by the second via forming process B-5-2, and the via hole is formed by a lid and an internal conductive process. To form the second via 14B. The rewiring layer substrate body manufacturing process B is predetermined by a copper plating wiring technique in which a plating resist layer is patterned on the second insulating resin layer 12B in the third wiring pattern forming process B-4-3 and then copper plating is performed. A third wiring pattern 13C of the pattern is formed. In the third wiring pattern formation step B-4-3, the third wiring pattern 13C and the second wiring pattern 13B are made conductive by forming a copper plating layer also on the second via 14B described above. .

  In the rewiring layer substrate body manufacturing process B, the insulating resin layer forming process B-3, the wiring pattern forming process B-4, and the via forming process B-5 described above are repeated as necessary to perform dummy processing as shown in FIG. A multilayer rewiring layer 7 is formed on the substrate 6 with a release layer 24 interposed therebetween. A device connection electrode 17 is formed on the third wiring pattern 13C constituting the uppermost layer of the rewiring layer 7 together with the wiring pattern.

  In the rewiring layer substrate body manufacturing process B, device connection bumps 16 are formed on the device connection electrodes 17 formed in the third wiring pattern 13C of the rewiring layer 7 by the device connection bump forming process B-6. The rewiring layer substrate body 5 shown in 9 is manufactured. In the device connection bump forming process B-6, for example, the device connection bumps 16 are integrally provided on the device connection electrodes 17 by a ball bonding method, a stud (ball) bump bonding method, or a plating method. In addition, the device connection bump 16 is formed by using a solder plating bump when the opening 15 is formed in the adhesive layer 11 on the device substrate body 2 side as described above. The alloy is connected to the electrode 10 at -1. In the rewiring layer substrate body manufacturing step B, the rewiring layer substrate body 5 manufactured as described above is subjected to a predetermined continuity inspection step B-7, thereby determining the non-defective product. Only the substrate body 5 is supplied to the next process.

  In the manufacturing process of the semiconductor package 1, the device substrate body 2 manufactured by the device substrate body manufacturing process A and the rewiring layer substrate body 5 manufactured by the rewiring layer substrate body manufacturing process B are integrated with the rewiring layer substrate body. The intermediate body 8 shown in FIG. 11 is manufactured by integration in the step C-1. Furthermore, the manufacturing process of the semiconductor package 1 includes a dummy substrate peeling step C-2 for peeling the dummy substrate 6 from the intermediate body 8, and a peeling layer / metal thin film layer removing step C for removing the peeling layer 11 and the metal thin film layer 25. -3 and the external connection bump forming step C-4 for forming the external connection bump 21 and the like, the semiconductor package 1 is manufactured. In the manufacturing process of the semiconductor package 1, the individual semiconductor package 9 is manufactured by performing the dicing process C-5 on the semiconductor package 1 as necessary.

  In the rewiring layer substrate body integration step C-1, an appropriate positioning mechanism is used with the device substrate body 2 and the rewiring layer substrate body 5 as shown in FIG. Align and combine to integrate. The rewiring layer substrate body integration step C-1 is performed by applying pressure while heating under predetermined conditions in a state where the device substrate body 2 and the rewiring layer substrate body 5 are combined. 3 and the dummy substrate 6 are integrated to produce an intermediate body 8. The rewiring layer substrate body integration step C-1 is easy to handle and precise because the device substrate body 2 and the rewiring layer substrate body 5 have the semiconductor substrate 3 and the dummy substrate 6 having mechanical rigidity. Positioning is also possible.

  In the rewiring layer substrate body integration step C-1, as described above, the adhesive layer 11 is formed using a photosensitive adhesive resin, and the electrode 10 of the device 4 faces the adhesive layer 11 outward. Device connection bumps 16 facing each opening 15 are fitted to the device substrate body 2 on which the circuit board 15 is formed, and the rewiring layer substrate body 5 is combined. In the rewiring layer substrate body integration step C-1, for example, when the device connection bumps 16 are formed by solder plating bumps, the semiconductor substrate 3 and the dummy substrate 6 are pressurized while being heated to a temperature equal to or higher than the melting temperature of the solder. As a result, the opposing electrode 10 and the device connection bump 16 are solder-connected, and the device 4 and the rewiring layer 7 are electrically connected.

  In the rewiring layer substrate body integration step C-1, when the adhesive layer 11 is formed using a non-photosensitive adhesive resin, the device connection bumps 16 break through the adhesive layer 11 softened by heating, and the electrodes By reaching 10 and joining it, the device 4 and the redistribution layer 7 are electrically connected.

  In the dummy substrate peeling step C-2, as shown in FIG. 12, the intermediate body 8 described above is irradiated with laser light R emitted from the laser device 23 from the dummy substrate 6 side at the interface with the peeling layer 24. The dummy substrate 6 is peeled off. In the dummy substrate peeling step C-2, for example, the excimer laser device 23 is used to control and irradiate the laser light R having a wavelength of 248 nm so as to be condensed on the peeling layer 24 with a spot diameter of 150 μm × 2000 μm. In the dummy substrate peeling step C-2, in this case, the laser beam R is optimized in a power ratio range of 0.53 to 1.0, and irradiation is performed over the entire area of the dummy substrate 6.

  As described above, the intermediate body 8 is formed by forming the dummy substrate 6 with a glass substrate or a quartz substrate having good light transmission, so that the laser beam R transmitted through the dummy substrate 6 is efficiently applied to the peeling layer 24. Absorption is performed and the release layer 24 is heated. Since the intermediate body 8 has a large difference in linear expansion coefficient between the dummy substrate 6 and the release layer 24, the phenomenon that the heated release layer 24 is peeled off from the main surface of the dummy substrate 6 occurs. Is left on the device substrate body 2 side, and the dummy substrate 6 is separated.

  As described above, in the intermediate body 8, the rewiring layer substrate body 5 forms the multilayer rewiring layer 7 on the main surface of the dummy substrate 6 via the peeling layer 24 and the metal thin film layer 25. Therefore, in the intermediate 8, the metal thin film layer 25 shields the laser beam R irradiated from the dummy substrate 6 side so as not to affect the redistribution layer 7. Damage is prevented from occurring, and only the dummy substrate 6 is peeled cleanly from the rewiring layer 7 with the peeling layer 24 as an interface.

  The peeling layer / metal thin film layer removing step C-3 is shown in FIG. 13 by removing the peeling layer 24 remaining on the surface of the rewiring layer 7 and the metal thin film layer 25 when the dummy substrate 6 is peeled off. Thus, the first wiring pattern 13A of the rewiring layer 7 is exposed over the entire surface. In the peeling layer / metal thin film layer removing step C-3, the peeling layer 24 is removed from the surface of the rewiring layer 7 by a dry etching method such as plasma etching or ion etching. In the peeling layer / metal thin film layer removing step C-3, the metal thin film layer 25 exposed by further removing the peeling layer 24 is removed by, for example, a wet etching method.

  In the external connection bump forming step C-4, the external connection bump 21 is formed on the device connection electrode 17 formed on the first wiring pattern 13A constituting the surface layer of the rewiring layer 7. In the external connection bump forming step C-4, a resist layer that electrically and mechanically protects the rewiring layer 7 by applying, for example, a solder resist over the entire surface of the rewiring layer 7 as a previous step. 18 is formed.

  In the external connection bump formation step C-4, the resist layer 18 is subjected to an opening formation patterning process to form openings that allow the device connection electrodes 17 to face outward. In the external connection bump forming step C-4, the external connection bump 21 made of solder or the like is formed on the device connection electrode 17 through the openings on the device connection electrode 17 by, for example, a printing method or a ball mounting method. The package 1 is manufactured.

  In the manufacturing method of the semiconductor package 1, the device substrate body 2 and the rewiring layer substrate body 5 are manufactured using the semiconductor substrate 3 and the dummy substrate 6 as described above. In the manufacturing method of the semiconductor package 1, a plurality of semiconductor packages 1 can be simultaneously formed on the semiconductor substrate 3 and the dummy substrate 6, and the semiconductor package 1 is individually subjected to a dicing process C-5. Cutting is performed for each semiconductor package 9. In the dicing process C-5, the semiconductor package 1 is cut using a dicing apparatus having a diamond cutter used in a conventional semiconductor manufacturing process to obtain the individual semiconductor package 9 shown in FIG.

  The present invention is not limited to the above-described embodiment, and after the device substrate body in which the device is formed and the rewiring layer substrate body in which the rewiring layer is formed are integrated, the dummy substrate is transmitted therethrough. What is necessary is just to have the basic process of irradiating the peeling layer with laser light and peeling the dummy substrate from the rewiring layer substrate body side. In the semiconductor package 30 shown in FIG. 14 as the second embodiment, a thin film resistor element 32, a thin film inductor element 33, or a thin film capacitor element 34 is formed in the rewiring layer 31, and these thin film elements are combined as appropriate. An LC filter function or the like is mounted on the wiring layer 31. Since the semiconductor package 30 has the same basic configuration as that of the semiconductor package 1 described above, the corresponding parts are denoted by the same reference numerals and detailed description thereof is omitted.

  In the manufacturing process of the semiconductor package 30, for example, a thin film resistor element forming portion of the second wiring pattern 13B is formed by using a resistor element forming material such as tantalum nitride, tantalum, chromium, or nickel chromium. The thin film resistor element 32 is formed by forming a pattern in a desired shape by a thin film forming technique such as a lithographic method. In the manufacturing process of the semiconductor package 30, when the second wiring pattern 13B is formed, the thin film inductor element 33 is formed by forming, for example, a helical copper pattern in a part thereof. In the manufacturing process of the semiconductor package 30, for example, the thin film capacitor element 34 may be formed by forming a dielectric between the electrode of the second wiring pattern 13B and the electrode of the third wiring pattern 13C facing the electrode, The metal film is formed by a method such as anodizing the metal film.

It is a manufacturing process figure of the semiconductor package shown as embodiment. It is sectional drawing of a semiconductor package. It is sectional drawing of an individual semiconductor package. It is explanatory drawing of a device board | substrate body manufacturing process, and is the figure which formed the adhesive layer in the semiconductor substrate. It is the figure which formed the opening part in the contact bonding layer. It is explanatory drawing of a rewiring layer board | substrate body manufacturing process, and is the figure which formed the peeling layer in the dummy board | substrate. It is the figure which formed the metal thin film layer. It is the figure which formed the same rewiring layer. It is the figure which formed the device connection bump. It is explanatory drawing of the process of aligning and combining a device substrate body and a rewiring layer substrate body. It is explanatory drawing of the process of heating and pressurizing and integrating the device substrate body and the rewiring layer substrate body. It is explanatory drawing of the process of irradiating a laser beam from the dummy substrate side. The intermediate body is obtained by removing the dummy substrate, the release layer, and the metal thin film layer. It is sectional drawing of the semiconductor package shown as 2nd Embodiment.

Explanation of symbols

  1 semiconductor package, 2 device substrate body, 3 semiconductor substrate, 4 device, 5 rewiring layer substrate body, 6 dummy substrate, 7 rewiring layer, 9 individual semiconductor package, 10 electrode, 11 adhesive layer, 12 insulating resin layer, 13 Wiring pattern, 15 openings, 16 device connection bumps, 17 device connection electrodes, 18 resist layer, 19 external connection electrodes, 20 openings, 21 external connection bumps, 23 laser device, 24 release layer, 25 metal layer 30 semiconductor package

Claims (4)

A device substrate body manufacturing process for manufacturing a device substrate body having an adhesive layer forming step of covering the device formed on the semiconductor substrate and forming an adhesive layer on the main surface of the semiconductor substrate;
Using a dummy substrate having light transmission characteristics, a peeling layer forming step of forming a peeling layer on the main surface of the dummy substrate, an insulating resin layer forming step of forming an insulating resin layer on the peeling layer, and the insulating resin A wiring pattern forming step for forming a predetermined wiring pattern on the layer; and a device connection bump forming step for forming a device connection bump opposite to the device electrode on the uppermost wiring pattern. Rewiring layer substrate body manufacturing process to form,
The rewiring layer substrate body is positioned with respect to the device substrate body by positioning the opposing electrodes and the connection bumps and integrated via the adhesive layer, thereby covering the device and rewiring layer. Rewiring layer substrate body integration process for producing an intermediate body laminated,
By irradiating the intermediate body with laser light from the dummy substrate side, the release layer is heated by the laser light transmitted through the dummy substrate, and the dummy substrate is attached to the rewiring layer at the interface with the release layer. A dummy substrate peeling step to peel off from,
An external connection bump forming step of forming an external connection bump on the first layer wiring pattern of the rewiring layer from which the dummy substrate has been peeled off,
A method of manufacturing a semiconductor package, comprising: manufacturing a semiconductor package in which the rewiring layer is stacked on the device and the external connection bumps are provided. Forming a large number of devices on the semiconductor substrate in the device substrate manufacturing process, and forming a number of rewiring layers respectively opposed to the devices in the rewiring layer substrate manufacturing process;
2. The semiconductor according to claim 1, wherein the individual semiconductor package having one or a plurality of devices and wiring layers is separated by a dicing process performed after the external connection bump forming process. Package manufacturing method.   In the rewiring layer substrate body manufacturing process, a glass substrate or a quartz substrate having a flat main surface is used as the dummy substrate, and the rewiring layer provided with thin film passive elements and functional elements is formed by a semiconductor technology. The method of manufacturing a semiconductor package according to claim 1.   The rewiring layer substrate body manufacturing step forms a thin film of the release layer on the main surface of the dummy substrate in the release layer formation step by using a resin material, and the release layer in a subsequent step of the release layer formation step. 4. The semiconductor package manufacturing method according to claim 3, wherein a metal thin film layer for protecting the rewiring layer is formed thereon.

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