JP2007228514A - Imaging apparatus and method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an imaging apparatus wherein a degree of freedom of detection for various adjustments is improved and the scale and the manufacturing cost of a signal processing circuit are suppressed. <P>SOLUTION: RAW data compressed by each block are read from an SDRAM 14 in the unit of the block, and a RAW expansion section 32 expands the data. The RAW data for an ordinary detection system are supplied to any of detectors 221 to 225 and the RAW data for a multi-detection system are supplied to a detector 230. The detector 230 detects prescribed information on the basis of input image data in each of a plurality of detection frames established on an image as a plurality of rectangular regions of the same size respectively at least in a horizontal direction, and since the single detector 230 sequentially receives image data at a position corresponding to an optional detection frame and can execute the detection from the detection frame, it is not required to prepare one detector for each detection frame. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an image pickup apparatus and method for picking up an image using a solid-state image pickup device, and in particular, an image pickup apparatus configured to temporarily store an image signal obtained by image pickup in a memory and process the image signal, and an image pickup method in the image pickup apparatus About.

  In recent years, imaging apparatuses capable of capturing an image using a solid-state imaging device and storing the captured image as digital data, such as a digital still camera and a digital video camera, have become widespread. In such an image pickup apparatus, the number of pixels of the image pickup element is increased and the function and performance of the apparatus are improved. In particular, as the number of pixels of the image sensor increases, the processing load of the image pickup signal increases. However, even such an image pickup apparatus is required to be able to process at high speed so that there is no stress in operation.

FIG. 11 is a block diagram illustrating a configuration example of a conventional imaging device.
11 includes an image sensor 81, an analog front end (AFE) circuit 82, a digital image processing circuit 83, an SDRAM (Synchronous Dynamic Random Access Memory) 84, a ROM (Read Only Memory) 85, and a storage device. 86. The digital image processing circuit 83 includes a camera signal preprocessing unit 91, a detection unit 92, a camera signal processing unit 93, a resolution conversion unit 94, a JPEG (Joint Photographic Experts Group) engine 95, a CPU (Central Processing Unit) 96, a video. An output encoder 97 and an SDRAM controller 98 are provided and are connected to each other via an internal bus 99.

  In such an image pickup apparatus, an image pickup signal from the image pickup element 81 is sequentially supplied to the AFE circuit 82, subjected to CDS (Correlated Double Sampling) processing and AGC (Auto Gain Control) processing, and then converted into a digital signal. And supplied to the digital image processing circuit 83. The camera signal preprocessing unit 91 performs defective pixel correction, shading correction, and the like on the input image signal, and writes the raw image data to the SDRAM 84 through the SDRAM controller 98 as raw data.

The detection unit 92 reads the raw data from the SDRAM 84 via the SDRAM controller 98 and performs various detection processes such as luminance information.
The camera signal processing unit 93 reads out the RAW data from the SDRAM 84 via the SDRAM controller 98, and executes various image quality correction processes on the read RAW data according to the control of the CPU 96 based on the detection result by the detection unit 92. The luminance signal (Y) and the color difference signals (R−Y, B−Y) are converted and output. The resolution conversion unit 94 performs resolution conversion processing on the output image data from the camera signal processing unit 93 as necessary.

  The video output encoder 97 converts the image data converted to a resolution suitable for display by the resolution converter 94 into an image signal for monitor display, and outputs it to a monitor (not shown) or a video output terminal 97a. Thereby, a camera through image can be displayed. The JPEG engine 95 compresses and encodes the image data from the camera signal processing unit 93 or the resolution conversion unit 94 in accordance with the JPEG standard, and temporarily stores it in the SDRAM 84. The CPU 96 records the JPEG encoded data stored in the SDRAM 84 in the storage device 86.

The CPU 96 controls the overall processing of the image pickup apparatus, and the ROM 85 stores programs executed by the CPU 96 and data necessary for the processing.
By the way, in the conventional general imaging apparatus as described above, the RAW data obtained from the imaging device is temporarily stored in an image memory such as an SDRAM, and then read and subjected to image quality correction processing and the like. For example, in the case of an apparatus of a type that captures one frame in a plurality of fields, such as when using an interlaced readout type image sensor, data of each field may be stored in a memory and then frame data may be generated. It is essential. Further, in order to suppress the size of the line memory of the camera signal processing unit, the entire screen is partially (for example, vertically) using only a delay line that is a fraction of the length of 1H (horizontal synchronization period). Even in the case of a processing system that performs processing (in the form of several strips in the direction), it is necessary to store the data of the entire screen in the memory at least before the processing.

  Here, when writing and reading RAW data to / from the memory, data for the entire screen flows on the internal bus, so the bus bandwidth necessary for this transmission occupies most of the entire bus bandwidth during imaging. . In particular, as the number of pixels of the image sensor increases and the capacity of RAW data increases, the load of data transfer increases and the time required for memory writing / reading also increases. Therefore, if the time required for the recording process is to be shortened, it is necessary to increase the bus band by increasing the transmission frequency, and there is a problem that the apparatus cost increases. There is also a problem that the larger the number of pixels, the larger the capacity of the memory for storing the RAW data.

  On the other hand, it is considered that the RAW data is compressed and transmitted during transmission of the internal bus. However, if the variable length coding method is used as this compression method, the bus bandwidth necessary for transmission cannot be made constant. There are also problems such as complicated processing and the inability to constantly obtain the effect of reducing the bus bandwidth.

  As a conventional imaging device having a function of compressing RAW data, for example, it has a function of compressing and recording RAW data by a reversible compression method using a Huffman table, and the Huffman table is stored for each color channel. Some have been optimized (for example, see Patent Document 1). In addition, when the RAW compression mode for compressing and recording the RAW data is set, the RAW data interpolation processing unit used in the normal compression mode is bypassed (for example, see Patent Document 2). . However, Patent Document 1 described above compresses RAW data using a variable-length encoding method, and both Patent Documents 1 and 2 compress RAW data in order to reduce the bandwidth of the internal bus. is not.

  In the conventional imaging apparatus as shown in FIG. 11, the RAW data once stored in the memory SDRAM 84 is read by the detection unit 92, and the detection unit 92 uses, for example, AF (Auto Focus), AE ( Signal detection for auto exposure and white balance control is performed. As this signal detection, there are a method for detecting data of the entire screen and a method for detecting by dividing one screen into a plurality of detection frames. In any of these methods, a general procedure is to sequentially read pixel data line by line from the upper left of the screen and input it to the detector.

  However, in the case where a plurality of detection frames are provided in the horizontal direction, in order to sequentially acquire and detect pixel data for each line in this way, the detection frame for the horizontal direction is matched with the input order of the pixel data. As many detectors as are required. For example, when each detector detects signals for a plurality of lines, detection is not completed for all the detectors in the horizontal direction until pixel data for the number of lines is input in the scanning order. Further, in each detector, it is necessary to hold data detected on the previous line until the detection for the number of lines is completed.

  Even when such a detection technique is employed, if the number of detection frame divisions is small, the number of detectors required is small, and the influence on the circuit scale and manufacturing cost is small. However, recent imaging devices are required to provide more detection frames to improve the accuracy of various adjustment functions and to enhance the functionality of imaging devices, as referred to as multi-photometry. If the number of detection frames increases in this way, the number of required detectors increases, and the scale of registers for holding detection data also increases, which increases the circuit scale and manufacturing cost. Become.

Furthermore, there is a demand for simultaneous detection using detection frames of different sizes for one screen, such as detection using both a relatively large detection frame and a detection frame that is more finely divided. In such a case, the number of detectors further increases, and it is necessary to read out RAW data for each detection method with different detection frames. This increases the transmission load of RAW data, and hinders processing speedup. become. In addition, among the finely divided detection frames, there is also a demand to perform various controls with higher accuracy using detection values from arbitrary detection frames. In this case as well, the transmission load and processing of RAW data are similarly performed. Increased time is a problem.
Japanese Patent Laid-Open No. 2004-40300 (paragraph numbers [0019] to [0028], FIG. 2) JP 2003-125209 A (paragraph numbers [0027] to [0037], FIG. 1)

  As described above, in the conventional imaging device, when detecting the RAW data read from the memory, if many detection frames obtained by dividing the screen are used to improve the accuracy of various adjustment functions, the corresponding amount is increased. As a result, the number of detectors increases and the circuit scale and manufacturing cost increase. In addition, as the number of pixels of the image sensor increases, the time required to read image data from the memory and the transmission load increase.

  The present invention has been made in view of the above points, an imaging apparatus having a high degree of freedom in detection for various adjustments, and a reduced scale and manufacturing cost of a signal processing circuit, and such an apparatus. An object is to provide an imaging method capable of realizing the above.

  In the present invention, in order to solve the above-described problems, in an imaging apparatus that captures an image using a solid-state imaging device, a memory that temporarily stores image data captured by the solid-state imaging device and digitally converted, and at least horizontal A single detection unit configured to detect predetermined information based on input image data in each of a plurality of detection frames set on the screen as rectangular regions of the same size, each set in a plurality of directions. There is provided an imaging apparatus comprising: a readout control unit that reads out image data held in a memory in a block unit including a predetermined number of adjacent pixels in a screen and supplies the unit to the single detection unit Is done.

  In such an imaging apparatus, image data captured by a solid-state imaging device and digitally converted is temporarily stored in a memory, and then read out in units of blocks each including a predetermined number of adjacent pixels in the screen. , Supplied to a single detector. A plurality of single detection units are set at least in the horizontal direction, and detect predetermined information based on input image data in each of a plurality of detection frames set on the screen as rectangular regions of the same size. Do.

  In addition, for example, a compression unit that compresses the digitally converted image data in units of blocks and supplies the compressed image data to the memory; and a decompression unit that decompresses the compressed image data read from the memory And another detection unit for detecting predetermined information based on input image data in a detection frame set on the screen as one or more rectangular areas larger than the detection frame of the single detection unit. The read control unit reads the compressed image data held in the memory in units of blocks, expands the data to the expansion unit, and selectively selects the single detection unit and the other detection units. You may make it supply.

  According to the imaging apparatus of the present invention, a plurality of predetermined information is set based on input image data in each of a plurality of detection frames set on the screen as a rectangular area of the same size, which is set at least in the horizontal direction. Only one detector for performing detection is provided, and image data read from the memory is supplied to the single detector in units of blocks each having a predetermined number of pixels. Thus, a single detector can sequentially receive image data at a position corresponding to an arbitrary detection frame and execute detection from the detection frame. For example, all detection frames parallel in the horizontal direction on the screen Even when detecting from a single detector, it is possible to detect with a single detector without preparing a detector corresponding to each detection frame. Therefore, it is possible to increase the degree of freedom of detection while suppressing the circuit scale and manufacturing cost of the detector.

  In addition, for example, the detection of predetermined information may be performed based on input image data in a detection frame set on the screen as one or more rectangular areas larger than the detection frame of the single detection unit. A detection unit is provided, and when the digitally converted image data is stored in the memory, the compressed image data is compressed and stored in units of blocks, the compressed image data is read out from the memory in units of blocks, and is expanded. You may make it selectively supply with respect to a detection part and another detection part. As a result, a single detection unit and other detection units that detect using different detection frames can be operated in parallel, and image data from the memory is read out as compressed image data. Time required and transmission load are suppressed. Therefore, it is possible to realize an image pickup apparatus that is high in speed and low in circuit scale and manufacturing cost while further increasing the degree of freedom of detection.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[First Embodiment]
FIG. 1 is a block diagram showing the configuration of the imaging apparatus according to the first embodiment of the present invention.

  The imaging apparatus shown in FIG. 1 includes an imaging element 11, an AFE circuit 12, a digital image processing circuit 13, an SDRAM 14, a ROM 15, and a storage device 16. The digital image processing circuit 13 includes a camera signal preprocessing unit 21, a detection unit 22, a camera signal processing unit 23, a resolution conversion unit 24, a JPEG engine 25, a CPU 26, a video output encoder 27, and an SDRAM controller 28. Are connected to each other by an internal bus 29. Further, in addition to such a conventional configuration, the digital image processing circuit 13 of this embodiment includes a RAW compression unit 31 and RAW expansion units 32 and 33.

  The imaging device 11 is a solid-state imaging device such as a CCD (Charge Coupled Devices) or CMOS (Complementary Metal Oxide Semiconductor) image sensor, and converts light incident from a subject through a lens block (not shown) into an electrical signal.

  The AFE circuit 12 samples and holds the image signal output from the image sensor 11 so as to maintain a good S / N (Signal / Noise) ratio by CDS processing, and further controls the gain by AGC processing. A / D (Analog / Digital) conversion is performed to output a digital image signal.

  The digital image processing circuit 13 is formed as, for example, a SoC (System On a Chip) circuit. In the digital image processing circuit 13, the camera signal pre-processing unit 21 performs a signal correction process for a defective pixel in the image sensor 11 and a shading process for correcting a peripheral light loss of the lens for the image signal supplied from the AFE circuit 12. The processed signal is output as RAW data.

  The RAW compression unit 31 compresses the RAW data from the camera signal preprocessing unit 21 by a compression method to be described later, and supplies the compressed RAW data to the SDRAM 14 via the SDRAM controller 28. As will be described later, the RAW compression unit 31 compresses the RAW data from the camera signal preprocessing unit 21 for each block with pixel data of a certain number of adjacent same color components as one block, and outputs compressed image data. To do.

  The RAW decompression units 32 and 33 decompress the compressed RAW data read from the SDRAM 14 via the SDRAM controller 28 for each block by a method described later, and output the decompressed data to the detection unit 22 and the camera signal processing unit 23, respectively. .

The detection unit 22 performs signal detection processing for AF, AE, white balance control, and the like from the RAW data from the RAW expansion unit 32.
The camera signal processing unit 23 performs demosaic processing on the RAW data from the RAW decompression unit 33 and then executes signal correction processing represented by white balance adjustment under the control of the CPU 26. Further, the image data after signal correction is converted into a luminance signal (Y) and a color difference signal (RY, BY) in a predetermined format such as 4: 2: 2.

  The resolution conversion unit 24 receives image data processed by the camera signal processing unit 23 or image data decompressed and decoded by the JPEG engine 25 and converts the image data into a predetermined resolution.

  The JPEG engine 25 compresses and encodes the image data processed by the resolution converter 24 to generate JPEG encoded data. Further, JPEG image data read from the storage device 16 is decompressed and decoded. The digital image processing circuit 13 may be provided with an encoding / decoding engine of a still image compression method or a moving image compression method other than the JPEG engine 25.

  The CPU 26 executes a program stored in the ROM 15 to control the digital image processing circuit 13 and the entire imaging apparatus in a centralized manner, and executes various operations for the control.

  The video output encoder 27 is configured as an NTSC (National Television Standards Committee) encoder, for example, and generates an image signal for monitor display based on the image data output from the resolution conversion unit 24 or the like. The video is output to the video output terminal 27a.

  The SDRAM controller 28 is an interface block for the SDRAM 14 and includes an address decoder and the like, and controls writing and reading operations of the SDRAM 14 according to a control signal from the CPU 26.

  The SDRAM 14 is a volatile memory prepared as a work area for data processing in the digital image processing circuit 13, and temporarily captures data captured from the image sensor 11, that is, RAW data compressed by the RAW compression unit 31. Capture data area 14a for temporary storage, JPEG code area 14b for temporarily storing image data encoded by the JPEG engine 25, data used in the encoding / decoding process, and the CPU 26 The CPU work area 14c for temporarily storing data used in the above process is included.

  The ROM 15 holds programs executed by the CPU 26 and various data. As the ROM 15, for example, a nonvolatile memory such as an EEPROM (Electronically Erasable and Programmable ROM) or a flash memory may be used.

  The storage device 16 is a device for recording an encoded image data file, and includes, for example, a recording medium such as a flash memory, an optical disk, and a magnetic tape, and a recording / reproducing drive thereof.

  In such an image pickup apparatus, an image pickup signal from the image pickup element 11 is sequentially supplied to the AFE circuit 12, subjected to CDS processing and AGC processing, converted into a digital signal, and supplied to the digital image processing circuit 13. . In the camera signal preprocessing unit 21, RAW data is generated by performing defective pixel correction, shading correction, or the like on the input image signal. The RAW data is compressed by the RAW compression unit 31 and then stored in the SDRAM 14. Once written.

  The RAW data is read from the SDRAM 14, expanded by the RAW expansion unit 32, and then supplied to the detection unit 22. The detection unit 22 performs a predetermined detection process based on the read image data, and notifies the CPU 26 of the detection result via the SDRAM 14, for example. The CPU 26 calculates various control values for AF, AE, and white balance adjustment based on the notified detection result.

  On the other hand, the RAW data in the SDRAM 14 is also read out and expanded by the RAW expansion unit 33 and then supplied to the camera signal processing unit 23. The camera signal processing unit 23 performs various image quality correction processes such as white balance adjustment on the input image data in accordance with the control of the CPU 26 based on the calculation of the control value.

  The image data after the image quality correction processing is temporarily stored in, for example, the SDRAM 14, converted into data having a resolution suitable for display by the resolution conversion unit 24, and further stored in, for example, the SDRAM 14, and then supplied to the video output encoder 27. Is done. Thereby, a camera through image is displayed on the monitor.

  When image recording is requested through an input unit (not shown) or the like, the resolution conversion unit 24 converts the image data subjected to image quality correction processing by the camera signal processing unit 23 to a resolution set for recording as necessary. For example, the JPEG engine 25 compresses and encodes the image data to generate encoded data. For example, the encoded data is once recorded in the SDRAM 14 and then recorded in the storage device 16.

  Further, the image data (encoded data) recorded in the storage device 16 is decompressed and decoded by the JPEG engine 25, converted in resolution by the resolution converter 24, and then output to the video output encoder 27. Can be displayed.

  In such a digital image processing circuit 13, a RAW compression unit 31 that compresses RAW data is provided at the input position of the image data from the camera signal preprocessing unit 21 to the internal bus 29, and is transmitted to the SDRAM 14 through the internal bus 29. Thus, the amount of RAW data to be recorded can be reduced. Further, by providing RAW expansion units 32 and 33 for expanding RAW data at the input positions of the image data from the internal bus 29 to the detection unit 22 and the camera signal processing unit 23, respectively, the detection unit 22 from the SDRAM 14 is similarly detected. In addition, the amount of RAW data transmitted to the camera signal processing unit 23 can be reduced.

  As a result, the transmission load of the internal bus 29 during the imaging operation can be reduced, and the time required for the writing / reading processing with respect to the SDRAM 14 can be shortened. In particular, by simplifying the compression / decompression process as much as possible, the effect of shortening the processing time can be increased. In addition, power consumption can be suppressed by reducing the transmission frequency on the bus.

  Further, the capacity of the SDRAM 14 can be reduced. Alternatively, the area of the SDRAM 14 is used for other processing, RAW data for a plurality of frames is stored, the number of continuous shots is increased, or the continuous shooting speed is improved, which contributes to higher image quality and higher functionality. You can also. Therefore, it is possible to realize a high-performance, small-sized and low-cost imaging device in which the time required for imaging and data recording is shortened.

  As will be described later, the RAW compression unit 31 and the RAW expansion units 32 and 33 can perform fixed-length encoding, maintain good image quality, and can be realized by relatively simple processing. Reversible compression / decompression technique is used. By encoding with a fixed length, the transmission load on the internal bus 29 and the capacity of the capture data area 14a on the SDRAM 14 can be stably reduced, and the read / write control processing in the SDRAM 14 can be simplified. In addition, since the compression / decompression process is simplified and speeded up, the imaging operation is reliably speeded up.

  Next, detection processing in the detection unit 22 of the digital image processing circuit 13 will be described. In the detection unit 22 according to the present embodiment, a RAW data is sequentially read out from the SDRAM 14 line by line (referred to as a normal detection method) and a number of detection frames are used, and RAW data corresponding to the detection frames is arbitrarily set. Detection can be performed by two types of methods (called a multi-detection method) that can be acquired and detected.

  By adopting a multi-detection method using a larger number of detection frames, it becomes possible to perform finer control during an imaging operation or image quality correction. For example, improve the accuracy of light source determination in focus adjustment and white balance control, control the brightness so that overexposure and underexposure do not occur, and optimize the brightness and color reproduction status according to the shooting scene and user settings It becomes possible to do. Furthermore, by performing detection in combination with a plurality of methods having different detection frame sizes, such as the above-described normal detection method and multi-detection method, more appropriate and fine control can be executed according to the purpose of the control. Will be possible, and there will be greater benefits such as improved image quality and higher functionality.

  The information detected by the camera signal processing unit 23 includes, for example, luminance information, color difference information, information on each component of RGB (Red, Green, Blue), an integrated value for each detection frame, or a predetermined value. A histogram or the like based on the threshold value can be considered. The normal detection method described below is used, for example, for detection of HPF output of luminance information for AF control. In addition, the multi-detection method is used, for example, for detection of integral values of luminance information for AE control, detection of histograms, integration values of RGB components for white balance adjustment, and the like.

FIG. 2 is a diagram for explaining an example of the normal detection method.
In the normal detection method, as shown in FIG. 2A, five detection frames Fa1 to Fa5 that are relatively large are set, and it is possible to individually detect each detection frame Fa1 to Fa5. . In this normal detection method, as shown in FIG. 2B, the RAW data stored in the SDRAM 14 is sequentially read out line by line and input to the detectors corresponding to the detection frames Fa1 to Fa5. It should be noted that the data in the image can be read by thinning out every predetermined line as necessary. Further, in addition to detection using such detection frames Fa1 to Fa5, detection may be performed from the entire screen.

  Here, since the detection frames Fa2 to Fa4 are provided in parallel in the horizontal direction, when the RAW data is read line by line, the RAW data for all the lines included in each detection frame Fa2 to Fa4 is obtained. Detection is not completed until read. Accordingly, a detector corresponding to each of the detection frames Fa2 to Fa4 is provided, and input data is temporarily stored in an internal register or the like in each detector until detection of the RAW data of all necessary lines is completed and detection is completed. It is necessary to keep it.

FIG. 3 is a diagram for explaining an example of the multi-detection method.
In the multi-detection method, detection can be performed from a larger number of detection frames (that is, smaller divided frames) as compared with the normal detection method of FIG. In particular, in this multi-detection method, more detection frames are provided in the horizontal direction than in the normal detection method. In the present embodiment, as shown in FIG. 3A, detection frames Fb1 to Fb49 obtained by dividing the screen into, for example, 7 × 7 areas are set. FIG. 3B shows a reading method when RAW data corresponding to each of the detection frames Fb1 to Fb49 is individually read from the SDRAM 14. In FIG. 3, the detection frames Fb <b> 1 to Fb <b> 49 are shown spaced apart from each other, but actually, the detection frames may be provided without any gaps.

  Here, a configuration example of a conventional detection unit capable of detecting by both the normal detection method and the multi-detection method is shown for reference. FIG. 4 is a block diagram showing a configuration example of such a conventional detection unit.

  The conventional detector 22a shown in FIG. 4 includes a Y-C synthesizer 210, normal detectors 221 to 225, and multi-detectors 231 to 237. In addition, a DMA (Direct Memory Access) controller 22b that controls reading of data from the SDRAM 14 under the control of the CPU 26 is provided at the input stage of the detection unit 22a. In this conventional configuration, since it is assumed that RAW data compression processing is not performed, the RAW expansion unit 32 is not provided in the input stage of the detection unit 22a.

  In this conventional configuration, the RAW data read from the SDRAM 14 is converted into luminance information or color difference information by the Y-C synthesis unit 210 as necessary, and is sent to any one of the detectors 221 to 225 and 231 to 237 each time. Supplied. That is, when the output data from the Y-C combining unit 210 is detected by the normal detection method, for example, it is distributed to the signal system of the detectors 221 to 225 for normal detection and detected by the multi-detection method. In this case, the signals are distributed to the signal systems of the detectors 231 to 237.

  The detectors 221 to 225 correspond to the detection frames Fa1 to Fa5 of the normal detection method shown in FIG. Here, in the normal detection method, as described above, the RAW data on the SDRAM 14 is supplied to one of the detectors 221 to 225 for each line. That is, when detection is performed by the detectors 221 to 225, the DMA 22b sequentially reads out the RAW data on the SDRAM 14 line by line in accordance with control from the CPU 26 and supplies it to the detection unit 22a. In the normal detection method, the detection frames Fa2 to Fa4 are provided in parallel in the horizontal direction as shown in FIG. 2A. Therefore, when RAW data is supplied for each line, the detection frames Fa2 to Fa2 are provided. At least three detectors 222 to 224 corresponding to Fa4 are required.

  On the other hand, the detectors 231 to 237 are provided for detection by a multi-detection method, and each correspond to a detection frame provided in parallel in the horizontal direction as shown in FIG. For example, when detecting from the detection frames Fb1 to Fb7, the detectors 231 to 237 detect the detection frames Fb1 to Fb7, respectively. As described above, conventionally, the RAW data on the SDRAM 14 is read for each line and supplied to the detectors 231 to 237 even in the multi-detection system in accordance with the operation in the normal detection system. There are as many detectors as there are horizontal detection frames.

  Here, since the number of detection frames is relatively small in the normal detection method, even if detectors are provided as many as the number of detection frames arranged in parallel in the horizontal direction, the circuit scale and manufacturing cost increase by that much. I didn't. However, in the multi-detection method, it is required to set more detection frames in the horizontal direction. When there are a large number of detection frames, an increase in circuit scale and manufacturing cost becomes a big problem. In particular, the detector needs to be provided with a register or the like for holding the input data until data is input to all lines of the corresponding detection frame. It becomes a very large circuit.

  On the other hand, if the RAW data is not read from the SDRAM 14 for each line but can be controlled to read only the necessary amount for each detection frame as shown in FIG. Can be reduced. However, when a reading method different from the detectors 221 to 225 of the normal detection method is applied to the detectors 231 to 237, the reading control by the CPU 26 becomes very complicated and difficult to realize.

  Further, in FIG. 4, when both the detection by the normal detection method using the detectors 221 to 225 and the detection by the multi-detection method using the detectors 231 to 237 are used, the amount of RAW data read from the SDRAM 14 increases. As a result, the transmission load of the internal bus 29 increases, and the time required for reading from the SDRAM 14 also increases. For example, when performing detection over the entire screen in both the normal detection method and the multi-detection method, it is necessary to read RAW data for one screen from the SDRAM 14 twice.

On the other hand, FIG. 5 is a block diagram showing a configuration example of a detection unit applied to the present embodiment. In FIG. 5, the functions corresponding to those in FIG. 4 are denoted by the same reference numerals.
As shown in FIG. 5, the detection unit 22 applied to the present embodiment includes a selector 200, Y-C combining units 211 and 212 for a normal detection method and a multi-detection method, respectively, and a normal detection method. Detectors 221 to 225 and a detector 230 for the multi-detection method. A RAW decompression unit 32 is provided at the input stage of the detection unit 22, and a DMA controller 22 b that controls reading of data from the SDRAM 14 through the internal bus 29 is provided at the input stage. Furthermore, a DMA controller 22 c that controls writing of the detection result to the SDRAM 14 through the internal bus 29 is provided at the output stage of the detector 230.

  Here, in the present embodiment, in the RAW compression unit 31, among the input RAW data, a fixed number (for example, 16 pixels) of the same color component pixel data arranged in parallel in the horizontal direction is regarded as one block, and the compressed image data. Is generated. The RAW decompression unit 32 in FIG. 5 decompresses the compressed image data read from the SDRAM 14 in units of blocks and outputs the decompressed data to the detection unit 22.

  The selector 200 distributes the input expanded pixel data to one of the Y-C combining units 211 and 212 under the control of the CPU 26. That is, RAW data detected by the normal detection method is output to the Y-C combining unit 211, and RAW data detected by the multi-detection method is output to the Y-C combining unit 212. The selector 200 switches the output in units of blocks, that is, in units of 16 pixels at the minimum.

  The Y-C combining units 211 and 212 are individually provided for the normal detection method and the multi-detection method, so that different types of data can be generated according to the detection method.

  As described with reference to FIG. 4, the detectors 221 to 225 detect input data corresponding to the detection frames Fa <b> 1 to Fa <b> 5 illustrated in FIG. 2. On the other hand, the detector 230 corresponds to one of the detectors 231 to 237 shown in FIG. 4, and can detect from any of the detection frames Fb1 to Fb49 shown in FIG.

  The DMA controller 22c can control writing of the detection result by the detector 230 to the SDRAM 14 separately from the reading control from the SDRAM 14 by the DMA controller 22b. For example, when the SDRAM 14 has input / output individual channels, the detection result of the detector 230 can be written to the SDRAM 14 when the detectors 221 to 225 perform detection by the normal detection method. . The detected value written in the SDRAM 14 is read by the CPU 26 and used for calculations for various adjustment controls.

  Although not shown, the detection values by the detectors 221 to 225 are also temporarily stored in the SDRAM 14 after the detection is completed and used by the CPU 26. Alternatively, these detection values may be read directly by the CPU 26. However, since the detection frames Fa1 to Fa5 corresponding to the detectors 221 to 225 are larger than the detection frames Fb1 to Fb49 corresponding to the detector 230, the output interval of the detection results from the detectors 221 to 225 is from the detector 230. Much longer than the output interval.

  Here, the DMA controller 22b reads the RAW data from the SDRAM 14 as compressed image data compressed in units of blocks under the control of the CPU 26. That is, the RAW data is read from the SDRAM 14 in units of blocks each including a certain number of pixel data, and is supplied to the detection unit 22. The number of pixels included in the block is the same as the number of pixels of the same color component included in the horizontal pixels of the detection frames Fb1 to Fb49 in the multi-detection method, or the number of pixels is equally divided. Is desirable.

  Therefore, by sorting the RAW data read in block units by the selector 200, the reading of the RAW data for the detectors 221 to 225 and the reading of the detector 230 can be individually controlled. For example, in this embodiment, RAW data in units of blocks is continuously read and supplied to the detectors 221 to 225 for one line as in the conventional normal detection method. Further, for the detector 230, it is possible to arbitrarily select the detection frames Fb1 to Fb49 and individually read out only the RAW data necessary for the detection frame. Then, RAW data reading for each line and RAW data reading corresponding to an arbitrary detection frame are alternately executed in a time division manner, and distributed by the selector 200 to supply the RAW data to a desired detector. It becomes possible.

  Instead of the configuration in which one DMA controller 22b for reading is provided as shown in FIG. 5, a separate reading DMA controller and RAW expansion unit are provided for each of the normal detection method and the multi-detection method. Even if the data read and decompressed by the system is supplied directly to the Y-C combining units 211 and 212 without using the selector 200, the same operation as described above is possible.

  In this way, the RAW data at an arbitrary position on the screen can be read and supplied to the detector 230, so that the number of detectors for the multi-detection method can be reduced to one. The circuit scale is reduced and the manufacturing cost is also suppressed.

  In addition, since it is not necessary to hold input data for one line and a detection value from one detection frame can be immediately output to the SDRAM 14 or the like, a circuit required for the detection unit 22 is provided with the number of detection frames. And the position of the required detection frame. In other words, if the detection frame has the same size, no matter how many detection frames are set on the screen or any position from which detection frame is required, only one detector 230 is required. Can be processed. Therefore, the degree of freedom of detection is increased without increasing the circuit scale, and finer control can be performed for the imaging operation and image quality correction.

  Further, by storing the compressed RAW data in the SDRAM 14 and reading the compressed RAW data, the detection by the normal detection method and the detection by the multi-detection method are performed as described above. Even when executed in parallel, the transmission load of read data on the internal bus 29 is reduced, and the time required for reading from the SDRAM 14 is also reduced. For example, even when detection is performed over the entire screen using both the normal detection method and the multi-detection method, if the RAW data compression rate is ½ as will be described later, uncompressed RAW data for one screen is stored in the SDRAM 14. It can be realized with the same processing time and transmission load as when reading from the network.

  Therefore, without increasing the circuit scale and manufacturing cost, the imaging operation and the accuracy of image quality correction are high, or various adjustment functions at the time of imaging are installed and the functions are improved, so that imaging capable of high-speed imaging operation is possible. An apparatus can be realized.

  Next, a RAW data compression / decompression technique applied in this embodiment will be described. In this embodiment, as will be described below, a lossy compression / decompression method that can perform fixed-length encoding, maintain good image quality, and can be realized with relatively simple processing. adopt.

  Here, by enabling encoding of a fixed length, it is possible to keep the bandwidth of RAW data read / written to / from the SDRAM 14 constant, and to stably reduce the transmission load on the internal bus 29. Also, handling of RAW data (for example, read control processing from the SDRAM 14) in the detection unit 22 and camera signal processing unit 23 and transmission control processing of RAW data through the internal bus 29 can be simplified. In particular, the detection unit 22 performs fixed-length encoding, thereby simplifying the CPU 26 reading address designation to the DMA 22b and the selector 200 switching control.

  In the following example, the RAW data signal is fixed to 14 bits per pixel, the quantization word length is fixed to 7 bits, and 16 pixels in the horizontal direction having the same color component are converted into one block of encoded data. For example, 14-bit data occupies a 16-bit area in the SDRAM 14. As described above, assuming 16 pixels as one block, when RAW data corresponding to one block is recorded in the SDRAM 14 without being compressed, an area of 256 bits is occupied. In the present embodiment, such recording is performed. The area can be compressed to 128 bits, and a 1/2 compression ratio can be achieved.

FIG. 6 is a block diagram showing an internal configuration of the RAW compression unit.
As shown in FIG. 6, the RAW compression unit 31 includes a polygonal line compression unit 301, a blocking unit 302, a maximum / minimum detection unit 303, a minimum value latch unit 304, a maximum value latch unit 305, a minimum value address latch unit 306, a maximum A value address latch unit 307, subtracters 308 and 309, a quantizer 310, a quantized data buffer 311, and a packing unit 312 are provided.

  The polygonal line compression unit 301 nonlinearly compresses the input 14-bit RAW data into 11-bit data by approximation using a polygonal line. The broken line compression unit 301 is provided for the purpose of improving the overall compression efficiency by reducing the gradation as much as possible before the subsequent compression procedure. For this reason, it may be omitted depending on the target compression rate. In this case, it is also necessary to omit the reverse broken line conversion unit provided at the output stage of the RAW expansion unit 32 described later with reference to FIG.

Here, FIG. 7 is a figure which shows the example of the broken line used in a broken line compression part.
FIG. 7 shows an example in which the gradation of the input data is converted by straight lines having five inclinations divided by four points. In this example, in accordance with human visual characteristics, a higher gradation is assigned as input data is smaller, that is, darker (or lighter in color). Such a polygonal line may be prepared for each color component, for example, and used by switching for each color component of the input pixel.

  In the polygonal line compression unit 301, for example, after converting the gradation of the input data using such a polygonal line, the converted data is divided by 8 (that is, shifted downward by 3 bits) to be converted into 11-bit data. Compress. At this time, the discarded lower bits are rounded off, for example. Alternatively, the polygonal line compression unit 301 prepares a ROM table that stores the input data and the compressed output data in association with each other based on the above calculation, and the input / output data is converted according to the ROM table. Also good.

Hereinafter, the description will be returned to FIG.
The blocking unit 302 separates the data output from the polygonal line compression unit 301 into blocks composed of the same color component pixels for 16 pixels adjacent in the horizontal direction, and outputs the separated blocks. Thereby, the correlation of the data in a block becomes strong, and the image quality deterioration by subsequent quantization processing can be suppressed.

  For example, when the Bayer array image sensor 11 is used, in the output data, the repetition of the R component and the Gr component and the repetition of the B component and the Gb component appear for each line. As an example, when the R component and the Gr component repeatedly appear in the input data to the blocking unit 302 such as R0, Gr0, R1, Gr1,..., R15, Gr15, R0, R1, R2,. .., R15, Gr0, Gr1,..., Gr15, the output order is changed so that 16 pixels of the same color component appear continuously, and the blocks are formed.

  The maximum / minimum detection unit 303 detects the maximum value and the minimum value in one block. Specifically, the maximum value and minimum value in one block, and the addresses indicating the number of pixels having the maximum value and minimum value from the beginning of one block (hereinafter referred to as maximum value address and minimum value address). ) Is detected. The maximum value address and the minimum value address are detected as address values of 0 to 15, respectively.

  However, considering the case where there are multiple pixels with the same value in the block and the value is the maximum value or the minimum value, the following determination rules are used for determining the maximum value and the minimum value: By providing this, confusion in compression / decompression processing is avoided. First, in determining the maximum value, as the initialization operation, the value of the 0th pixel is captured as a temporary maximum value (temporary maximum value). Next, for the first to fifteenth pixels, if the value is not less than the temporary maximum value, the temporary maximum value is updated with the value of that pixel. Thereby, the temporary maximum value after the determination of the 15th pixel is determined as the maximum value in the block.

  In determining the minimum value, similarly, as the initialization operation, the value of the 0th pixel is taken in as a temporary minimum value (temporary minimum value). Next, for the 1st to 15th pixels, if the value is less than the temporary maximum value, the temporary minimum value is updated with the value of the pixel. Thereby, the temporary minimum value after the determination of the 15th pixel is determined as the minimum value in the block.

  For example, of the 16 pixels, when the first two pixels (0th and 1st) have the same maximum value, the maximum value address is “1”. When all 16 pixels have the same value, the minimum value address is “0” and the maximum value address is “15”.

  The maximum / minimum detection unit 303 outputs the detected minimum value and maximum value to the minimum value latch unit 304 and the maximum value latch unit 305, respectively, and the minimum value address and the maximum value address are respectively output to the minimum value address latch unit. 306 and the maximum value address latch unit 307. Further, the input data for one block is sequentially output to the subtracter 308 after the maximum and minimum determinations of the block are completed.

  The minimum value latch unit 304 and the maximum value latch unit 305 latch the minimum value and the maximum value from the maximum / minimum detection unit 303, respectively. Further, the minimum value address latch unit 306 and the maximum value address latch unit 307 latch the minimum value address and the maximum value address from the maximum / minimum detection unit 303, respectively. The minimum value latch unit 304, the maximum value latch unit 305, the minimum value address latch unit 306, and the maximum value address latch unit 307 have their blocks until the block corresponding to the input data is encoded in the packing unit 312. Latch input data.

  The subtracter 308 subtracts the minimum value of the corresponding block output from the minimum value latch unit 304 from the pixel data output from the maximum / minimum detection unit 303. This subtraction is equivalent to subtracting the DC offset common to the pixels in one block from the data of each pixel.

  The subtractor 309 subtracts the minimum value of the corresponding block output from the minimum value latch unit 304 from the maximum value output from the maximum value latch unit 305. This subtraction result indicates the dynamic range (DR) at the time of quantization.

  The quantizer 310 quantizes the output data of the subtracter 308 according to the size of the dynamic range output from the subtractor 309. In this embodiment, as an example, quantization is performed with a fixed length of 7 bits.

  As the quantizer 310, for example, a configuration in which the output data of the subtracter 308 is divided by the dynamic range using an integer type divider can be applied. Also, when the quantization step is limited to a power of 2, a bit shifter that operates as follows can be applied, thereby reducing the circuit scale. If such a bit shifter is used on the compression processing side, the circuit scale can be similarly reduced in the inverse quantization on the decompression processing side.

When the 11-bit input data from the subtracter 308 is quantized into 7-bit data, for example, the following shift operation may be performed.
[When 0 ≦ DR ≦ 127] The input data is output as it is.

[When 128 ≦ DR ≦ 255] The input data is shifted downward by one bit.
[When 256 ≦ DR ≦ 511] The input data is shifted down by 2 bits.
[When 512 ≦ DR ≦ 1023] The input data is shifted downward by 3 bits.

[When 1024 ≦ DR ≦ 2047] The input data is shifted downward by 4 bits.
The quantized data buffer 311 temporarily holds the quantized data for 16 pixels output from the quantizer 310.

  The packing unit 312 uses the output data from the quantized data buffer 311, the minimum value latch unit 304, the maximum value latch unit 305, the minimum value address latch unit 306, and the maximum value address latch unit 307 to 128 per block. Pack into bit compressed data. The packing unit 312 reads out the quantized data corresponding to each pixel from the quantized data buffer 311, based on the output data of the minimum value address latch unit 306 and the maximum value address latch unit 307, and the maximum value and the minimum value. The quantized data corresponding to is discarded, and only the quantized data for the remaining 14 pixels in the block is packed as shown in FIG.

FIG. 8 is a diagram showing a configuration of compressed data for one block generated by packing.
As shown in FIG. 8, the compressed data includes a maximum value and a minimum value (both 11 bits) in the block, a maximum value address and a minimum value address (both 4 bits) corresponding to these values, a maximum value and It consists of quantized data (98 bits) for 14 pixels excluding the pixel having the minimum value.

  Here, since the maximum value and the minimum value in the block are packed, the corresponding quantized data is omitted, and instead, the maximum value address and the minimum value address indicating the positions of these pixels are packed. The original data can be restored when decompressing. Since the quantized data is 7 bits, the address is 4 bits because of 16 addresses, and from these differences, a reduction effect of 6 bits can be obtained by combining the maximum value and the minimum value per block. As described above, 128-bit data obtained by compressing RAW data for 16 pixels occupying a memory area for 256 bits to 1/2 is obtained.

  Next, FIG. 9 is a block diagram showing an internal configuration of the RAW expansion unit. In the following, the RAW expansion unit 32 will be described, but the RAW expansion unit 33 has the same configuration, and thus the description thereof is omitted here.

  As shown in FIG. 9, the RAW decompression unit 32 includes a data latch unit 321, a selector 322, a subtracter 323, an inverse quantizer 324, an adder 325, an address counter 326, an address comparison unit 327, a selector 328, and an inverse broken line transform. A unit 329 and a dot sequential processing unit 330.

  The data latch unit 321 latches 128-bit compressed data read from the SDRAM 14. The data latch unit 321 latches the input data until all the blocks corresponding to the input data are processed in the selector 328.

  The selector 322 receives quantized data (98 bits) among the data latched by the data latch unit 321 and sequentially selects 7-bit data corresponding to one pixel from the data, and performs inverse quantization. To the container 324.

  The subtractor 323 receives the maximum value (11 bits) and the minimum value (11 bits) among the data latched by the data latch unit 321, subtracts the minimum value from the maximum value, and outputs the dynamic range.

  The inverse quantizer 324 inversely quantizes the quantized data for each pixel from the selector 322 according to the size of the dynamic range. In this embodiment, a 7-bit fixed length code is inversely quantized and 11-bit data is output.

  As the inverse quantizer 324, for example, a configuration of multiplying quantized data and a dynamic range by using an integer multiplier can be applied. In addition, as described in the description of the quantizer 310 above, when the quantization step is limited to a power of 2, it can be configured by a bit shifter, thereby reducing the circuit scale. it can. This bit shifter operates, for example, as follows.

[When 0 ≦ DR ≦ 127] The input data (quantized data) is output as it is.
[When 128 ≦ DR ≦ 255] The input data is shifted upward by one bit.
[When 256 ≦ DR ≦ 511] The input data is shifted upward by 2 bits.

[When 512 ≦ DR ≦ 1023] The input data is shifted upward by 3 bits.
[When 1024 ≦ DR ≦ 2047] The input data is shifted upward by 4 bits.
The adder 325 adds the output data of the inverse quantizer 324 and the minimum value latched by the data latch unit 321. As a result, a common DC offset value in the block is added to the dequantized data.

The address counter 326 performs a count-up operation in accordance with the pixel output timing, and generates a count value (0 to 15) corresponding to the pixel order in the block.
The address comparison unit 327 receives the maximum value address and the minimum value address among the data latched by the data latch unit 321, compares it with the count value from the address counter 326, and if it matches the value of each address, the selector A selection signal is output to 328.

  The selector 328 selects and outputs the data from the adder 325 and the maximum and minimum values from the data latch unit 321. Specifically, when the selection signal corresponding to the minimum value address is received from the address comparison unit 327, the maximum value from the data latch unit 321 is selected and output, and the selection signal corresponding to the minimum value address is received. Selects and outputs the minimum value from the data latch unit 321, and otherwise selects and outputs the data from the adder 325. Thereby, the data of the same color pixel compressed to 11 bits is expanded in pixel order.

The reverse broken line conversion unit 329 expands the data from the selector 328 from 11 bits to 14 bits of data by the reverse characteristics of the RAW compression unit 31 and the broken line compression unit 301.
Here, FIG. 10 is a diagram illustrating an example of a polygonal line used in the reverse polygonal line conversion unit.

  The polygonal line in FIG. 10 is adapted to convert the gradation by characteristics opposite to those of the polygonal line compression unit 301 shown in FIG. The inverse broken line conversion unit 329 first multiplies the input data by 8 (that is, shifts upward by 3 bits) to 14 bits, and then performs gradation conversion using the broken line in FIG. 10 to obtain 14-bit pixel data. Stretch. A ROM table in which input data and decompressed output data are stored in association with each other may be prepared, and input / output data conversion may be performed according to the ROM table.

If compression by the polygonal line compression unit 301 is not applied at the time of compression, data conversion at the reverse polygonal line conversion unit 329 is also bypassed at the time of decompression.
Hereinafter, the description will be returned to FIG.

  The dot sequential processing unit 330 converts the decompressed data into the pixel order of the original RAW data by the reverse process of the blocking performed by the blocking unit 302 of the RAW compression unit 31 and outputs the converted data. For example, this is the case when 16 pixels of the same color component are blocked and compressed such that R0, R1, R2,..., R15, Gr0, Gr1,. Are rearranged so that the R component and the Gr component appear repeatedly, such as R0, Gr0, R1, Gr1,..., R15, Gr15. In order to perform such rearrangement, the dot-sequential processing unit 330 includes a buffer memory for holding the expanded data for two blocks, and when the data for two blocks are accumulated in the buffer memory, Data of each color component is output alternately.

  According to the RAW compression unit 31 and the RAW expansion units 32 and 33 having the above-described configuration, the quantization word length per pixel at the time of compression is set to a fixed length, so that the compression can be performed by performing the fixed length encoding. it can. Therefore, the bandwidth of data read / written to / from the SDRAM 14 through the internal bus 29 can be reduced to a certain level, and address management for the SDRAM 14 can be simplified.

  In addition, since the compression rate is determined by the combination of the number of pixels of one block to be compressed and the quantization word length, the required image quality (that is, the amount of allowable compression distortion) and the allocation of the transmission band on the transmitted bus Therefore, it is possible to flexibly cope with the read / write performance of the SDRAM 14. For example, as in the above-described embodiment, RAW data for 16 pixels is quantized with a quantization word length of 7 bits, so that the compression rate is ½, but if it is a normal natural image, PSNR (Peak Signal to Noise Ratio) at the time of conversion into luminance / color difference signals after compression / expansion can be maintained at about 50 dB. If the PSNR of this signal is about 50 dB to 40 dB, the compression distortion can be suppressed to such an extent that it cannot be detected with the naked eye.

  In addition, since compression / decompression processing is basically executed by one-dimensional processing, for example, a line memory for referring to pixel data of the upper and lower lines becomes unnecessary, and processing becomes relatively simple. For this reason, the circuit scale for compression / decompression and the manufacturing cost can be suppressed, and the effect of speeding up the processing and shortening the processing time can be enhanced. That is, the effect of shortening the read / write time of RAW data in the SDRAM 14 and the effect of reducing the transmission load of the internal bus 29 can be reliably improved.

Accordingly, it is possible to realize an imaging apparatus that can record / display high-quality images at a high speed during imaging, and that is small in size and relatively low in manufacturing cost.
Note that the RAW compression unit 31 and the RAW expansion units 32 and 33 having the above-described configuration may perform variable length encoding by setting the quantization word length. For example, at the time of compression, by changing the quantization word length adaptively based on the dynamic range, variable length coding can be performed, and the compression efficiency can be further increased. Furthermore, image quality degradation can be completely prevented by lossless compression using the same technique. In this case, however, compression / decompression by a broken line is not performed.

  Further, the CPU 26 may adaptively control the settings of the RAW compression unit 31 and the RAW expansion unit 32. For example, the compression rate can be changed by controlling the quantization word length, the number of pixels in one block, or turning on / off the polygonal line compression / decompression function. The functions of the RAW compression unit 31 and the RAW expansion unit 32 may be turned on / off. For example, control such as turning on the compression / decompression function only during continuous shooting, or turning off the compression / decompression function in a mode in which RAW data is recorded in the storage device 16 can be applied.

  Further, even when the functions of the RAW compression unit 31 and the RAW expansion unit 32 are provided between the SDRAM controller 28 and the internal bus 29, for example, instead of the above positions, the time required for writing / reading RAW data to / from the SDRAM 14 Can be shortened and the capacity of the SDRAM 14 can be reduced.

  In the compression method described above, when the quantization step is a power of 2, the quantizer can be configured by a bit shifter. In this case, the shift amount indicates the dynamic range in the block. Here, when the maximum value in the block is quantized, it is obvious that all the bits thereof are 1. Therefore, on the expansion side, instead of the absolute value of the maximum value, the maximum value of the quantum value is calculated from the shift amount. Can be obtained and expanded.

  Therefore, by storing the shift amount (at least 3 bits in the above operation example) in the quantizer instead of the maximum value (11 bits) in the compressed data, the number of bits of data to be stored in the compressed data is reduced. be able to. Therefore, the image quality can be improved by further increasing the compression rate or increasing the quantization word length.

  In each of the above-described embodiments, an example in which RAW data is blocked and compressed for each line is shown. However, the above compression / decompression method is applied to block each rectangular area over a plurality of lines. Is also possible. For example, when an image sensor capable of reading out all pixels (progressive reading) such as a CMOS sensor is used, the pixel data is read out sequentially, so that the correlation of the pixel data with respect to the vertical direction becomes strong. Therefore, even if the pixels in the rectangular area are blocked, the compression can be performed without degrading the image quality. Furthermore, the rectangular area to be blocked can be the same as the detection frame used in the multi-detection method.

1 is a block diagram illustrating a configuration of an imaging apparatus according to a first embodiment of the present invention. It is a figure for demonstrating the example of a normal detection system. It is a figure for demonstrating the example of a multi detection system. It is a block diagram which shows the structural example of the conventional detection part. It is a block diagram which shows the structural example of the detection part applied to this Embodiment. It is a block diagram which shows the internal structure of a RAW compression part. It is a figure which shows the example of the broken line used in a broken line compression part. It is a figure which shows the structure of the compressed data for 1 block produced | generated by packing. It is a block diagram which shows the internal structure of a RAW expansion | deployment part. It is a figure which shows the example of the broken line used in a reverse broken line conversion part. It is a block diagram which shows the structural example of the conventional imaging device.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... Imaging device, 12 ... Analog front end (AFE) circuit, 13 ... Digital image processing circuit, 14 ... SDRAM, 14a ... Capture data area, 14b ... JPEG code area, 14c ... CPU work area , 15... ROM, 16... Storage device, 21... Camera signal preprocessing section, 22, 22a... Detection section, 22b and 22c. , 25... JPEG engine, 26... CPU, 27... Video output encoder, 27 a... Video output terminal, 28... SDRAM controller, 29... Internal bus, 31. ... RAW decompression unit, 200 ... selector, 211, 212 ... YC synthesis unit, 221 to 225, 230 ... Demultiplexer

Claims (21)

In an imaging device that captures an image using a solid-state imaging device,
A memory that temporarily holds image data captured by the solid-state imaging device and digitally converted;
A single detection unit configured to detect predetermined information based on input image data in each of a plurality of detection frames set on the screen as rectangular regions of the same size, each set at least in the horizontal direction; ,
A read control unit that reads out image data stored in the memory in units of blocks each including a predetermined number of pixels adjacent in a screen, and supplies the read data to the single detection unit;
An imaging device comprising:   The read control unit reads image data corresponding to a detection frame at an arbitrary position among detection frames of the single detection unit from the memory and supplies the image data to the single detection unit. The imaging device according to claim 1. A compression unit that compresses the digitally converted image data in units of blocks and supplies the compressed image data to the memory;
A decompression unit for decompressing the compressed image data read from the memory;
Another detection unit for detecting predetermined information based on input image data in a detection frame set on a screen as one or more rectangular areas larger than the detection frame of the single detection unit;
Further comprising
The read control unit reads the compressed image data held in the memory in units of blocks, expands the compressed image data to the expansion unit, and selectively supplies it to the single detection unit and the other detection units. The imaging apparatus according to claim 1, wherein:   The read control unit reads the compressed image data corresponding to a detection frame at an arbitrary position in the detection frame of the single detection unit from the memory, and the single detection unit via the decompression unit The imaging apparatus according to claim 3, wherein the imaging apparatus is supplied. The other detection units individually correspond to detection frames set as rectangular areas on the screen by a number smaller than the number of detection frames arranged in parallel in the single detection unit in the horizontal direction. At least an individual detector,
The read control unit sequentially reads the compressed image data for the number of horizontal lines on the image necessary for the individual detection unit from the memory for each horizontal line, and sends the compressed data to the other detection unit via the decompression unit. Supply,
The imaging apparatus according to claim 3.   The imaging apparatus according to claim 3, wherein the single detection unit stores the detection value in the memory every time detection in each detection frame is completed.   The read control unit reads the compressed image data for the single detection unit and the compressed image data for the other detection unit alternately from the memory in a time division manner. Imaging device.   The imaging apparatus according to claim 3, wherein the compression unit generates the compressed image data as fixed-length encoded data.   The decompression unit, the single detection unit, and the other detection unit are connected to the memory through a common bus, and the image data decompressed by the decompression unit is directly connected to the single unit without going through the bus. The imaging apparatus according to claim 3, wherein the imaging device is input to the other detector and the other detector.   The imaging apparatus according to claim 9, wherein the compression unit writes the compressed image data into the memory through the bus. A calculation unit that calculates various control values based on a detection result by at least one of the single detection unit and the other detection unit;
An image quality correction unit that performs an image quality correction process on the image data read from the memory and expanded by the expansion unit based on a control value calculated by the calculation unit;
The imaging apparatus according to claim 3, further comprising:   The compression unit is configured to calculate the minimum value and the minimum value of the pixel data in the block, the position information in the block, and the pixel data in the block excluding the maximum value and the minimum value. The imaging apparatus according to claim 3, wherein the compressed image data including quantized data obtained by quantizing a subtraction value obtained by subtracting a value is generated. The compression unit is
For each block, a maximum / minimum detection unit that detects the maximum value and the minimum value of the pixel data, and the position information in the block, and
A quantization unit that quantizes the subtraction value obtained by subtracting the minimum value in the corresponding block from the pixel data according to a dynamic range calculated as a difference value between the maximum value and the minimum value in the block. When,
For each block, the maximum value and the minimum value in the block, the position information thereof, and the quantized data quantized by the quantization unit, corresponding to the maximum value and the minimum value A packing unit that packs the quantized data except for generating the compressed image data;
The imaging apparatus according to claim 12, further comprising:   The imaging apparatus according to claim 13, wherein a quantization word length in the quantization unit is a fixed value.   The compression unit further includes a pre-compression unit that converts the gradation of the digitally converted image data according to human visibility characteristics and then supplies the compressed data to the compression unit after reducing the number of bits. The imaging apparatus according to claim 13.   14. The imaging apparatus according to claim 13, wherein the quantization unit quantizes the subtraction value with a bit shifter that shifts the quantization step to a power of 2 and shifts downward by a number corresponding to the dynamic range. .   The imaging apparatus according to claim 16, wherein the packing unit packs a shift amount in the bit shifter instead of the maximum value in the block. The extension part is
Inverse quantization for dequantizing the quantized data extracted from the compressed image data for each block according to the dynamic range calculated as a difference value between the maximum value and the minimum value extracted from the compressed image data And
An adder for adding the minimum value to the data dequantized by the dequantization unit;
Based on the position information of the minimum value and the maximum value extracted from the compressed image data for each block, the maximum value, the minimum value, and the output value from the adding unit are sent to the compression unit. An output control unit that outputs the input original pixel data in the order;
The imaging apparatus according to claim 13, further comprising:   The image pickup apparatus according to claim 3, wherein the block includes pixel data of the same color component.   The imaging apparatus according to claim 3, wherein the block includes pixel data included in a rectangular area on the captured image. In an imaging method for imaging an image using a solid-state imaging device,
A writing unit temporarily writing image data captured by the solid-state imaging device and digitally converted into a memory;
A step of reading out the image data written in the memory in units of blocks composed of a predetermined number of adjacent pixels in the screen, and supplying the read data to the single detector;
A plurality of the single detection units are set at least in the horizontal direction, and detection of predetermined information is performed based on input image data in each of a plurality of detection frames set on the screen as rectangular regions of the same size. The steps of
An imaging method comprising:

Images