JP2007214615A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device for realizing low power consumption and stable operations. <P>SOLUTION: The semiconductor integrated circuit device includes a plurality of function blocks operated by a current, corresponding to a constant current generated by a reference current source. One of the function blocks includes a first circuit that is operated by the constant current of a current source first transistor, in current-mirror connection with a second transistor of diode connection connected in series with a first transistor fur supplying the current corresponding to the constant current. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit device, for example, to a technique effective when used for a device having a plurality of circuit function blocks operating with a constant current source.

Japanese Patent Laid-Open No. 2003-283267 discloses an example in which a constant current is supplied to a plurality of circuits using a multi-stage current mirror. In this publication, a multi-stage current mirror is used to drive the organic EL panel by a current writing method.
JP 2003-283267 A

  FIG. 9 shows a block diagram of the semiconductor integrated circuit device previously examined by the present inventors. In FIG. 9, a plurality of circuit function blocks BLK1 to BLK3 are provided, a constant current Io is formed by the band gap reference circuit BGR, and the circuit function blocks BLK1 to BLK3 are operated based on the constant current Io. In the figure, a diode-connected P-channel MOSFET Q01 for passing the constant current Io is provided in the band gap reference circuit BGR. In each circuit function block BLK1 to BLK3, MOSFETs Q14 to Q15 and Q24 which are current mirror connected to the MOSFET Q01. To Q25 and Q30 to Q31 are provided.

  In the circuit function block BLK1, the constant current formed by the MOSFETs Q14 to Q15 is intermittently supplied to the functional circuit CKT1 by controlling the switches S1 and S2. For example, during a period in which the circuit function block BLK1 does not perform any operation, the switches S1 and S2 are turned off to reduce current consumption in the function circuit CKT1. In the circuit function block BLK2, the function circuit CKT2 is a ring oscillator, and the oscillation frequency is controlled by a constant current flowing in the MOSFETs Q24 to Q25. In the circuit function block BLK3, the function circuit CKT3 operates steadily by a constant current formed by the MOSFETs Q30 to Q31.

  In the circuit function block BLK1, noise is generated when the switches S1 and S2 are turned on to stop or restart the function circuit. In the circuit function block BLK2, noise is constantly generated by the oscillation operation in the function circuit CKT2. In general, the noise can be absorbed by the constant current Io of the band gap reference circuit BGR. The inventor of the present application studied to significantly reduce the constant current Io to about 1 μA (microampere) in order to reduce power consumption in the semiconductor integrated circuit device. However, if the current value of the constant current Io is set to a minute current in this way, the noise cannot be absorbed. For example, the circuit function block BLK3 receives both noises from the circuit function blocks BLK1 and BLK2. It has been found that there is a problem that normal operation cannot be performed. Note that Patent Document 1 only distributes a current for gradation display, and does not consider such noise.

  An object of the present invention is to provide a semiconductor integrated circuit device that realizes low power consumption and stable operation. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. It has a plurality of functional blocks that operate with a current corresponding to a constant current formed by a reference current source. One of the plurality of functional blocks includes a first transistor for passing a current corresponding to the constant current, a second transistor connected in series with the first transistor, diode-connected, and a current with the second transistor. A first circuit that operates with a constant current of the first current source transistor that is mirror-connected is included.

  The first and second transistors prohibit or reduce noise transmission from the first current source transistor side.

  FIG. 1 is a schematic block diagram of an embodiment of a semiconductor integrated circuit device according to the present invention. The semiconductor integrated circuit device of this embodiment has a plurality of circuit function blocks BLK1 to BLK3. The circuit function block BLK1 includes a function circuit CKT1 that operates with a constant current formed by P-channel type current source MOSFETs Q14 to Q15. The functional circuit CKT1 is selectively operated by an extrusion type constant current formed by the current source MOSFETs Q14 to Q15 via the switches S1 and S2. For example, in the sleep state or standby state, the switches S1 and S2 are turned off. In such a sleep state or standby state, current consumption in the circuit function CKT1 is reduced.

  The circuit function block BLK2 includes a function circuit CKT2 that operates by a constant current formed by the P-channel type current source MOSFETs Q24 to Q25, as described above. The functional circuit CKT2 is, for example, a ring oscillator, and the oscillation frequency is controlled by an extrusion type constant current formed by the current source MOSFETs Q24 to Q25. The circuit function block BLK3 has a function circuit CKT3 that operates by an extrusion type constant current formed by P-channel type current source MOSFETs Q30 to Q31. The functional circuit CKT3 is a circuit that operates steadily by a constant current formed by the current source MOSFETs Q30 to Q31.

  The current source MOSFETs Q14 to Q15, Q24 to Q25, and Q30 to Q31 of the circuit function blocks BLK1 to BLK3 are operated based on a constant current Io formed by the reference current source BGR. The reference current source BGR has a diode-connected P-channel MOSFET Q01 through which a constant current Io flows. Among the circuit function blocks BLK1 to BLK3, the circuit function block BLK1 is provided with a buffer amplifier BA1. The buffer amplifier BA1 is composed of P-channel MOSFETs Q10 and Q13 and N-channel MOSFETs Q11 and Q12. The P-channel MOSFET Q01 and the P-channel MOSFET Q10 of the reference current source BGR are connected in a current mirror form. The N-channel MOSFETs Q11 and Q12 are connected in a current mirror form, and convert the push-out current from the MOSFET Q10 into a sink current. The MOSFET Q13 is diode-connected so that an output current of a current mirror circuit constituted by the MOSFETs Q11 and Q12 flows. The MOSFET Q13 is connected to the current source MOSFETs Q14 to Q15 in a current mirror form.

  The circuit function block BLK2 is provided with a buffer amplifier BA2. The buffer amplifier BA2 has the same configuration as the buffer amplifier BA1. That is, it is composed of P-channel MOSFETs Q20 and Q23 and N-channel MOSFETs Q21 and Q22. The P-channel MOSFET Q01 and the P-channel MOSFET Q20 of the reference current source BGR are connected in a current mirror form. The N-channel MOSFETs Q21 and Q22 are connected in a current mirror form, and convert the push-out current from the MOSFET Q20 into a sink current. The MOSFET Q23 is diode-connected so that an output current of a current mirror circuit constituted by the MOSFETs Q21 and Q22 flows. The MOSFET Q23 is connected to the current source MOSFETs Q24 to Q25 in a current mirror form.

  The current source MOSFETs Q30 to Q31 of the circuit function block BLK3 are connected to the MOSFET Q01 of the reference current source BGR in a current mirror form. That is, in the circuit function block BLK3, the buffer amplifier BA1 is omitted, and the current source MOSFETs Q30 to Q31 for supplying an operating current to the circuit function CKT3 are directly in the form of a current mirror with the MOSFET Q01 of the reference current source BGR. Yes.

  In this embodiment, the constant current Io formed by the reference current source BGR is made as small as about 1 μA in order to reduce the power consumption. Correspondingly, in the circuit function block BLK1, the element sizes of the MOSFETs Q01 and Q10, Q11 and Q12 and Q13 and Q14 to Q15 constituting the current mirror circuit are appropriately set, and correspond to the element size ratio. Thus, current amplification is performed. That is, current amplification corresponding to the operating current of the circuit function CKT1 is performed. The same applies to the other circuit function blocks BLK2 and BLK3. Since the circuit amplifier block BLK3 does not have the buffer amplifier as described above, the operating current is set according to the element sizes of the MOSFETs Q01 and Q30 to Q31.

  In the circuit function block BLK1, noise is generated when the switches S1 and S2 are turned on to stop or restart the function circuit CKT1. This noise is reduced or reduced in transmission to the reference current source BGR due to the presence of the buffer amplifier BA1. For example, the parasitic capacitance between the drain and the gate of the MOSFET Q12 and the parasitic capacitance between the drain and the gate of the MOSFET Q10 serve as the noise transmission path, and the noise is attenuated by the parasitic capacitance and can be substantially eliminated. In the circuit function block BLK2, noise is constantly generated by the oscillation operation in the function circuit CKT2. This noise can also be substantially eliminated by the buffer amplifier BA2 in the same manner as described above to prohibit transmission to the reference current source BGR side. As a result, the circuit function block BLK3 directly connected to the reference current source BGR can perform a stable operation without being affected by the noise.

  FIG. 2 is a schematic block diagram of another embodiment of the semiconductor integrated circuit device according to the present invention. In the semiconductor integrated circuit device of this embodiment, in the same circuit function blocks BLK1 and BLK2, the function circuit CKT1 operates with a suction type constant current formed by N-channel type current source MOSFETs Q16 to Q16. The functional circuit CKT1 is selectively operated by a constant current formed by the current source MOSFETs Q16 to Q17 via switches S3 to S4. For example, in a state where the functional circuit CKT1 does not perform any operation, for example, a sleep state or a standby state, the switches S3 to S4 are turned off. In such a sleep state or standby state, current consumption in the circuit function CKT1 is reduced.

  The circuit function block BLK2 has a functional circuit CKT2 that operates by a suction type constant current formed by N-channel type current source MOSFETs Q26 to Q27. The functional circuit CKT2 is, for example, a ring oscillator, and the oscillation frequency is controlled by a suction type constant current formed by the current source MOSFETs Q27 to Q27. The circuit function block BLK3 includes a function circuit CKT3 that operates with a constant current formed by P-channel type current source MOSFETs Q30 to Q31. The functional circuit CKT3 is a circuit that operates steadily by a constant current formed by the current source MOSFETs Q30 to Q31.

  In the circuit function block BLK1 having the circuit function CKT1 that is selectively operated by the switches S1 and S2 and the circuit function block BLK2 having the circuit function CKT2 that operates steadily and generates large noise in the operation, such noise is generated. In order not to affect other circuit function blocks BLK3 and the like, buffer amplifiers BA1 and BA2 are provided as in FIG.

  The buffer amplifier BA1 is connected to the P-channel MOSFET Q01 in a current mirror form because the MOSFET Q01 of the reference current source BGR is a P-channel MOSFET and the necessary current source is composed of N-channel MOSFETs Q16 to Q17 and is a suction type. And a diode-connected N-channel MOSFET Q11 connected in series to the MOSFET Q10. That is, the current source MOSFETs Q16 to Q17 are connected to the MOSFET Q11 in the form of a current mirror. Similarly, the buffer amplifier BA2 includes a P-channel MOSFET Q20 and an N-channel MOSFET Q21.

  In the circuit function block BLK1, noise is generated when the switches S3 to S4 are turned on to stop or restart the function circuit CKT1. At this time, the transmission to the reference current source BGR is reduced or reduced by the presence of the buffer amplifier BA1. For example, the parasitic capacitance between the drain and gate of the MOSFET Q10 serves as a transmission path for the noise, and the noise is attenuated by the parasitic capacitance and can be substantially eliminated. In the circuit function block BLK2, the noise that is constantly generated by the oscillation operation in the function circuit CKT2 is also substantially deleted in the same manner as described above by the buffer amplifier BA2, and transmission to the reference current source BGR side is prohibited. Can do. As a result, the circuit function block BLK3 directly connected to the reference current source BGR can perform a stable operation without being affected by the noise.

  1 and 2 corresponds to the conductivity type of the output MOSFET of the reference current source BGR and the conductivity type of the current source MOSFET required in the circuit function CKT, and the type of FIG. You should use them properly like the ones. For example, in the semiconductor integrated circuit device, the circuit function block BLK1 in FIG. 1 and the circuit function block BLK2 in FIG. 2 may be combined.

  In a circuit function that does not generate noise as in the circuit operation CKT3, if a necessary current source is a suction type current source, a MOSFET such as the buffer amplifier BA1 of FIG. 2 is provided. In the reference current source BGR, N-channel MOSFETs Q10 and Q11 like the buffer amplifier BA1 of FIG. 2 are provided, and the constant voltage directed to the push-type current source composed of the P-channel MOSFET with the P-channel MOSFET Q01 and MOSFET Q11 as output MOSFETs, N You may make it form the constant voltage toward the suction type power source which consists of channel MOSFETs.

  FIG. 3 shows a circuit diagram of an embodiment of the reference current source according to the present invention. Each circuit element in the figure is formed on one semiconductor substrate such as single crystal silicon together with other circuit elements (not shown) by a known Bi-CMOS integrated circuit manufacturing technique.

  The band gap generating unit includes a pair of npn-type bipolar transistors T1 and T2 and resistors R1 to R3. The transistors T1 and T2 are formed so that the size of the transistor T1 is n times larger than that of the transistor T2. That is, by setting the size of the transistor T1 large, when the same current flows through the transistors T1 and T2, the emic current density of the transistor T2 is set to be n times the emitter current density of the transistor T1. The

  Corresponding to the difference between the emitter current densities of the transistors, the bases and emitter voltages Vbe1 and Vbe2 of the transistors T1 and T2 are formed so that the base and emitter voltage Vbe1 of the transistor T2 is increased by a constant voltage ΔVbe corresponding to the silicon band gap. Is done. The bases of the transistors T1 and T2 are made common, one end of the resistor R1 is connected to the emitter of the transistor T1, and the ground potential VSS of the same circuit as the emitter of the transistor T2 is supplied to the other end of the resistor R1. A voltage ΔVbe is applied across the resistor R1, where a constant current is formed. The collectors of the transistors T1 and T2 are provided with resistors R2 and R3 having the same resistance value.

  The base and collector of the transistor T2 are connected. The collector of the transistor T1 is connected to the base of the transistor T3 as the feedback amplifier circuit. The emitter of the transistor T3 is set to the circuit ground potential VSS. The collector is provided with a load resistor R4. The collector output of the amplifying transistor T3 is fed back to the resistors R2 and R3 via the emitter-follower type transistor T4 so that the voltage drops across the resistors R2 and R3 are the same. That is, by making the resistance values of the resistors R2 and R3 equal, the transistors T1 and T2 are caused to flow the same constant current (ΔVbe / R1). A phase compensation capacitor C1 is provided between the base and collector which are the input and output of the amplification transistor T3.

  The operation of the band gap circuit is as follows. The bipolar transistor base-emitter voltage Vbe has a characteristic of having a negative voltage coefficient with respect to temperature. This is corrected by the voltage difference ΔVbe between the base and emitter voltages Vbe1 and Vbe2 having a positive voltage coefficient with respect to temperature, and a constant voltage independent of temperature can be obtained from the emitter of the feedback transistor T4. An emitter follower transistor T5 similar to the feedback transistor T4 is provided and a constant voltage is applied to the resistor R5 to form the reference current Io. The diode-connected P-channel MOSFET Q01 is provided at the collector of the transistor T5.

  FIG. 4 shows a circuit diagram of one embodiment of the circuit function blocks BLK1 and BLK2 of FIG. The external terminals P and N are connected to the bases of the differential transistors T10 and T11 via input resistors R11 and R12. Resistors R21 and R22 are connected between the bases of the differential transistors T10 and T11, and a bias voltage VB is supplied to the middle point thereof. The bias voltage VB is a midpoint voltage of the high level / low level supplied to the external terminals P and N. The emitters of the differential transistors T10 and T11 are connected in common, and a bias current source IO for supplying an operating current is provided. The bias current source IO is composed of the MOSFETs Q16 and Q26.

  In this embodiment, diode-connected P-channel MOSFETs Q40 and Q41 are provided between the collectors of the differential transistors T10 and T11 and the power supply voltage VDD. These P-channel MOSFETs Q40 and Q41 are respectively provided with P-channel MOSFETs Q42 and Q43 in the form of current mirrors. The drain current of the drain of the MOSFET Q42 is caused to flow through an N-channel MOSFET Q44 connected in a diode form. An N-channel MOSFET Q46 in the form of a current mirror is provided for this MOSFET Q44. The drains of the MOSFET Q46 and the MOSFET Q43 are connected to serve as an output terminal.

  The differential amplifier circuit outputs the signal voltage supplied from the external terminals P and N in the form of a current signal. That is, the differential transistors T10 and T11 determine the distribution ratio of the bias current source IO corresponding to the voltage difference between the external terminals P and N. The current mirror circuits Q40 and Q42 and Q41 and Q43 amplify the current corresponding to the element size ratio. The MOSFETs Q44 and Q46 have the same size, and perform an operation of converting the drain current of the MOSFET Q42 from a pushing current into a sinking current. As a result, a current corresponding to the difference in the current distribution ratio is output from the output terminal to which the drains of the MOSFETs Q43 and Q46 are connected.

  For example, when the external terminal P is higher in voltage than the external terminal N, the collector current of the transistor T10 becomes larger than the collector current of the transistor T11, and the current of the MOSFET Q43 is compared with the drain current of the MOSFET Q46 through the current mirror as described above. As the drain current becomes smaller, the gate voltage of the CMOS inverter circuit is lowered by the differential current. Thus, the CMOS inverter circuit forms a high level output signal OUT with the input signal at a low level. Conversely, when the external terminal N has a higher voltage than the external terminal P, the collector current of the transistor T11 becomes larger than the collector current of the transistor T10, and the drain current of the MOSFET Q46 becomes smaller than the drain current of the MOSFET Q43, and the CMOS inverter circuit. Is increased by the differential current. As a result, the CMOS inverter circuit forms a low level output signal OUT with the input signal at a high level.

  With this configuration, it is possible to directly convert a received signal having a small amplitude and an intermediate potential with respect to the power supply voltage VDD supplied to the differential amplifier circuit as described above into a CMOS level output signal OUT. Thereby, for example, the input circuit IB can be simplified and the signal transmission speed can be improved as compared with a case where a level shift circuit that converts a small amplitude such as an ECL level into a CMOS level is used. In the case where a sufficient current gain cannot be obtained with the differential amplifier circuit, a similar differential amplifier circuit may be provided in a tandem configuration to increase the gain by a two-stage amplifier configuration.

  When the input circuit is steadily operated as in the circuit function CKT2 of FIG. 2, the current source IO is connected to the emitters of the differential transistors T10 and T11 as shown in FIG. On the other hand, in order to stop the operation of the input circuit in the sleep state or the standby state as in the circuit function CKT1 of FIG. 2, the switches S1 to S2 are provided and turned off. . Alternatively, MOSFETs that short-circuit the gates and sources of the constant current MOSFETs Q16 and Q17 are provided, and the constant current MOSFETs Q16 and Q17 are turned off.

  FIG. 5 is a circuit diagram showing one embodiment of the output circuit of the semiconductor integrated circuit device according to the present invention. This embodiment is not particularly limited, but is directed to a CAN (Controller Area Network), which is a protocol that is currently a de facto standard among in-vehicle LANs. That is, the output circuit of this embodiment forms an output signal transmitted to the input circuit of FIG. The pair of external terminals P and N correspond to the external terminals in FIG. 4 and are connected to a two-wire signal wiring. A resistor R is connected between the two wires.

  One external terminal P is connected to the drain of the P-channel output MOSFET Q2. A diode D2 for preventing a backflow is provided between the source of the output MOSFET Q2 and the power supply voltage VDD. Further, n Zener diodes Z21 to Z2n connected in series are connected between the gate and drain of the output MOSFET Q2. The external terminal N is connected to the drain of the N-channel output MOSFET Q1 through a diode D1 for preventing backflow. N Zener diodes Z11 to Z1n connected in series are connected between the gate and drain of the output MOSFET Q1.

  A drive signal from the driver DRV is supplied to the gates of the MOSFETs Q1 and Q2. In the CAM output circuit, for example, when a logic 1 signal is output, the N-channel MOSFET Q1 and the P-channel MOSFET Q2 are turned on, and the resistor R connected between the external terminals P and N via a signal wiring is connected to the CAM output circuit. A current flows, a high level signal is sent to the external terminal P, and a low level signal is sent to the external terminal N. When a logic 0 signal is output, both the N-channel MOSFET Q1 and the P-channel MOSFET Q2 are turned off, and the external terminals P and N are set to the same potential by a resistor R connected through a signal wiring. Two potential states are output between the external terminals P and N, whether there is a potential difference generated by the resistor R or the same potential.

  Although not particularly limited, the external terminals P and N are connected to the input terminal of the input circuit IB. The input circuit IB includes the input circuit as shown in FIG. 4 and has two potential states, that is, whether the potential difference generated by the resistor R exists between the external terminals P and N or is the same potential. And the received signal of logic 1 or logic 0 is formed. The input circuit IB has an input offset smaller than the input voltage corresponding to the logic 1 output signal. Therefore, when the external terminals P and N are at the same potential corresponding to the received signal transmitted from another semiconductor integrated circuit device connected to the signal wiring, the input circuit IB has one level (logic) according to the offset. 0) output signal. The potential difference generated by the resistor R at the external terminals P and N cancels the input offset and reverses the input voltage of the differential amplifier circuit to form the other level (logic 1) output signal.

  In CAN, other wirings run in parallel with the above two signal wirings, and an excessive surge voltage is applied by electromagnetic induction or radio waves, so that the output MOSFETs Q1, Q2 and the input circuit IB are connected as described above. If so, the input element is destroyed. Therefore, in this embodiment, the output MOSFETs Q1 and Q2 are devised so as to have a protective function. That is, the Zener diodes Z11 to Z1n and Z21 to Z2n provided between the gates and drains of the MOSFETs Q1 and Q2 act as surge voltage detecting elements, and the MOSFET Q1 or Q2 is turned on to allow a surge current to flow. It is.

  In CAN, when the power supply voltage VDD is 5 V and a logic 1 signal is output as described later, the external terminal P is set to a high level such as 3.5 V, and the external terminal N is set to a low level such as 1.5 V. To do. When a logic 0 signal is output, the external terminals P and N are set to an intermediate level such as 2.5V. The surge voltage caused by electromagnetic induction or radio waves is allowed up to about ± 50 V so that the protection function does not operate. Since the output MOSFETs Q1 and Q2 and the input elements of the input circuit IB are guaranteed to have a breakdown voltage of about 80V, the Zener diodes Z11 to Z1n and Z21 to Z2n are turned on at 50V or more and 80V or less. To be.

  The zener diodes Z11 to Z1n and Z21 to Z2n are configured by connecting about ten zener diodes having a breakdown voltage of 5V to 6V in series as described above. For example, when ten Zener diodes having a breakdown voltage of about 5.6V are connected, when the gate voltage of the MOSFET Q2 is + 5V and in the off state, the external terminal P has a surge exceeding about −51V as described above. When a voltage is applied, the Zener diodes Z21 to Z2n are turned on to supply a negative voltage to the gate of the MOSFET Q2. As a result, the P-channel MOSFET Q2 is turned on, a current flows from the power supply voltage VDD toward the external terminal P to absorb the negative voltage, and the junction breakdown between the drain and the channel of the MOSFET Q2 or the input element of the input circuit IB Prevent the destruction of.

  Further, when a surge voltage exceeding about + 56V is applied to the external terminal N when the gate of the MOSFET Q1 is off at 0V, the Zener diodes Z11 to Z1n are turned on, and the gate of the MOSFET Q1 is turned on. Supply positive voltage. As a result, the N-channel MOSFET Q1 is turned on, a current flows from the external terminal N toward the circuit ground potential VSS to absorb the positive surge voltage, and the junction between the drain and the channel of the MOSFET Q1 is broken. The destruction of the input element of the circuit IB is prevented.

  Since the output MOSFETs Q1 and Q2 themselves are formed so as to flow a relatively large current, the current for absorbing the surge voltage as described above can sufficiently flow. Therefore, the Zener diodes Z11 to Z1n and Z21 to Z2n only need to transmit a gate voltage for turning on the MOSFETs Q1 and Q2, so that it is necessary to pass a large current like the Zener diode provided in Patent Document 1. There is no. Therefore, even if the semiconductor integrated circuit is formed, the chip area can be reduced. By incorporating the surge protection function in the semiconductor integrated circuit in this way, the number of external elements necessary for the semiconductor integrated circuit device having the CAN interface can be reduced.

  FIG. 6 shows a block diagram of an embodiment of an in-vehicle LAN in which the present invention is used. A plurality of devices DVC1 to DVCm having interface circuits each having an output circuit and an input circuit as shown in FIG. 1 are connected in parallel to two wirings arranged in parallel. The external terminals P are commonly connected to one of the two wires. The external terminals N are also commonly connected to the other of the two wirings.

  Although not particularly limited, a resistor R11 is connected to one end side between the two wirings, and two resistors R12 are connected in series to the other end side. The interconnection point of the resistor R12 is connected to one electrode of the capacitor C2 via the resistor R13. The other electrode of the capacitor C2 is given a circuit ground potential. In this embodiment, in the signal transmission operation as described above between the devices DVC1 to DVCm, a midpoint voltage (2.5 V) is formed by the resistor R12 and is held in the capacitor C2. As a result, when the P-channel MOSFETs Q1 and Q2 of the output circuit are both turned off, both the two wirings are stably maintained at a midpoint voltage such as 2.5V.

  FIG. 7 is a schematic element layout diagram of an embodiment of the semiconductor integrated circuit device according to the present invention. The semiconductor integrated circuit device of this embodiment has a bipolar transistor, a MOSFET, and a CMOS circuit like the reference current source BGR as shown in FIG. 3 and the input circuit as shown in FIG. 4, and is formed by a Bi-CMOS process. The In the PMOS section, a P-channel MOSFET Q2 constituting the output circuit as shown in FIG. 5 and the diode D2 are formed. In the NMOS portion, an N-channel MOSFET Q1 constituting the output circuit and the diode D1 are formed. IB1 is an input circuit that operates constantly. IB2 is an input circuit that operates during normal operation and is stopped when the low power mode is entered. These input circuits IB1 and IB2 correspond to the circuit function blocks BLK2 and BLK1 shown in FIGS. OSC is an oscillation circuit and corresponds to the circuit function block BLK2 in FIGS. BGR is a band gap reference circuit, and forms a reference voltage or a reference constant current. The OCD is an overcurrent detection circuit, which is stopped during operation in a steady operation and in a low power mode. The LOG is a logic circuit unit, which is composed of a CMOS circuit, forms a control signal for transmission / reception operation and transmission data, and processes reception data.

  Zener diodes Z21 to Z2n and Z11 to 1n for providing the MOSFETs Q2 and Q1 with the protection function are formed around the PMOS and NMOS portions. These Zener diodes Z21 to Z2n and Z11 to 1n are each provided with about ten pieces as described above. However, since the flowing current may be small as described above, the periphery of the PMOS unit and the NMOS unit may be reduced. It can be formed in a small area region. In the same figure, the portion marked with x in the square indicates an electrode connected to the external terminal.

  FIG. 8 is a schematic element cross-sectional view of one embodiment of a semiconductor integrated circuit according to the present invention. In the figure, a P-channel MOSFET (PMOS), an N-channel MOSFET (NMOS), and a bipolar transistor Bip-Tr are exemplarily shown. In the P channel MOSFET (PMOS), P + type sources and drains are formed in a deep well DNWL formed in a P type substrate (PSUB) and an N well NW separated by an element isolation region. A gate electrode made of FGP is formed on a well (substrate gate) sandwiched between the source and drain via a gate insulating film so as to straddle the source and drain. In an N-channel MOSFET (NMOS), N + type sources and drains are formed in a deep well DNWL formed in a P type substrate (PSUB) and a P well PW separated by an element isolation region. A gate electrode made of FGN is formed on a well (substrate gate) sandwiched between the source and drain via a gate insulating film so as to straddle the source and drain. When the semiconductor integrated circuit device is operated at 5V, 5V is supplied to the deep well DNWL and the N well NW, and 0V is applied to the P well PW and the substrate PSUB via the P + region and the well PW.

  In the bipolar transistor Bip-Tr, an Emily region made of N + is formed on the surface portion of the P-type base region. The collector is composed of an N− type region and NBL, and the collector electrode C is electrically connected to NBL via the N + region and CN. The emitter electrode is formed on the emily region made of N +, and the base electrode is electrically connected to the base region P so as to surround the emitter electrode. The bipolar transistor Bip-Tr can be used as an electrically independent element by an element isolation region formed so as to surround the bipolar transistor Bip-Tr and a PN junction with the substrate.

  Although the invention made by the inventor has been specifically described based on the above embodiment, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. For example, the circuit function block may be anything as long as it has a circuit portion that is operated by a constant current source. The specific configuration of the reference current source can take various embodiments. The present invention can be widely used in a semiconductor integrated circuit device having a plurality of circuit function blocks that operate based on a reference current formed by a reference current source.

1 is a schematic block diagram showing an embodiment of a semiconductor integrated circuit device according to the present invention. It is a schematic block diagram which shows another Example of the semiconductor integrated circuit device based on this invention. It is a circuit diagram which shows one Example of the reference current source which concerns on this invention. FIG. 3 is a circuit diagram showing an embodiment of the circuit function blocks BLK1, 2 of FIG. 1 is a circuit diagram showing one embodiment of an output circuit of a semiconductor integrated circuit device according to the present invention. FIG. It is a block diagram which shows one Example of the vehicle-mounted LAN with which this invention is used. 1 is a schematic element layout diagram showing one embodiment of a semiconductor integrated circuit device according to the present invention. 1 is a schematic device sectional view showing an embodiment of a semiconductor integrated circuit according to the present invention. It is a block diagram of the semiconductor integrated circuit device examined previously by the inventor of the present application.

Explanation of symbols

  BLK1 to BLK3: circuit functional block, CKT1 to CKT3: functional circuit, BA1, BA2: buffer amplifier, BGR: reference current source, Q1 to Q48: MOSFET, T1 to T11: transistor, R1 to R13: resistor, C1, C2 ... Capacitor, D1 to D4 ... Diode, Z11 to Z4n ... Zener diode, DRV ... Drive circuit, IB ... Input circuit, P, N ... External terminal, OSC ... Oscillator circuit, LOG ... Logic circuit, OCD ... Overcurrent protection circuit, DVC1 ~ DVCm ... device, PSUB ... P-type substrate, DMWL ... deep well, NW ... N well, PW ... P well.

Claims (9)

A reference current source for forming a constant current;
A plurality of circuit functional blocks that operate at a current corresponding to the constant current,
At least one of the plurality of circuit functional blocks is
A first transistor for passing a current corresponding to the constant current;
A second transistor in series with the first transistor and diode-connected;
A first current source transistor in current mirror connection with the second transistor;
And a first circuit that operates with a constant current from the first current source transistor. A reference current source for forming a constant current;
A plurality of circuit functional blocks that operate at a current corresponding to the constant current,
At least one of the plurality of circuit functional blocks is
A first transistor for passing a current corresponding to the constant current;
A second transistor in series with the first transistor and diode-connected;
A third transistor in current mirror connection with the second transistor;
A fourth transistor connected in series with the third transistor and diode-connected;
The semiconductor integrated circuit device, wherein the first current source transistor is current mirror connected to the fourth transistor. In claim 1,
Another one of the plurality of circuit functional blocks is:
A second current source transistor for supplying a current corresponding to the constant current;
And a second circuit that operates with a constant current from the second current source transistor. In claim 2,
Another one of the plurality of circuit functional blocks is:
A second current source transistor for supplying a current corresponding to the constant current;
And a second circuit that operates with a constant current from the second current source transistor. In claim 3,
The first circuit is a semiconductor integrated circuit device in which noise is generated in an input portion of the current source transistor when the constant current of the first current source transistor is intermittently supplied. In claim 4,
The semiconductor integrated circuit device, wherein the first circuit generates noise at an input portion of the current source transistor by an operation of the first circuit. In claim 1 or 2,
The reference current source is a semiconductor integrated circuit device composed of a band gap reference circuit. In claim 7,
The constant current formed by the reference current source is set to a minute current that cannot be absorbed when noise is transmitted to the wiring connecting the reference current source and the plurality of circuit function blocks by capacitive coupling. Semiconductor integrated circuit device. In claim 8,
The transistor is a MOSFET,
The band gap reference circuit is a semiconductor integrated circuit device that utilizes a difference in emitter current density between two bipolar transistors.

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