JP2007206798A - Program, method and device for generating control program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To support formation of a digitalized time sequence diagram and automatically generate a control program for signal control from the formed time sequence diagram. <P>SOLUTION: A sequence diagram formation support part 3a supports formation of the sequence diagram by providing a drawing part 2a to a user, and a code generation part 3d generates a source code by combining attribute and arrangement information of the drawing part contained in sequence diagram information 2c received from the sequence diagram formation support part 3a with external definition information 2d prepared separately from the sequence diagram information 2c. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a control program generation program for generating a control program for controlling a controlled device, a control program generation method, and a control program generation device, and more particularly to an electronic time sequence diagram that is the basis of control program generation. The present invention relates to a control program generation program, a control program generation method, and a control program generation apparatus capable of supporting efficient creation and automatically generating a control program corresponding to an electronic time sequence diagram.

  In recent years, as vehicle-mounted devices such as engines and automatic transmissions mounted on vehicles (for example, automobiles) have become more sophisticated, on-board computers such as ECUs (Electronic Control Units) that control the operation of these vehicle-mounted devices. The control program that runs on is also complicated.

  In the development process of such a control program, a time sequence diagram that defines the specification of the time change of signal values such as the engine speed, the fuel injection amount, and the gear stage number is widely used. In general, the program developer reads the signal value, the trigger of signal change, the action relationship of the signal change, etc. from the time sequence diagram, and then creates a control program that satisfies the conditions shown in the time sequence diagram. It is.

  However, since the work of creating a control program based on a diagram such as a time sequence diagram is complicated, the program development efficiency is poor and it is easy to induce mistakes of the program developer. For this reason, there has been proposed a method for generating a control program by generating a diagram such as a time sequence diagram on a computer having a graphical user interface and editing the digitized time sequence diagram.

  For example, Patent Document 1 relates to a method for generating an inspection program for inspecting a control program for plant control, and allows a user to input a signal value, a timing of signal value change, and a determination condition at an arbitrary point in a time sequence diagram. Thus, a technique for generating an inspection program is disclosed.

JP 2000-276224 A

  However, the technique of Patent Document 1 has a problem that the operation of generating the control program from the time sequence diagram is complicated and the work efficiency of the program developer is not good. Specifically, the only operation that can be performed on the time sequence diagram is an operation that designates an arbitrary time point, and the specific contents of the control program had to be set on a setting screen displayed as a separate window. . For this reason, the program developer has to perform work while comparing the display screen of the time sequence diagram and the setting screen.

  By the way, when generating a control program based on an electronic time sequence diagram, it is necessary to generate a control program that accurately represents the contents of the time sequence diagram while eliminating the ambiguity of the time sequence diagram. However, at present, an automatic generation method of such a control program has not been established.

  Therefore, a control program generation method for automatically generating a control program corresponding to an electronic time sequence diagram is provided while supporting efficient creation of an electronic time sequence diagram that is the basis for generating a control program. How to achieve it is a big issue.

  The present invention has been made to solve the above-described problems caused by the prior art, and can support efficient creation of an electronic time sequence diagram that is the basis for generating a control program. It is an object of the present invention to provide a control program generation program, a control program generation method, and a control program generation device capable of automatically generating a control program corresponding to the converted time sequence diagram.

  In order to solve the above-described problems and achieve the object, the invention according to claim 1 is a control program generation program for generating a control program for controlling a controlled device, and is used for controlling the controlled device. When a user creates a time sequence diagram representing a time change of a plurality of signals to be generated, the user can arrange the relationship between signals used for control of the controlled device by arranging logic symbols in the time sequence diagram. An input procedure to be input and a control program generation procedure for generating the control program based on attributes and arrangement information of the logic symbols arranged in the time sequence diagram received in the input procedure To do.

  Further, in the invention according to claim 2, in the above invention, the control program generation procedure develops the relationship between signals defined by the logic symbols arranged in the time sequence diagram into the control program. In this case, the control program reflecting the relationship between the signals is generated in accordance with the drawing order of the signals in which the logic symbols are arranged in the time sequence diagram.

  According to a third aspect of the present invention, in the above invention, the control program generation procedure is a development that represents a development order in which a relationship between signals is developed in the control program in the logic symbols arranged in the time sequence diagram. When the order information is included, the control program reflecting the relationship between the signals is generated by giving priority to the development order information over the drawing order of the signal in which the logic symbols are arranged in the time sequence diagram. It is characterized by.

  According to a fourth aspect of the present invention, in the above invention, the input procedure allows input of a boundary that divides the time sequence diagram into a predetermined number of partial diagrams, and the control program generation procedure depends on the boundary. The control program is generated for each divided partial view.

  The invention according to claim 5 is the above invention, wherein the input procedure allows input of a plurality of time sequence diagrams and relationship information between the time sequence diagrams, and the control program generation procedure includes: The control program is generated after combining the time sequence diagrams based on the relationship information.

  In the invention according to claim 6, in the above invention, the control program generation procedure develops the relationship between signals defined by the logic symbols arranged in the time sequence diagram to the control program. In the case where there is a delay time from when a specific signal among the signals having the relationship changes until another signal changes, the control program reflecting the delay time is generated. And

  In the invention according to claim 7, in the above invention, the input procedure includes a logic symbol capable of directly inputting a program logic as the logic symbol, and the logic symbol is included in the time sequence diagram. When displayed, the program logic directly input by the user is displayed as a part of the logic symbol.

  In the invention according to claim 8, in the above invention, the control program generation procedure develops the relationship between signals defined by the logic symbols arranged in the time sequence diagram into the control program. In this case, the signal control logic representing the change of each signal and the time control logic for calling the signal control logic at a predetermined timing are generated separately.

  In the invention according to claim 9, in the above invention, the computer further executes a definition data registration procedure for registering definition data defining the attribute of the logic symbol in a storage unit, and the control program generation procedure includes: The control program is generated after associating the arrangement information of the logic symbols included in the time sequence diagram with the definition data registered by the definition data registration procedure.

  In the invention according to claim 10, in the above invention, the computer further executes a pattern extraction procedure for extracting a common signal control pattern from one or a plurality of the time sequence diagrams received by the input procedure, and the control is performed. The program generation procedure is characterized in that the control program using the common logic is generated after the signal control pattern extracted by the pattern extraction procedure is converted into a common logic.

  The invention according to claim 11 is characterized in that, in the above-mentioned invention, the pattern extraction procedure extracts the combination of the logic symbols representing the operational relationship of the signals as the common signal control pattern.

  According to a twelfth aspect of the present invention, in the above invention, when the input procedure determines that there is a non-input part in a time sequence diagram based on a positional relationship of the logic symbols arranged by a user. The input of the time sequence diagram is complemented based on the positional relationship of the symbols.

  In the invention according to claim 13, in the above invention, the control program generation procedure develops the relationship between signals defined by the logic symbols arranged in the time sequence diagram to the control program. In this case, the control program is generated by using a logic that constitutes the control program and a programming rule that represents a rule for securing a data storage area.

  According to a fourteenth aspect of the present invention, there is provided a control program generating device for generating a control program for controlling a controlled device, wherein the time sequence represents a time change of a plurality of signals used for controlling the controlled device. When the user creates a diagram, the input means accepts the relationship between signals used for the control of the controlled device by placing a logic symbol in the time sequence diagram, and the input means accepts the diagram. Control program generation means for generating the control program based on the attribute and arrangement information of the logic symbols arranged in the time sequence diagram.

  According to a fifteenth aspect of the present invention, there is provided a control program generation method for generating a control program for controlling a controlled device, wherein the time sequence represents a time change of a plurality of signals used for controlling the controlled device. When a user creates a diagram, an input process that allows a user to input a relationship between signals used for control of the controlled device by arranging logic symbols in the time sequence diagram, and is accepted in the input process. And a control program generating step for generating the control program based on the attribute and arrangement information of the logic symbols arranged in the time sequence diagram.

  According to the invention according to claim 1, 14 or 15, it is used for controlling the controlled device when the user creates a time sequence diagram showing the time change of the plurality of signals used for controlling the controlled device. The configuration is such that the relationship between signals is input by the user by arranging logic symbols in the time sequence diagram, and the control program is generated based on the attributes and arrangement information of the logic symbols arranged in the received time sequence diagram. Therefore, by letting the user perform intuitive sequence diagram creation work, it is possible to support the efficient creation of an electronic time sequence diagram that is the basis for generating a control program, and the digitized time There is an effect that a control program corresponding to the sequence diagram can be automatically generated.

  According to the second aspect of the present invention, when the relationship between the signals defined by the logic symbols arranged in the time sequence diagram is expanded to the control program, the time of the signal having the logic symbols arranged therein is expanded. Since it is configured to generate a control program that reflects the relationship between signals according to the drawing order in the sequence diagram, it eliminates the ambiguity of the time sequence diagram without letting the user specify the development order and makes the generation logic unique It is possible to determine the quality, and the quality of the generation logic can be improved.

  According to the invention of claim 3, when the logic symbols arranged in the time sequence diagram include expansion order information representing the expansion order for expanding the relationship between signals to the control program, the logic symbols are Since the control program reflecting the relationship between the signals is generated with priority given to the development order information over the drawing order of the arranged signals in the time sequence diagram, the time can be set by allowing the user to directly specify the development order. The ambiguity of the sequence diagram can be eliminated and the generation logic can be uniquely determined, and the quality of the generation logic can be improved.

  Further, according to the invention according to claim 4, since the input of the boundary for dividing the time sequence diagram into a predetermined number of partial diagrams is allowed, and the control program is generated for each partial diagram divided by the boundary, The control program can be easily modularized, and the time sequence diagram and the diversion of the control program can be promoted.

  According to the invention of claim 5, the control program allows input of a plurality of time sequence diagrams and relationship information between the time sequence diagrams, and combines the time sequence diagrams based on the relationship information. Since the time sequence diagrams developed in a distributed manner can be easily integrated, each time sequence diagram can be made large enough to maintain visibility.

  According to the invention of claim 6, when the relationship between the signals defined by the logic symbols arranged in the time sequence diagram is expanded to the control program, a specific signal among the signals having the relationship When there is a delay time from when the signal changes until another signal changes, a control program reflecting this delay time is generated, so the change timing of a specific signal and the relationship between this signal and Even if there is a shift in the change timing of the signal that has the control program, it is possible to easily generate the control program.

  According to the seventh aspect of the present invention, the logic symbol capable of directly inputting the program logic is provided as the logic symbol, and the logic symbol is directly displayed by the user when displayed on the time sequence diagram. Since the input program logic is configured to be displayed as a part of the logic symbol, the user can understand the logic represented in the time sequence diagram only by looking at the time sequence diagram.

  According to the eighth aspect of the invention, when the relationship between the signals defined by the logic symbols arranged in the time sequence diagram is developed into the control program, the signal control signal indicating the change of each signal is shown. Since the logic and the time control logic that calls the signal control logic at a predetermined timing are generated separately, the signal control logic can be easily made into a common module and the generated logic can be called By clarifying the relationship, the quality of the generation logic can be improved.

  According to the invention of claim 9, the definition data defining the logic symbol attributes is registered in the storage unit, and the logic symbol arrangement information included in the time sequence diagram is associated with the registered definition data. Since the control program is generated by the system, the creation of the time sequence diagram can be made more efficient, and the generated control program can be made compatible with multiple programming languages, or different control programs can be created from the same time sequence diagram. As a result, the control program can be generated flexibly.

  According to the invention of claim 10, a common signal control pattern is extracted from one or more received time sequence diagrams, and the extracted signal control pattern is converted into common logic, and then control using the common logic is performed. Since the program is generated, the quality of the generated control program can be improved by automatically modularizing the generated control program.

  According to the eleventh aspect of the present invention, since the combination of logic symbols representing the operational relationship of signals is extracted as a common signal control pattern, common patterns appearing at a plurality of locations in the sequence diagram are extracted. Thus, by prompting the use, it is possible to improve the efficiency of the sequence diagram creation work and improve the quality of the generated control program.

  According to the twelfth aspect of the present invention, when it is determined that there is an uninput part in the time sequence diagram from the positional relationship of the logic symbols arranged by the user, the time sequence diagram is based on the positional relationship of the logic symbols. Therefore, the sequence diagram creation procedure can be simplified.

  According to the invention of claim 13, when the relationship between signals defined by the logic symbols arranged in the time sequence diagram is expanded to the control program, the logic and data storage areas constituting the control program Since the configuration is such that the control program is generated using the programming rules that represent the securing rules, the reliability of the generated logic can be improved, and the memory area used by the generated control program can be efficiently reduced. There is an effect that can be done.

  Exemplary embodiments of a control program generation method according to the present invention will be described below in detail with reference to the accompanying drawings. In the following embodiments, a case will be described in which a control program generating apparatus is configured by installing a dedicated program in a general-purpose computer such as a personal computer (PC) or a workstation (WS). In the following embodiments, the above time sequence diagram is simply referred to as a “sequence diagram”.

  First, the outline and features of the control program generation method according to the present invention will be described with reference to FIG. FIG. 1 is a diagram showing an outline and features of a control program generation method according to the present invention. The “control program generation tool” shown in the figure is a control program generation program to which the control program generation method according to the present invention is applied, and exhibits a function when installed in a computer such as a personal computer (PC).

  As shown in FIG. 1, the control program generation tool displays a sequence diagram input screen on a display device such as a display device and displays a palette or the like representing a list of drawing parts to the user. "Is provided (see (1) in FIG. 1). Here, the “drawing component” refers to a line such as a straight line or a curve representing the passage of time of various signals, and a symbol such as a dependency relationship between each signal and a determination condition.

  The user selects a drawing part provided from the control program generation tool as appropriate, and creates a sequence diagram by placing it on the sequence diagram input screen or inputting an attribute value ((2) in FIG. 1). reference). In the sequence diagram shown in the sequence diagram input screen of FIG. 1, time is plotted on the horizontal axis and signal values related to each signal are arranged for each signal on the vertical axis. Further, in this sequence diagram, a signal that takes two values “ON” and “OFF” is illustrated, but the signal is not limited to a signal that takes two values.

  The control program generation tool reads the sequence diagram created in this way (see (3) in FIG. 1), and acquires the arrangement information and attribute values of each drawing component arranged in the sequence diagram ((( 4)). A control program (for example, source code) is generated by synthesizing “external definition information” prepared separately from the sequence diagram and the information acquired in (4) of FIG. Details of the external definition information used in (5) of FIG. 1 will be described later with reference to FIG.

  The source code shown in FIG. 1 is a source code in C language which is one of programming languages. This source code corresponds to the sequence diagram shown in FIG. Specifically, the control content is described to turn off the signal value of the signal B on condition that the signal value of the signal A changes from OFF to ON at time T [n] in the sequence diagram.

  As described above, in the control program generation method according to the present invention, the drawing parts for creating the sequence diagram representing the time change of each signal value are provided to the user, and the drawing parts arranged in the created sequence diagram are provided. It is decided to synthesize the location information and attribute values of the external definition information and the external definition information representing additional conditions for generating the source code. Therefore, it is possible to support efficient creation of an electronic time sequence diagram that is a basis for generating a control program and to automatically generate a control program corresponding to the electronic time sequence diagram.

  Although FIG. 1 shows the case where the source code itself is generated as the control program, the present invention is not limited to this, and an intermediate product for generating the source code (for example, meta information indicating the source code generation rule) is generated. In other words, the control program may be generated by passing the intermediate product to an external source code generation program. Further, FIG. 1 shows the case where the source code in C language is generated, but it is also possible to prepare a plurality of programming languages for the generated source code and let the user select it.

  In the following, a case will be described in which a control program generation apparatus is configured by installing a dedicated program to which a control program generation method according to the present invention is applied in a general-purpose computer such as a personal computer (PC) or a workstation (WS). To do. In the following description, the control program generation device generates a vehicle control program, particularly an engine or transmission control program.

  The control program generated by the control program generation device is used when determining the output signal based on the input signal, or when determining the output signal without using the input signal, or when the control program is installed. It can also be used when determining the internal state of the device based on the input signal.

  FIG. 2 is a block diagram illustrating a configuration of the control program generation device 1 according to the present embodiment. As shown in FIG. 1, the control program generation device 1 includes a storage unit 2, a control unit 3, and an input / output unit 4. The control unit 3 is a processing unit (program) corresponding to the control program generation tool shown in FIG.

  As shown in FIG. 2, the storage unit 2 stores drawing parts 2a, common pattern information 2b, sequence diagram information 2c, external definition information 2d, and common code information 2e. The sequence diagram creation support unit 3a, the pattern extraction unit 3b, the drawing component registration unit 3c, the code generation unit 3d, the common code extraction unit 3e, and the external definition information operation unit 3f are further provided.

  The storage unit 2 is a storage unit composed of a storage device such as a magnetic disk device or a disk array device. The drawing component 2a, common pattern information 2b, sequence diagram information 2c, external definition information 2d, and common code information 2e is stored.

  The drawing component 2a is a symbol such as a line such as a straight line or a curve that represents the passage of time of various signals, a dependency relationship between each signal, or a judgment condition, which is used to create a sequence diagram. A person can also create a new drawing component 2a.

  The drawing component 2a can be set with attributes such as information related to the other drawing component 2a and the order in which the code generation unit 3d develops the drawing component 2a into the control program. When the development order is not designated, the code generation unit 3d causes each drawing component in the drawing sequence in the time sequence diagram of the signal in which the drawing component 2a is arranged, in the direction from the top to the bottom, the left to the right in the sequence diagram. 2a will be read.

  For example, when signals A, B, and C are drawn in the order of B, A, and C from the top to the bottom in the time sequence diagram, the drawing component 2a arranged in the B signal is preferentially read, and the time When the sequence diagram shows a later time as it goes to the right, the drawing component positioned on the left side of the B signal is read preferentially.

  Here, an example of the drawing component 2a will be described with reference to FIGS. 3 and 4 are diagrams showing an example 1 and 2 of the drawing component 2a, respectively. FIGS. 5 and 6 are diagrams showing an example 1 and 2 of the arrangement of the drawing component 2a in the sequence diagram, respectively. It is.

  A drawing component 2a used for designating the signal value of each signal is shown at 103a in FIG. This 103a is used not only to specify an update value of a signal but also to specify a numerical value of a determination condition. For example, values such as “0”, “= 0”, and “A + 1” can be input in the rectangle 103a, and the input value is displayed on 103a and held as an attribute value. Become.

  Reference numerals 103b and 103c in FIG. 3 indicate marks (symbols) for threshold determination, where 103b indicates "~" and 103c indicates "~". When the code generation unit 3d described later converts these symbols into C language, 103b is converted to “> =” and 103c is converted to “<=”. Further, the black circles shown in 103b and 103c indicate that the value specified in the rectangle is included, and the left and right positions of the arrows adjacent to the black circle can be changed as appropriate according to the arrangement state.

  103d and 103e in FIG. 3 are marks (symbols) for threshold determination, and 103d indicates “greater than” and 103e indicates “less than”. When the code generation unit 3d described later converts these symbols into C language, 103d is converted to “>” and 103e is converted to “<”. The white circles indicated by 103d and 103e indicate that the specified value is not included in the rectangle, and the left and right positions of the arrows adjacent to the white circle can be changed as appropriate according to the arrangement state.

  103f and 103g in FIG. 3 are marks (symbols) for performing a match determination. 103f is used for a signal other than a binary signal (flag), and 103g is used for a binary signal (flag). . When these codes are converted into C language by the code generation unit 3d described later, they are converted to “==”. Also, the value specified in the rectangle 103f is used as the right side value of “==”.

  103h and 103i in FIG. 3 are marks (symbols) for determining the mismatch, 103h is used for signals other than binary signals (flags), and 103i is used for binary signals (flags). . In addition, when the code generation unit 3d described later converts these symbols into the C language, it is converted into “! =”. Also, the value specified in the 103h rectangle is used as the right side value of "! =".

  103j and 103k in FIG. 3 are marks (symbols) for performing a logical operation. 103j represents an AND condition, and 103k represents an OR condition. In addition, when the code generation unit 3d described later converts these symbols into C language, 103j is converted into “&&”, and 103k is converted into “||”.

  104a and 104b in FIG. 4 are marks (symbols) for performing an assignment operation. 104a is used for signals other than binary signals (flags), and 104b is used for binary signals (flags). . In addition, when the code generation unit 3d described later converts these symbols into the C language, the symbols are converted to “=”. The value designated in the rectangle 104a is used as the right side value of “=”.

  In FIG. 4, 104c, 104d, and 104e are marks (symbols) that indicate the occurrence timing of the event. 104c is used for an external event, and 104d and 104e are used for an event related to a timer. Note that the threshold value designated in the rectangle 104d is a timer timeout value. If 104e is used, a plurality of threshold values (threshold values # 1 and # 2 in the figure) can be designated.

  A mark (symbol) for designating a function directly is shown at 104f in FIG. 4, and a function name or the like is designated directly in a rectangle. When the code generation unit 3d described later converts this symbol into C language, the function name specified in the rectangle 104f is expanded as it is in the source code.

  Reference numeral 104g in FIG. 4 denotes a mark (symbol) representing loop processing such as repetition, and a loop start condition, a loop immediate end (break) condition, and a loop end condition can be designated. In addition, when the code generation unit 3d described later converts this symbol into C language, 104g is converted into "while ()" or "do {} while ()".

  104h and 104i in FIG. 4 are marks (symbols) representing comments, which can be displayed in the sequence diagram by specifying “display / hide comment” as an attribute value of other symbols. Or not to display. In addition, when the code generation unit 3d described later converts these symbols into the C language, the content of the comment is expanded as “/ * to * /” on the right side of each command statement in the source code. become.

  Reference numeral 104j in FIG. 4 denotes a mark (symbol) representing an auxiliary line used for assisting understanding of the sequence diagram. This symbol is ignored by the code generator 3d described later and is not reflected in the source code. In this way, by preparing marks (symbols) that are not reflected in the source code, the sequence diagram can be efficiently drawn and the readability of the sequence diagram can be improved.

  Next, an arrangement example of each drawing component 2a described with reference to FIGS. 3 and 4 will be described with reference to FIGS. 5 and 6, “No” representing the number of each example, “Combination example” representing the combination and arrangement example of the drawing component 2a, and “Logic” representing the source code example generated by the code generation unit 3d. Generated image ".

  In No. 1 of FIG. 5, 103a, 103g, 103k, and 104a are used among the drawing parts 2a shown in FIGS. 3 and 4, and the signal C is changed according to the states of A and B that are binary signals (flags). It shows the case of changing the value. Specifically, when either flag A or flag B is ON, it is specified that a value obtained by subtracting D from the value of variable C is set as the value of new variable C.

  When the code generation unit 3d detects a processing pattern indicated by No1 in FIG. 5, that is, a pattern for updating a specific signal value when any of a plurality of conditions regarding the signal value is satisfied, for example, As shown in the figure, a code for updating the variable C is generated based on the condition satisfied by the flag A or the flag B.

  In No. 2 in FIG. 5, if 103g, 104b and 104d are used among the drawing parts 2a shown in FIGS. 3 and 4, and the flag C is OFF when an external event occurs, the flag C is turned ON and the counter D Is specified to start counting after initializing to 0.

  The code generation unit 3d displays the processing pattern shown in No. 2 in FIG. 5, that is, the pattern for updating the signal value and starting the counter if the signal value satisfies a predetermined condition when an external event occurs. If detected, for example, as shown in the figure, a condition code indicating the occurrence of the event A and a code for updating the flag C and the counter D when the event A occurs are generated.

  In No. 3 of FIG. 5, 103 a, 103 g, 104 b, and 104 d are used among the drawing parts 2 a shown in FIGS. 3 and 4, and if the flag A is ON at the end of the counter B count, the value of the variable C is set to D Is specified to be the value of the new variable C.

  When the code generation unit 3d detects the processing pattern indicated by No. 3 in FIG. 5, that is, the count end and a pattern for updating a specific signal value when a predetermined condition is satisfied for the signal value. For example, as shown in the figure, a code for updating the variable C is generated based on the condition satisfied by the counter B and the flag A.

  No. 4 in FIG. 5 shows an example in which 103e, 103j, 103k, and 104a are used among the drawing components 2a shown in FIGS. 3 and 4 and specific signal values are corrected one after another based on a plurality of conditions. ing. Specifically, it is specified that the value of the variable H is changed (corrected) by a combination of the conditions set in the flags A to E and the variable F.

  If the code generation unit 3d detects the processing pattern indicated by No. 4 in FIG. 5, that is, a pattern that corrects the value of the same variable according to a plurality of conditions, for example, as shown in FIG. A code for correcting the variable H based on the condition satisfied by the flag E and the variable F is generated.

  In No. 5 of FIG. 6, an example is shown in which 103 g, 103 j, 104 a, and 104 b of the drawing component 2 a shown in FIGS. 3 and 4 are used and a plurality of signal values are updated based on changes in specific signal values. Yes. Specifically, it is specified that the value of the variable B is updated to C, the value of the variable D is updated to E, and the flag F is updated to OFF with the flag A changing from OFF to ON.

  If the code generation unit 3d detects the processing pattern indicated by No. 5 in FIG. 5, that is, a pattern in which a plurality of signal values are updated simultaneously when a specific signal state changes, for example, the flag A is satisfied. Based on the determined condition, a code for updating the variable B, the variable D, and the flag F is generated.

  In No. 6 of FIG. 6, 103d, 103g, and 104a are used among the drawing parts 2a shown in FIGS. 3 and 4, and when the specific signal value is increased to reach a predetermined upper limit value, this upper limit value is maintained. An example is shown. Specifically, if both the flag A and the flag B are ON at a predetermined timing, the flag B is turned OFF and the value of the variable C is increased by D. If the value of the variable C reaches E For example, the variable C is designated as E.

  If the code generation unit 3d detects the processing pattern indicated by No. 6 in FIG. 5, that is, a pattern that increases a specific signal value and guards with an upper limit value, for example, the variable C is increased by D. When the variable C reaches E, a code is generated to stop the increase.

  No. 7 in FIG. 6 shows an example in which 103a and 103f of the drawing component 2a shown in FIGS. 3 and 4 are used and the signal values represented by the array are simultaneously updated when the same condition is satisfied. Specifically, it specifies that the signal value is updated to C if each signal value matches B.

  When the code generation unit 3d detects the processing pattern indicated by No. 7 in FIG. 5, that is, a pattern in which the signals represented as an array are simultaneously updated when the same condition is satisfied, for example, the array A [n ] To generate a code to loop the update.

  No. 8 in FIG. 6 shows an example in which 103b and 104a are used in the drawing component 2a shown in FIGS. 3 and 4 and the update process of each signal value is loop-processed. Specifically, while the value of variable A is greater than B, the value obtained by subtracting E from the value of variable D is substituted for variable C, and the value of variable C is set to variable D while subtracting the value of variable A by one. Is assigned. Then, it is specified that the loop process is terminated on condition that the value of the variable C becomes F or more.

  When the code generation unit 3d detects the processing pattern indicated by No. 8 in FIG. 5, that is, a pattern that loops the unconditional update process and the update process with condition determination, for example, the variable C is updated. With respect to, a code for generating a loop process is generated after a condition is added to the update of the variable A and the variable B without adding a condition.

  In this way, by preparing various drawing components 2a, it is possible to efficiently create a sequence diagram, and rules necessary for generating source code while allowing the creation of various types of sequence diagrams. Sexuality can be secured. Furthermore, it is possible not only to prepare the drawing component 2a in advance, but also to add a new drawing component 2a obtained by combining the drawing components 2a prepared in advance. Also, creating a new drawing component by combining the drawing component 2a is referred to as "macro-ization". Note that an example of macro conversion will be described later with reference to FIG.

  Returning to the description of FIG. 2, the description of the information stored in the storage unit 2 will be continued. The common pattern information 2b is information representing the common pattern extracted from the sequence diagram by the pattern extraction unit 3b. By providing the common pattern to the user in the same manner as the drawing component 2a, the sequence diagram creation efficiency is improved. Can do. An example of such “pattern extraction” will be described later with reference to FIG.

  The sequence diagram information 2c is information relating to the sequence diagram created by the sequence diagram creation support unit 3a. Specifically, the sequence diagram information 2c is information including the arrangement position of each drawing component 2a arranged in the sequence diagram and the designated attribute value. Note that the code generation unit 3d described later generates a code such as a source code based on the sequence diagram information 2c.

  The external definition information 2d is additional information for supplementing the sequence diagram, and the code generation unit 3d described later synthesizes the sequence diagram information 2c and the external definition information 2d to generate a code such as a source code. Is generated.

  For example, even if the same sequence diagram is created, if different external definition information 2d is prepared, source codes having different determination conditions can be generated. Further, by using this external definition information 2d, it becomes easy to generate a code corresponding to a plurality of programming languages. Further, by including information supplementing the drawing component 2a in the external definition information 2d, it is possible to reduce the input operation when creating the sequence diagram. A synthesis example of the sequence diagram information 2c and the external definition information 2d will be described later with reference to FIG.

  Further, in this embodiment, an example in which the external definition information 2d is provided is shown, but it is possible to include all information necessary for code generation in the sequence diagram without providing the external definition information 2d. Good.

  The common code information 2e is information regarding a common code (for example, a common function) extracted from codes generated by a code generation unit 3d described later. By using this common code information 2e, it is possible to modularize the code, and when there is a need to change the common code included in the common code information 2e, the common code is simply modified. It will be possible to modify all the code that uses.

  The control unit 3 is a processing unit corresponding to the control program generation tool shown in FIG. 1, and is shared by the sequence diagram creation support unit 3a, the pattern extraction unit 3b, the drawing component registration unit 3c, and the code generation unit 3d. A code extraction unit 3e and an external definition information operation unit 3f are provided.

  The sequence diagram creation support unit 3a displays a sequence diagram input screen including a palette for selecting the drawing component 2a and the common pattern information 2b in the storage unit 2 on the display 4b through the input / output unit 4 and uses them. The creation of the sequence diagram is supported by accepting the placement operation and input operation of the drawing component 2a by the user from the input / output means 4a such as a keyboard or a mouse via the input / output unit 4, and information on the completed sequence diagram is provided as sequence diagram information. 2c is a processing unit that performs processing of registering in the storage unit 2 as 2c. The sequence diagram creation support unit 3a is a processing unit that accepts a sequence diagram being created or a sequence diagram that has been created from a portable medium reader of the input / output unit 4 and supports editing processing of these sequence diagrams. is there.

  The pattern extraction unit 3b searches the sequence diagram being created by the sequence diagram creation support unit 3a by using a user instruction or a timer at a predetermined interval as a trigger, and uses a pattern matching technique or the like in common in the sequence diagram. This is a processing unit that performs processing for registering information obtained as a result of extracting the pattern used in the storage unit 2 as common pattern information 2b. The drawing component registration unit 3c is a processing unit that performs a process of registering a new drawing component 2a composed of a combination of a plurality of drawing components 2a in the storage unit 2.

  The code generation unit 3d reads the sequence diagram information 2c registered by the sequence creation support unit 3a and the external definition information 2d registered by the external definition information operation unit 3f, which will be described later, from the storage unit 2, and stores these information (2c And 2d) is a processing unit that performs processing for generating code such as source code. The code generation unit 3d reads the common code information 2e registered by the common code extraction unit 3e described later from the storage unit 2, and generates a code reflecting a common function included in the common code information 2e It is also a department. Details of the processing performed by the code generation unit 3d will be described later with reference to FIGS.

  Further, when the code generation unit 3d develops the relationship between the signals represented by the drawing component 2a into a code, for example, each drawing component in the direction from the top to the bottom and from the left to the bottom of the sequence diagram. 2a will be read. If an attribute indicating the development order is set in the drawing component 2a, each drawing component 2a is read with priority on the development order.

  The common code extraction unit 3e extracts a common code (for example, a common function) from the codes generated by the code generation unit 3d by using a pattern matching technique and the like, and information on the extracted common code is used as the common code information 2e. As a processing unit that performs processing to be registered in the storage unit 2.

  The external definition information operation unit 3 f is a processing unit that performs processing such as registration, change, update, and deletion of the external definition information 2 d described above based on an instruction received via the input / output unit 4. As described above, by operating the external definition information 2d, the efficiency of code generation can be improved, and in particular, a uniform code is generated when a plurality of users share the work. be able to.

  The input / output unit 4 is an output device such as a display device, an input device such as a keyboard or a mouse or a portable medium reader, or a communication device such as a LAN (Local Area Network) board. The sequence diagram input by the sequence diagram creation support unit 3a Processing such as displaying a screen, receiving an input of a sequence diagram, outputting a code generated by the code generation unit 3d to another personal computer (PC) on the network, and receiving an editing operation on external definition information Do it.

  Next, an example of a sequence diagram created by the sequence diagram creation support unit 3a shown in FIG. 2 and an example of a source code created by the code generation unit 3d will be described with reference to FIGS. FIG. 7 is a diagram showing an example of a sequence diagram, and FIGS. 8 and 9 are diagrams showing an example 1 and 2 of control programs generated from the sequence diagram shown in FIG. 7, respectively.

  In FIG. 7, the operational relationship of each signal such as the counter_1, the flag_1, and the flag_2, the time change, and the like are described using the drawing component 2a illustrated in FIGS. FIG. 7 shows a case in which each signal value is changed based on two external events of event_1 and event_2.

  Note that (1) to (20) shown in FIG. 7 correspond to (1) to (20) of the source code shown in FIGS. FIG. 8 shows the source code corresponding to the part related to event_1 in FIG. 7, and FIG. 9 shows the source code corresponding to the part related to event_2.

  In the sequence diagram of FIG. 7, the horizontal axis indicates time (assuming time flows from left to right), and the vertical axis indicates each signal. Each signal on the vertical axis includes a signal name (for example, “counter_1”, a variable name corresponding to the signal (for example, cnt_1), an upper limit value (for example, “4194 (ms)” representing the maximum value), a lower limit value, and the like. Information on a value (for example, “0 (ms)” representing the minimum value) is included, and the upper limit value and the lower limit value can specify “ON” and “OFF” for the flag.

  Next, a control program generated based on the sequence diagram of FIG. 7 will be described. As shown in FIG. 8, two functions, init_proc and cycle_proc, are generated as functions corresponding to event_1 in FIG. This init_proc describes an initialization process performed when event_1 occurs, and cycle_proc describes a recurring process that is repeatedly executed at predetermined intervals after the execution of init_proc.

  As shown in FIG. 9, two functions, init_proc and cycle_proc, are generated as functions corresponding to event_2 in FIG. The execution timing of these functions is the same as that in FIG.

  Next, an outline of a control program generation procedure performed in the control program generation device 1 shown in FIG. 2 will be described with reference to FIG. FIG. 10 is a flowchart showing an outline of a control program generation procedure. As shown in the figure, the sequence diagram creation support unit 3a displays an input screen on which the drawing component 2a and the common pattern information 2b can be used on the display device of the input / output unit 4 (step S101). A sequence diagram input by the user is accepted via an input device such as a keyboard or mouse (step S102).

  When the creation of the sequence diagram is completed and an instruction from the user is received via an input device such as a keyboard or a mouse of the input / output unit 4, the sequence diagram creation support unit 3a registers the sequence diagram information 2c in the storage unit 2. Subsequently, the code generation unit 3d reads the sequence diagram information 2c from the storage unit 2, and acquires position information, attribute information, and the like of the drawing component included in the sequence diagram information 2c (step S103).

  Then, the sequence diagram creation support unit 3a combines the information acquired in step S103 with the external definition information 2d read from the storage unit 2 (step S104), and generates a source code (step S105). Subsequently, the sequence diagram creation support unit 3a outputs the source code created via the LAN board of the input / output unit 4 (step S106) and ends the process.

  Hereinafter, the contents of the code generation process in the code generation unit 3d shown in FIG. 2 will be described in more detail. FIG. 11 is a diagram illustrating an example when the determination portion is designated by a logic symbol (see FIGS. 3 and 4). FIG. 11 shows a state in which different source codes are generated by properly using logic symbols having different meanings.

  11a in FIG. 11 is an example in which an arrow symbol is arranged in the determination part, 11a-1 represents a sequence diagram in which the arrow symbol is arranged, and 11a-2 represents a source code generated based on 11a-1. . As shown in 11a-1, at time “4”, the signal A is changed from ON to OFF, and an arrow symbol is arranged in the direction from ON to OFF. Similarly, at time “4”, the signal B changes from ON to OFF. In this case, source code is generated to turn off the value of the signal B on condition that “the previous value A ′ of the signal A is ON and the latest value A of the signal A is OFF”. .

  11b in FIG. 11 is an example in which a black circle symbol is arranged in the determination part, 11b-1 represents a sequence diagram in which the black circle symbol is arranged, and 11b-2 represents a source code generated based on 11b-1. ing. As shown in FIG. 11b-1, the signal A is always OFF, but a black circle symbol representing the determination portion is arranged at time “4”. Similarly, at time “4”, the signal B changes from ON to OFF. In this case, a source code for turning off the value of the signal B on condition that “the latest value of the signal A is OFF”, in other words, a condition code not referring to the previous value A ′ is generated.

  Thus, if an arrow symbol is used, a condition code corresponding to the rising edge or falling edge of the signal value is generated, while if a black circle symbol is used, a condition code corresponding only to the signal value level is generated. Is generated. That is, it is possible to specify a determination condition that is difficult to specify only from the time change of the signal value by arranging symbols having different meanings. In FIG. 11, the arrow symbol and the black circle symbol are illustrated as symbols to be arranged in the determination part, but other logic symbols (see FIGS. 3 and 4) may be arranged.

  Next, a procedure for generating a source code from a sequence diagram including a determination symbol will be described with reference to FIG. FIG. 12 is a flowchart showing a procedure for generating a source code from a sequence diagram including a determination symbol. In the figure, the case where the contents of the sequence diagram are sequentially read in the direction in which the time on the time axis increases is shown.

  First, the time axis is incremented by 1 (step S201), and the signal value on the corresponding time axis is read (step S202). Subsequently, it is determined whether or not there is a determination symbol on the corresponding time axis (step S203). If the determination symbol is found (step S203, Yes), whether or not the found symbol is a black circle symbol is determined. Determination is made (step S204). If no determination symbol is found in step S203 (No in step S203), the processing from step S201 is repeated.

  In step S204, when the determination symbol is a black circle symbol (step S204, Yes), the reference signal side code based on only the current value of the reference signal (the code in the parenthesis of the if statement in 11b-2 in FIG. 11). ) Is generated (step S205). On the other hand, if the determination symbol is not a black circle (No in step S204), the reference signal side code (the code in the parenthesis of the if statement in 11a-2 in FIG. 11) based on the current value and the previous value of the reference signal is generated. (Step S206).

  Following step S205 or step S206, the code generation unit 3d generates a control signal side code (processing code related to the variable B in 11a-2 or 11b-2 in FIG. 11) (step S207). Then, it is determined whether or not all data has been completed (step S208). If all data has been completed (step S208, Yes), the process ends. On the other hand, when all the data has not been completed (No at Step S208), the processes after Step S201 are repeated.

  In FIG. 12, an arrow symbol and a black circle symbol are illustrated as symbols to be arranged in the determination portion. However, when other logic symbols (see FIGS. 3 and 4) are arranged, a symbol type determination process ( Step S204) may be added according to the type of logic symbol.

  By the way, although the case where the determination part is designated by the logic symbol is shown in FIG. 11, the determination part can be designated by other methods. Therefore, hereinafter, the designated variation of the determination part will be described with reference to FIGS. 13 and 14.

  FIG. 13 is a diagram illustrating an example in which a determination part is set on the editor side. Here, the editor refers to the sequence diagram input screen shown in FIG. The sequence diagram and the source code shown in 13a of FIG. 13 are the same as 11a of FIG. 11, and 13b is the same as 11b of FIG.

  As shown in 13a-1 and 13b-1 in FIG. 13, when a predetermined section of the editor time axis is specified by clicking with the mouse, the specified section ("4" in FIG. 13) is determined. The editor recognizes that it is a part. Upon receiving information from the editor, the sequence diagram creation support unit 3a registers information representing the designated section in the storage unit 2 as sequence diagram information 2c together with the contents of the sequence diagram.

  FIG. 14 is a diagram illustrating an example when the determination portion is designated by changing the attribute of the signal line. The sequence diagram and the source code shown in 14a of FIG. 14 are the same as 11a of FIG. 11, and 14b is the same as 11b of FIG.

  As shown in 14a-1 and 14b-1 in FIG. 14, when the attribute value such as the thickness or color of the signal line representing the signal value is changed, the part having the different attribute value is regarded as the determination part. As described above, by making it possible to specify the determination portion by changing the attribute value of the signal line, it is possible to specify the determination portion with a simple operation, so that sequence diagram creation efficiency can be improved.

  Incidentally, in FIGS. 11 to 14, the determination based on the value of the reference signal (signal A in FIGS. 11 to 14) has been described, but the determination based on the value of the control signal (signal B in FIGS. 11 to 14). It is also possible to perform. Therefore, hereinafter, an example of the determination portion set on the control signal side will be described with reference to FIGS. 15 and 16.

  FIG. 15 is a diagram illustrating an example of a determination portion set on the control signal side. In FIG. 15, 15a shows the case where the previous value of the control signal is seen, and 15b shows the case where the previous value of the control signal is not seen.

  As indicated by 15a-1 in FIG. 15, at time “4”, the signal B is changed from ON to OFF, and an arrow symbol is arranged from ON to OFF. In this case, a source code for turning off the value of the signal B is generated on condition that “the previous value B ′ of the signal B is ON”. On the other hand, as shown in 15b-1, when an arrow symbol is not arranged, a source code for turning off the value of the signal B regardless of the previous value B 'of the signal B is generated.

  Next, a code generation processing procedure related to the control signal will be described with reference to FIG. FIG. 16 is a flowchart illustrating a code generation processing procedure related to the control signal. Note that the flowchart shown in FIG. 16 is a detailed version of step S207 shown in FIG.

  As shown in FIG. 16, the code generator 3d determines whether or not an arrow symbol is attached to the control signal (for example, signal B in FIG. 15) (step S301), and when the arrow symbol is attached. (Step S301, Yes), the control signal side code is generated with reference to the previous value (Step S302), and the process is terminated. On the other hand, when the arrow symbol is not attached (No at Step S301), the control signal side code is generated without referring to the previous value (Step S303), and the process is terminated.

  Next, the case where there is a delay in the change of the control signal will be described with reference to FIG. FIG. 17 is a diagram illustrating an example when there is a delay in the change of the control signal. Note that “delay” refers to changing the control signal after a predetermined time has elapsed from the change of the reference signal. 17a is a sequence diagram in which a delay is designated, 17b is a delay portion, 17c is a source code example 1 representing a delay, and 17d is a source code representing a delay. Examples 2 are shown respectively.

  As shown in 17b of FIG. 17, on the sequence diagram, the signal B as the control signal is changed at the time “6” when two unit times have elapsed after the signal A as the reference signal has changed at the time “4”. It is specified to do so.

  There are various source codes that express such a delay, but in this embodiment, two types of source codes are particularly illustrated. For example, as shown in 17c, a code for the delay () function that waits for a specified time following the determination code based on the signal A is generated (for example, a delay time “2” is specified as an argument of this function). . Then, a code for turning off the signal B is generated following the delay () function.

  Further, as shown in 17d, apart from the determination code based on the signal A, a timerproc_1ms () function that is executed every unit time (here, the unit time is 1ms) is generated, and this timerproc_1ms () function is generated. Among them, a function (count_down ()) for counting down the counter is called, and a code for changing the signal B from OFF to ON when the counter becomes 0 is generated.

  Next, a code generation processing procedure including a delay will be described with reference to FIG. FIG. 18 is a flowchart showing a code generation processing procedure including a delay. As shown in the figure, the code generation unit 3d acquires the determination time on the reference signal side (step S401) and also acquires the change time on the control signal side (step S402).

  If there is a difference between the determination time and the change time, that is, if there is a delay (step S403, Yes), the delay process is embedded (step S404) and the process ends. On the other hand, if there is no delay (step S403, No), the process is terminated without embedding the delay process.

  Next, a case where logic is directly specified in the determination part in the sequence diagram will be described with reference to FIG. FIG. 19 is a diagram illustrating an example when logic is specified in the determination part. In 19a of FIG. 19, a sequence diagram when logic is directly input and a source code generated based on this sequence diagram are generated correspondingly to 19b and 19c, and directly input logic is generated corresponding to 19b in 19d. The source code to be generated is shown in 19e, and the source code generated corresponding to 19c is shown.

  In this way, by allowing logic to be directly input to the determination part in the sequence diagram, it is possible to flexibly cope with the preference and level of the control program developer, and to improve the efficiency of control program generation work. it can. Further, by displaying the directly input logic on the sequence diagram, the control program developer can understand the logic shown in the time sequence diagram only by looking at the time sequence diagram.

  Next, how to use a plurality of external definition information 2d will be described with reference to FIGS. 20 and 21. FIG. FIG. 20 is a diagram illustrating an example when a plurality of external definition information 2d is prepared. In the figure, 20a is a sequence diagram in which symbols (α to ε) linked to external definition information are arranged, 20b is external definition information # 1, and 20c is an external whose contents are different from 20b. External definition information # 2 which is definition information is shown. Also, the broken arrows with δ and ε are symbols for designating that the signal value decreases by ε for each time δ.

  In this manner, different source codes can be generated by drawing one sequence diagram and combining the drawn sequence diagrams with external definition information having different contents. In other words, if a partial diagram having a specific change pattern is created, this partial diagram can be applied to other sequence diagrams. Therefore, it is possible to easily reuse and divert the sequence diagram.

  Next, processing for switching a plurality of external definition information shown in FIG. 20 will be described with reference to FIG. FIG. 21 is a flowchart showing a processing procedure for switching the external definition information 2d. As shown in the figure, when the user creates the sequence diagram and the external definition information 2d through the sequence diagram creation support unit 3a and the external definition information operation unit 3f (step S501), the code generation unit 3d A logic file is generated (step S502).

  The code generation unit 3d generates a label definition file from the external definition information 2d (step S503), and determines whether a plurality of external definition information 2d is registered (step S504). If a plurality of external definition information 2d are registered (step S504, Yes), the user is requested to specify how to properly use (step S505), and the logic for properly using the logic based on the received specified content is logic. The file is added (step S506), and the process is terminated.

  On the other hand, if it is determined in step S504 that the external definition information is singular or does not exist (No in step S504), the label definition file is reflected in the logic file (step S507) and the process is terminated. .

  20 and 21 explain how to use a plurality of external definition information 2d. However, this external definition is also used for the purpose of extracting a common code by absorbing the difference in the sequence diagram having a different appearance with the external definition information 2d. Information 2d can be used. Therefore, hereinafter, the case where the difference in the sequence diagram is absorbed by the external definition information 2d will be described with reference to FIGS.

  FIG. 22 is a diagram illustrating an example in which the difference in the sequence diagram is absorbed by the external definition information 2d. As shown by 22a and 22b in the figure, the signal value changes shown in the sequence diagrams are different, and the signals are different in that one is the signal A and the other is the signal B. However, even if the sequence diagrams look different in this way, the common code can be extracted if the difference is absorbed by the external definition information 2d.

  For example, in the external definition information # 1, the signal line included in the sequence diagram is defined as the signal line for the signal A. On the other hand, the external definition information # 2 defines the signal line for the signal B. In the external definition information # 1, the value of ε attached to the broken arrow is defined as 0.6, but in the external definition information # 2, the value of ε is defined as −0.2. As described above, when the difference between the sequence diagrams can be absorbed by using the external definition information, the logic corresponding to each sequence diagram can be shared.

  Next, a processing procedure when absorbing the difference in the sequence diagram with the external definition information 2d will be described with reference to FIG. FIG. 23 is a flowchart showing a processing procedure when the difference in the sequence diagram is absorbed by the external definition information 2d.

  The code generation unit 3d generates a logic file from the sequence diagram (step S601), and determines whether there is common logic (step S602). If there is a common logic (step S602, Yes), after extracting the common logic (step S603), the difference between the sequence diagrams is output to the external definition information 2d corresponding to each sequence diagram ( Step S604) The process ends. If there is no common logic (step S602, No), the process is terminated without performing the processes after step S603.

  Next, a user input complementing function performed by the sequence diagram creation support unit 3a will be described with reference to FIG. FIG. 24 is a diagram illustrating an example of a supplement function for user input. Here, the complementary function refers to a function for automatically inputting a signal line or other symbols inferred from the received input process when an input process by the user is received.

  For example, as shown at 24a in FIG. 24, the user inputs a signal line indicating that the signal A changes at time “4” in the direction from ON to OFF (in the direction of the dashed arrow), and the time “ It is assumed that the signal line is input in the direction from OFF to ON in “6” (the direction of the broken arrow). In this case, since it can be inferred that the value of the signal line does not change in other time zones, this complementary function automatically draws the horizontal line shown in 24b to complete the signal line.

  The part automatically drawn by the completion function (complement part) is stored separately from the part entered by the user, so it is possible to generate source code that faithfully reflects the user's intention. it can. For example, when it is specified that the complementary part is excluded from the source code generation (see 24c in FIG. 24), the source code indicating that the signal A is OFF at time “4” and the signal A is ON at time “6”. Is generated. On the other hand, if it is specified that the complementary part is not excluded from the source code generation, the signal A is always ON at the time “0 to 4”, is always OFF at the time “4 to 6”, and after the time “6”. A source code indicating that is always ON is generated.

  Next, a case where the code generation unit 3d generates source code based on the programming rule information will be described with reference to FIGS. FIG. 25 is a diagram illustrating an application example of programming rule information. The programming rule information may be included in the external definition information 2d and the common code information 2e, or may be registered in the storage unit 2 as information different from the external definition information 2d and the common code information 2e. Also good.

  25a in FIG. 25 is an example of source code generated by the code generation unit 3d without applying the programming rule, and 25c is an example of source code generated by applying the programming rule (rule # 1) shown in 25b. It is.

  As shown in 25b of FIG. 25, in rule # 1, an external variable that is referenced from an external module with a high priority is copied to a local variable and then subjected to arithmetic processing, and the arithmetic result is set to the external variable. Is specified. In FIG. 25B, rule # 1 is shown as text for explanation, but rule # 1 may be described by a combination of symbols, alphanumeric characters, and the like representing the same contents.

  Also, as indicated by 25a in FIG. 25, in the source code before applying rule # 1, the upper limit is set so that the value of a does not exceed a predetermined upper limit value (A_MAX) after incrementing the external variable a. Is described. However, since the variable a is an external variable, immediately after the code “a + = 1;” of func1 () is executed, if another function or the like refers to the value of a, the value of a becomes “A_MAX + 1”. (That is, the value of a before the upper limit restriction is referred to) occurs.

  On the other hand, in the source code after applying rule # 1, the value of the external variable a is assigned to the local variable a_local, the same arithmetic processing as 25a is performed on a_local, and the result of the operation is assigned to the external variable a. Yes. Therefore, it is possible to prevent an external module from referring to the value a before the upper limit is limited.

  Note that the example shown in FIG. 25 is merely an example of a programming rule. As another example, for example, if a variable that is not used at the same time is registered as a programming rule that a variable indicating the same memory area is used, the memory area used by the control program is efficiently used. Can be reduced.

  Next, the processing procedure of the programming rule information application processing will be described with reference to FIG. FIG. 26 is a flowchart showing the processing procedure of the programming rule information application processing. As shown in the figure, the code generation unit 3d reads the logic once generated (step S701), and detects the priority for each module by checking the reference / reference relationship between modules (step S702).

  Subsequently, a rule is read from the programming rule information (step S703), and it is determined whether or not the module has a low priority (step S704). If the module has a low priority (step S704, Yes), the rule read in step S703 is applied to the logic read in step S701 (step S705), and logic correction is executed (step S706). The process ends. On the other hand, if the module has a high priority (step S704, No), the process is terminated without performing the processes after step S705.

  Next, common module extraction processing performed by the common code extraction unit 3e will be described with reference to FIGS. 27 and 28. FIG. 27 and 28 are diagrams showing common module extraction examples 1 and 2, respectively. In FIG. 27, an example of reducing a user's sequence diagram input work burden by extracting signal value control processing for a plurality of signals having a predetermined operational relationship as a common module, and FIG. 28 is a sequence diagram of FIG. Each example shows that the readability of the generated code is improved by extracting the signal value control processing of a predetermined portion as a common module.

  First, FIG. 27 will be described. As shown by 27a in FIG. 27, when the signal A as the reference signal is 0, both the signal B and the signal C as the control signals are OFF, and when the signal A is 1, the signal B is ON. When the signal C is OFF and the signal A is 2, it is assumed that both the signal B and the signal C are ON. As described above, when a control signal that changes in accordance with a change in the reference signal is specified, the description about the signal B and the signal C in each sequence diagram is superior.

  Therefore, the relationship between the signals shown in 27a is extracted as a common module A (see 27b in FIG. 27). Then, as shown in 27c of FIG. 27, when the user performs the drawing operation of the signal A, the user is linked to the common module A including the instruction to change the signal B and the signal C. By doing in this way, a user's input operation can be reduced effectively.

  Next, FIG. 28 will be described. The sequence diagram shown by 28a in FIG. 28 and the sequence diagram shown by 28b in FIG. 28 have the common point that the signal C is displaced from OFF to ON. Therefore, a displacement process for displacing the signal C from OFF to ON, a substitution process accompanying the displacement process, and the like are extracted as a common module (“c_on ()” in FIG. 28). Then, when generating codes corresponding to 28a and 28b in FIG. 28, logic in which this common module is embedded is generated (see 28d and 28e in FIG. 28).

  Next, an example of the above “macro-ization” will be described with reference to FIG. FIG. 29 is a diagram illustrating an example of rendering component macro. In FIG. 29, “No” representing the number of each example, “Pre-macro” representing the combination of the drawing parts 2a before macroization, and “Post-macroization” representing the new drawing parts 2a after macroization. ".

  In No. 1 of FIG. 29, an example is shown in which a part obtained by combining 103 g, 103 j, and 104 b in the drawing part 2 a shown in FIGS. 3 and 4 is defined as a new drawing part 2 a composed of a double circle and an arrow. Yes. Thus, by replacing the combination of a plurality of drawing components 2a with one drawing component 2a, drawing operations associated with sequence diagram creation can be omitted, so that sequence diagrams can be created efficiently.

  In the example shown in No. 2 and No. 3 in FIG. 29, the drawing operation can be omitted as in the example shown in No. 1. In particular, it is possible to improve the efficiency of sequence diagram creation by registering a pattern used many times in a sequence diagram as a new drawing component 2a, and it is uniform when a plurality of users share the work and proceed. A sequence diagram can be created.

  Next, an example of the above “pattern extraction” will be described with reference to FIG. FIG. 30 is a diagram illustrating an example of pattern extraction in the sequence diagram. The common pattern information 2b can be extracted so as to include the variable name corresponding to the signal value as it is, or can be extracted as information that does not include the variable name.

  30a shown in FIG. 30 is a sequence diagram as an extraction source, and a dotted-line rectangular portion shown in 130a is a portion to be extracted. The extraction target portion may be specified by the user, or may be automatically extracted by the pattern extraction unit 3b using a technique such as pattern matching.

  In addition, 130b shown in FIG. 30 is an example in the case where the variable name corresponding to the signal value is extracted as it is, and similarly 130c is an example in which the information is extracted as information not including the variable name corresponding to the signal value. It is.

  Next, a synthesis example of the sequence diagram information 2c and the external definition information 2d shown in FIG. 2 will be described with reference to FIG. FIG. 31 is a diagram showing a synthesis example of the sequence diagram information 2c and the external definition information 2d. In the figure, 131a is a sequence diagram corresponding to sequence diagram information 2c, 131b and 131c are external definition information 2d having different contents, and 131d and 131e are generated corresponding to 131b and 131c, respectively. Code.

  When it is described that the signal A, the signal B, and the signal C are changed at the timing α as indicated by 131a in FIG. 31, a mark (symbol) that represents the operational relationship of each signal is omitted. , Which signal is changed based on which signal change cannot be uniquely determined.

  Therefore, in the external definition information A131b, as a signal attribute, a reference signal from which the signal A acts is a signal, a control signal from which the signal B and the signal C are to act, and information that the signal C depends on a change in the signal B. Include. When the external definition information A131b and the sequence diagram 131a are combined, when the signal A changes from OFF to ON, the signal C is turned ON and the signal B is triggered by the change of the signal C from OFF to ON. Is generated as a source code A131d to turn ON.

  On the other hand, in the external definition information B131c, as a signal attribute, the signal A is the reference signal that is the source of the action, the signal B and the signal C are the control signals that are the destination of the action, and the signal B and the signal C are equal signals. Information shall be included. When the external definition information 131c and the sequence diagram 131a are combined, when the signal A changes from OFF to ON, the source code B 131e for turning on the signal B and the signal C is generated.

  As described above, even if the sequence diagrams are the same, different source codes can be generated by changing the external definition information 2d. If rules specific to various languages are included in the external definition information 2d, source codes in different programming languages can be generated from the same sequence diagram. Further, as shown in FIG. 31, if the external definition information 2d includes information corresponding to the drawing component 2a, the drawing operation of the sequence diagram can be simplified, so that the efficiency of the sequence diagram creation work is improved. Can do.

  Next, the sequence diagram dividing process performed by the sequence diagram creation support unit 3a shown in FIG. 2 will be described with reference to FIG. FIG. 32 is a diagram illustrating a division example of the sequence diagram. As shown in the figure, when it is desired to divide the sequence diagram 132a displayed on the sequence diagram input screen, a line indicating the boundary of the sequence diagram as the drawing component 2a (see 132b in FIG. 32), a rectangle or the like is closed. A prepared figure (132c in FIG. 32) is prepared. Then, when the sequence diagram 132a is divided by the boundary line, the divided sequence diagrams 1 and 2 are generated as indicated by an arrow A in FIG. When the sequence 132b is designated by the boundary rectangle, the sequence diagram 3 in the designated range is generated as indicated by the arrow B in the figure.

  As described above, when the sequence diagram creation support unit 3a performs the sequence diagram dividing process, the sequence diagram creation support unit 3a can appropriately divide the sequence diagram information 2c registered in the storage unit 2. Therefore, it is possible to optimize the generation unit of the source code generated by the code generation unit 3d and improve the reusability of the source code.

  Next, a sequence diagram combining process performed by the sequence diagram creation support unit 3a shown in FIG. 2 will be described with reference to FIG. FIG. 33 is a diagram illustrating a combination example of sequence diagrams. As shown in the figure, when there are a plurality of sequence diagrams, the sequence diagram creation support unit 3a receives the relationship information (see 133a in FIG. 33) indicating the relationship between the plurality of sequence diagrams and each sequence diagram. The sequence diagrams are combined based on the description contents of the relationship information.

  For example, the relationship information describes that sequence diagram 2 is located on the right side of sequence diagram 1, sequence diagram 3 is located on the lower side of sequence diagram 1, and sequence diagram 4 is located on the right side of sequence diagram 3. If so, a sequence diagram (see 133b in FIG. 33) indicated by an arrow A in FIG. 33 is generated. In addition, when it is described in the relationship information that the sequence diagrams 1 to 4 are arranged in the order from left to right, a sequence diagram (see 133c in FIG. 33) shown by an arrow B in FIG. 33 is generated. Is done.

  As described above, when the sequence diagram creation support unit 3a performs the sequence diagram combining process, the sequence diagram creation support unit 3a can appropriately combine the sequence diagram information 2c registered in the storage unit 2. Therefore, it is possible to generate a source code after collecting a huge sequence diagram and a sequence diagram created by sharing a plurality of users into one.

  Next, a network configuration example of the control program generation device 1 shown in FIG. 2 will be described with reference to FIG. FIG. 34 is a diagram illustrating a network configuration example of the control program generation device 1. Note that the network configuration example in the figure shows a case where distributed development is performed by a plurality of users (program developers). Further, the “control program generating program” shown in FIG. 2 corresponds to the control unit 3 in FIG. 2, and the “storage unit” corresponds to the storage unit 2 in FIG.

  As shown in FIG. 34, a “control program generation program” is installed on a plurality of personal computers (PCs), and a “storage unit” for storing various information such as drawing parts 2a and external definition information 2d is connected via a LAN or the like. If configured on the predetermined PC, a large number of program developers can perform sequence diagram creation work and source code creation work using common information. Further, if various kinds of information on the “storage unit” are updated, if an exclusive process is performed, inconveniences such as a plurality of program developers registering contradictory information can be avoided.

  As described above, in this embodiment, the sequence diagram creation support unit supports the creation of the sequence diagram by providing the drawing parts to the user, and the sequence diagram information received from the sequence diagram creation support unit by the code generation unit Since the source code is generated by synthesizing the attributes and arrangement information of the drawing parts included in and the external definition information prepared separately from the sequence diagram information, it is digitized as the basis for generating the control program. It is possible to support efficient creation of a time sequence diagram and to automatically generate a control program corresponding to an electronic time sequence diagram.

  In the above-described embodiment, the case where the code generation unit generates the source code based on the sequence diagram information generated by the sequence diagram creation support unit has been described. However, the present invention is not limited to this, and the code generation unit may generate a document representing the control specifications or an inspection program for performing an operation inspection of the source code based on the sequence diagram information. By doing so, it becomes possible to collectively manage the products accompanying the generation of the control program, and even when the sequence diagram is changed, the change can be reflected on the entire product.

  As described above, the control program generation program, the control program generation method, and the control program generation apparatus according to the present invention are useful for automatic generation of a control program for controlling various signal values, and in particular, control that operates on an in-vehicle computer. Suitable for automatic program generation.

It is a figure which shows the outline | summary and the characteristic of the control program production | generation method based on this invention. It is a block diagram which shows the structure of the control program production | generation apparatus which concerns on a present Example. It is a figure which shows the example 1 of a drawing component. It is a figure which shows the example 2 of a drawing component. It is a figure which shows the example 1 of arrangement | positioning to the sequence diagram of drawing components. It is a figure which shows the example 2 of an arrangement | positioning to the sequence diagram of drawing components. It is a figure which shows an example of a sequence diagram. It is a figure which shows the example 1 of a control program produced | generated from the sequence diagram shown in FIG. It is a figure which shows the example 2 of the control program produced | generated from the sequence diagram shown in FIG. It is a flowchart which shows the outline | summary of a control program production | generation procedure. It is a figure which shows the example at the time of designating the determination part with a logic symbol. It is a flowchart which shows the procedure which produces | generates a source code from the sequence diagram containing the determination symbol. It is a figure which shows the example at the time of setting the determination part on the editor side. It is a figure which shows the example at the time of designating the determination part by the attribute change of a signal line. It is a figure which shows the example of the determination part set to the control signal side. It is a flowchart which shows the code | cord | chord generation process procedure which concerns on a control signal. It is a figure which shows the example in case there exists a delay in the change of a control signal. It is a flowchart which shows the code generation processing procedure containing a delay. It is a figure which shows the example at the time of specifying a logic in the determination part. It is a figure which shows the example at the time of preparing several external definition information. It is a flowchart which shows the process sequence of the switching process of external definition information. It is a figure which shows the example which absorbs the difference of a sequence diagram with external definition information. It is a flowchart which shows the process sequence at the time of absorbing the difference of a sequence diagram with external definition information. It is a figure which shows the example of the complement function of a user input. It is a figure which shows the example of application of programming rule information. It is a flowchart which shows the process sequence of a programming rule information application process. It is a figure which shows the example 1 of common module extraction. It is a figure which shows the example 2 of a common module extraction. It is a figure which shows the example of drawing components macro conversion. It is a figure which shows the example of the pattern extraction in a sequence diagram. It is a figure which shows the example of a synthesis | combination of sequence diagram information and external definition information. It is a figure which shows the example of a division | segmentation of a sequence diagram. It is a figure which shows the example of a coupling | bonding of a sequence diagram. It is a figure which shows the network structural example of a control program production | generation apparatus.

DESCRIPTION OF SYMBOLS 1 Control program production | generation apparatus 2 Memory | storage part 2a Drawing part 2b Common pattern information 2c Sequence diagram information 2d External definition information 2e Common code information 3 Control part 3a Sequence diagram creation assistance part 3b Pattern extraction part 3c Drawing part registration part 3d Code generation part 3e Common code extraction unit 3f External definition information operation unit 4 Input / output unit 4a Input means 4b Display

Claims (15)

A control program generation program for generating a control program for controlling a controlled device,
When a user creates a time sequence diagram representing a time change of a plurality of signals used for controlling the controlled device, the relationship between signals used for controlling the controlled device is represented by a logic symbol in the time sequence diagram. An input procedure that allows the user to input by arranging
A control program generation program for causing a computer to execute a control program generation procedure for generating the control program based on attributes and arrangement information of the logic symbols arranged in the time sequence diagram received in the input procedure. The control program generation procedure includes:
When the relationship between the signals defined by the logic symbols arranged in the time sequence diagram is expanded to the control program, according to the drawing order of the signals in which the logic symbols are arranged in the time sequence diagram The control program generation program according to claim 1, wherein the control program that reflects the relationship between the signals is generated. The control program generation procedure includes:
The time sequence of the signal in which the logic symbol is arranged when the logic symbol arranged in the time sequence diagram includes development order information representing a development order for developing the relationship between signals to the control program The control program generation program according to claim 2, wherein the control program that reflects the relationship between signals is generated with priority on the development order information over the drawing order in the figure. The input procedure is as follows:
Allowing the input of a boundary to divide the time sequence diagram into a predetermined number of partial views;
The control program generation procedure includes:
The control program generation program according to claim 1, wherein the control program is generated for each partial view divided by the boundary. The input procedure is as follows:
Allowing input of a plurality of time sequence diagrams and relationship information between each time sequence diagram,
The control program generation procedure includes:
The control program generation program according to any one of claims 1 to 4, wherein the control program is generated after combining the time sequence diagrams based on the relationship information. The control program generation procedure includes:
When the relationship between the signals defined by the logic symbols arranged in the time sequence diagram is expanded to the control program, other signals after a specific signal changes among the signals having the relationship The control program generation program according to any one of claims 1 to 5, wherein when there is a delay time until the change, the control program reflecting the delay time is generated. The input procedure is as follows:
The logic symbol has a logic symbol that allows direct input of program logic. When the logic symbol is displayed in the time sequence diagram, the program logic directly input by the user is displayed as one of the logic symbols. The control program generation program according to claim 1, wherein the control program generation program is displayed as a unit. The control program generation procedure includes:
When the relationship between the signals defined by the logic symbols arranged in the time sequence diagram is expanded to the control program, the signal control logic indicating the change of each signal and the signal control logic are predetermined. The control program generation program according to any one of claims 1 to 7, wherein the control program is generated separately from the time control logic to be called at the timing. Further causing the computer to execute a definition data registration procedure for registering definition data defining attributes of the logic symbols in a storage unit,
The control program generation procedure includes:
The control program is generated by associating the arrangement information of the logic symbols included in the time sequence diagram with the definition data registered by the definition data registration procedure. The control program generation program according to any one of the above. Causing the computer to further execute a pattern extraction procedure for extracting a common signal control pattern from the one or more time sequence diagrams received by the input procedure;
The control program generation procedure includes:
10. The control according to claim 1, wherein the control program using the common logic is generated after the signal control pattern extracted by the pattern extraction procedure is converted into common logic. Program generation program. The pattern extraction procedure includes:
11. The control program generation program according to claim 10, wherein a combination of the logic symbols representing the operational relationship of the signals is extracted as the common signal control pattern. The input procedure is as follows:
When it is determined that there is a non-input part in the time sequence diagram from the positional relationship of the logic symbols arranged by the user, the time sequence diagram is input-completed based on the positional relationship of the logic symbols. A control program generation program according to any one of claims 1 to 11. The control program generation procedure includes:
When developing the relationship between signals defined by the logic symbols arranged in the time sequence diagram to the control program, a programming rule representing a logic and a data storage area securing rule constituting the control program The control program generation program according to any one of claims 1 to 12, wherein the control program is generated by using the control program. A control program generation device for generating a control program for controlling a controlled device,
When a user creates a time sequence diagram representing a time change of a plurality of signals used for controlling the controlled device, the relationship between signals used for controlling the controlled device is represented by a logic symbol in the time sequence diagram. Input means for allowing the user to input by arranging
A control program generation device comprising: control program generation means for generating the control program based on the attribute and arrangement information of the logic symbols arranged in the time sequence diagram received by the input means. A control program generation method for generating a control program for controlling a controlled device,
When a user creates a time sequence diagram representing a time change of a plurality of signals used for controlling the controlled device, the relationship between signals used for controlling the controlled device is represented by a logic symbol in the time sequence diagram. An input process that allows the user to input by arranging
A control program generation method comprising: a control program generation step of generating the control program based on the attribute and arrangement information of the logic symbols arranged in the time sequence diagram received in the input step.

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