JP2007194330A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device for preventing erroneous operation caused by coupling capacity among lead wires for wiring. <P>SOLUTION: The semiconductor device includes a first wiring layer M1 and a second wiring layer M2. Each of the first wiring layer M1 and the second wiring layer M2 includes a global bit line GBL_EVEN, and a global bit line GBL_ODD that is activated when the global bit line GBL_EVE is not activated. In each layer of the first wiring layer M1 and the second wiring layer M2, the global bit lines GBL_EVEN and GBL_ODD are alternately arranged, the global bit lines GBL_EVEN and GBL_ODD in the first wiring layer M1 and the second wiring layer M2 are arranged in almost parallel, and different global line GBL is arranged in the first wiring layer M1 and the second wiring layer M2 in the laminating direction of the first wiring layer M1 and the second wiring layer M2. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a plurality of wirings such as a data bus.

  In recent years, as the capacity of memory chips has increased, process technology has become finer, and the wiring width and wiring interval of data buses and the like in semiconductor devices have become smaller.

  In addition, although the prior art about this invention was demonstrated based on the general technical information which the applicant acquired, the information which should be disclosed as prior art document information before filing in the range which an applicant memorize | stores The applicant does not have

  When the wiring width and the wiring interval of the data bus are reduced, the disturbance due to the coupling capacitance between the data bus wirings becomes a serious problem. More specifically, when a plurality of wirings are activated, if the coupling capacitance between the wirings is large, the level of the other wiring fluctuates due to the coupling of one wiring, and the semiconductor device malfunctions. End up.

  Therefore, an object of the present invention is to provide a semiconductor device capable of preventing malfunction caused by coupling capacitance between wirings.

  In order to solve the above problems, a semiconductor device according to an aspect of the present invention includes a first wiring layer and a second wiring layer, and each of the first wiring layer and the second wiring layer includes: Including a first wiring and a second wiring that is activated when the first wiring is not activated. The first wiring and the second wiring in each of the first wiring layer and the second wiring layer Two wirings are alternately arranged, and the first wiring and the second wiring in the first wiring layer, and the first wiring and the second wiring in the second wiring layer are arranged substantially in parallel, In the stacking direction of the wiring layer and the second wiring layer, when the first wiring is disposed in the first wiring layer, the second wiring is disposed in the second wiring layer, and the first wiring layer is disposed in the first wiring layer. When the second wiring is arranged, the first wiring is arranged in the second wiring layer.

  According to the present invention, it is possible to prevent malfunction of the semiconductor device due to the coupling capacitance between the wirings.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

<First Embodiment>
FIG. 1 is a diagram schematically showing a configuration of a semiconductor device according to a first embodiment of the present invention.

  Referring to FIG. 2, the semiconductor device is, for example, an AG-AND type flash memory, and includes a plurality of memory cells MC arranged in a matrix. A plurality of word lines WL are arranged corresponding to each row of the plurality of memory cells MC. In the figure, among the plurality of word lines WL, a word line WLA and a word line WLB are representatively shown. The control gate CG of each memory cell MC is connected to the corresponding word line WL.

  A plurality of global bit lines GBL are arranged in the column direction. Each of the plurality of global bit lines GBL is directly connected to the source of the corresponding memory cell MC, or is connected to the source of the corresponding memory cell MC via the assist gate transistor AGT. In the drawing, among the plurality of global bit lines GBL, global bit lines GBL_EVEN1 to GBL_EVEN3 and global bit lines GBL_ODD1 to GBL_ODD2 are representatively shown.

  Further, the semiconductor device includes a plurality of assist gate transistors AGT arranged in the column direction. The plurality of assist gate transistors AGT are connected to an assist gate line AG extending in the column direction. The assist gate line AG corresponds to the gate of a MOS transistor (insulated gate type field effect transistor), and an inversion layer is formed on the semiconductor substrate below the assist gate transistor AGT based on the voltage supplied to the assist gate line AG. .

  Further, the semiconductor device includes a plurality of selection transistors MTA and selection transistors MTB arranged in the row direction.

  Next, an operation when the nonvolatile semiconductor device according to the embodiment of the present invention writes data to the memory cell MC will be described. Here, a case where data is written to memory cell MC0A and memory cell MC4A will be described.

  At the time of data writing, global bit lines GBL_ODD1 and GBL_ODD2 corresponding to memory cell MC0A and memory cell MC4A to be written are driven to a selected state. Further, the global bit lines GBL_EVEN1 to GBL_EVEN3 are driven to a non-selected state.

  Further, the word line WLA corresponding to the memory cell MC0A and the memory cell MC4A is driven to the selected state. Further, the voltage line STA and the voltage line STB are driven to the selected state, and the selection transistors MTA0 to MTA4 and the selection transistors MTB0 to MTB3 are turned on. In addition, assist gate line AG0 corresponding to memory cell MC0A and memory cell MC4A is driven to a selected state, and an inversion layer is formed in a region below assist gate transistors AGT0 and AGT4.

  Then, current flows between global bit line GBL_ODD1 and common voltage line CD, and between global bit line GBL_ODD2 and common voltage line CD via memory cells MC0A and memory cell MC4A that are in the on state. Then, a high electric field is generated in the memory cell MC0A and the memory cell MC4A. High energy electrons (hot electrons) generated by the high electric field are attracted to the electric field generated by the high voltage applied to the word line WLA and reach the floating gates of the memory cell MC0A and the memory cell MC4A, thereby writing data. Done.

  Next, the operation when the nonvolatile semiconductor device according to the embodiment of the present invention reads data from the memory cell MC will be described. Here, a case where data is read from memory cell MC0A and memory cell MC4A will be described.

  At the time of data reading, the global bit lines GBL_ODD1 and GBL_ODD2 corresponding to the memory cells MC0A and MC4A to be read are driven to a selected state. Further, the global bit lines GBL_EVEN1 to GBL_EVEN3 are driven to a non-selected state.

  Further, the word line WLA corresponding to the memory cell MC0A and the memory cell MC4A is driven to the selected state. Further, the voltage line STA and the voltage line STB are driven to the selected state, and the selection transistors MTA0 to MTA4 and the selection transistors MTB0 to MTB3 are turned on. In addition, assist gate line AG0 corresponding to memory cell MC0A and memory cell MC4A is driven to a selected state, and an inversion layer is formed in a region below assist gate transistors AGT0 and AGT4.

  Then, current flows between global bit line GBL_ODD1 and common voltage line CD, and between global bit line GBL_ODD2 and common voltage line CD via memory cells MC0A and memory cell MC4A that are in the on state. The amount of current flowing between each global bit line and the common voltage line is determined by the threshold voltage corresponding to the amount of charge accumulated in the floating gates of memory cell MC0A and memory cell MC4A, and the read voltage supplied to word line WL. . Then, the sense amplifier (not shown) detects the amount of current flowing between each global bit line GBL and common voltage line CD, whereby the data stored in memory cell MC0A and memory cell MC4A is read.

  FIG. 2 is a diagram showing a layout of the semiconductor device according to the first embodiment of the present invention. 3 is a cross-sectional view showing the ab cross section in FIG. 2 of the semiconductor device according to the first embodiment of the present invention.

  Referring to FIGS. 2 and 3, the semiconductor device includes a semiconductor substrate 1 and insulating layers 2 to 3.

  An insulating layer 2 is disposed on the semiconductor substrate 1. The insulating layer 2 includes a control gate CG. An insulating layer 3 is disposed on the insulating layer 2. The insulating layer 3 includes a wiring layer M. The wiring layer M includes global bit lines (first wiring) GBL_EVEN1 to GBL_EVEN4 and global bit lines (second wiring) GBL_ODD1 to GBL_ODD4. The global bit line GBL_EVEN and the global bit line GBL_ODD are arranged alternately and substantially in parallel in the wiring layer M.

  The control gate CG shown in FIG. 3 corresponds to the word line WLA and the word line WLB, and is arranged substantially perpendicular to the global bit line GBL_EVEN and the global bit line GBL_ODD.

  As described above, in the semiconductor device according to the first embodiment of the present invention, the global bit line GBL_ODD and the global bit line GBL_EVEN are alternately and substantially arranged in the wiring layer M, and data writing and data reading are performed. Is performed, one of the global bit line GBL_ODD and the global bit line GBL_EVEN is activated and the other is deactivated. With such a configuration, it is possible to prevent malfunction of the semiconductor device due to the coupling capacitance between adjacent global bit lines.

  Next, another embodiment of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

<Second Embodiment>
The present embodiment relates to a semiconductor device in which the layer structure is changed with respect to the semiconductor device according to the first embodiment. Configurations and operations other than those described below are the same as those of the semiconductor device according to the first embodiment.

  FIG. 4 is a diagram showing a layout of a semiconductor device according to the second embodiment of the present invention. FIG. 5 is a cross-sectional view showing the ab cross section in FIG. 4 of the semiconductor device according to the second embodiment of the present invention.

  Referring to FIGS. 4 and 5, the semiconductor device further includes an insulating layer 4 in addition to the semiconductor device according to the first embodiment.

  An insulating layer 2 is disposed on the semiconductor substrate 1. The insulating layer 2 includes a control gate CG. An insulating layer 3 is disposed on the insulating layer 2. The insulating layer 3 includes a first wiring layer M1. The first wiring layer M1 includes global bit lines GBL_ODD1, GBL_EVEN2, GBL_ODD3, and GBL_EVEN4. An insulating layer 4 is disposed on the insulating layer 3. The insulating layer 4 includes a second wiring layer M2. The second wiring layer M2 includes global bit lines GBL_EVEN1, GBL_ODD2, GBL_EVEN3, and GBL_ODD4.

  The global bit line GBL_EVEN and the global bit line GBL_ODD are alternately arranged in each of the first wiring layer M1 and the second wiring layer M2. The global bit line GBL_EVEN and the global bit line GBL_ODD in the first wiring layer M1, and the global bit line GBL_EVEN and the global bit line GBL_ODD in the second wiring layer M2 are arranged substantially in parallel. In the stacking direction of each layer in the semiconductor device, a global bit line GBL that is not activated simultaneously is arranged in the first wiring layer M1 and the second wiring layer M2. That is, in the stacking direction of each layer in the semiconductor device, when the global bit line GBL_EVEN is arranged in one wiring layer, the global bit line GBL_ODD is arranged in the other wiring layer, and the global bit line GBL_ODD is arranged in one wiring layer. When arranged, the global bit line GBL_EVEN is arranged in the other wiring layer.

  The first wiring layer M1 further includes shield wirings VSS1 to VSS4. The shield wirings VSS1 to VSS4 are respectively disposed between the global bit line GBL_EVEN and the global bit line GBL_ODD in the first wiring layer M1. The shield wirings VSS1 to VSS4 are included in the second wiring layer M2, and each of the shield wirings VSS1 to VSS4 is arranged between the global bit line GBL_EVEN and the global bit line GBL_ODD in the second wiring layer M2. There may be. Further, the shield wirings VSS1 to VSS4 may be included in both the first wiring layer M1 and the second wiring layer M2.

  FIG. 6A is a diagram showing coupling capacitance between global bit lines in the semiconductor device according to the first embodiment of the present invention. FIG. 6A schematically shows a part of FIG.

  FIG. 6B is a diagram showing the coupling capacitance between global bit lines in the semiconductor device according to the second embodiment of the present invention. FIG. 6B schematically shows a part of FIG.

  Referring to FIG. 6A, in the semiconductor device according to the first embodiment of the present invention, the electric lines of force in the region connecting linearly between global bit lines GBL_EVEN1 and GBL_EVEN2 are blocked by global bit line GBL_ODD1. be able to. However, in the semiconductor device according to the first embodiment of the present invention, a coupling capacitor A is generated between the global bit lines GBL_EVEN1 and GBL_EVEN2 due to electric lines of force that wrap around the upper and lower layers of the wiring layer M.

  On the other hand, referring to FIG. 6B, in the semiconductor device according to the second embodiment of the present invention, the electric lines of force that wrap around the both sides of the region that linearly connects the global bit lines GBL_EVEN1 and GBL_EVEN2 are shown. They can be blocked by the shield wiring VSS1 and the global bit line GBL_ODD1, respectively. Here, a coupling capacitor B is generated in a region linearly connecting the global bit lines GBL_EVEN1 and GBL_EVEN2, but the distance between the global bit lines GBL_EVEN1 and GBL_EVEN2 is larger than that of the semiconductor device according to the first embodiment. Therefore, the influence of the coupling capacitor B is smaller than that of the coupling capacitor A.

  Therefore, in the semiconductor device according to the second embodiment of the present invention, the semiconductor device according to the first embodiment of the present invention further includes a semiconductor device caused by coupling capacitance between global bit lines. Malfunctions can be prevented.

  In the semiconductor device according to the second embodiment of the present invention, the first wiring layer M1 includes the shield wirings VSS1 to VSS4. However, the present invention is not limited to this. For example, in FIG. 5B, even if the first wiring layer M1 does not include the shield wirings VSS1 to VSS4, the electric force lines that wrap around the both sides of the region that linearly connects the global bit lines GBL_EVEN1 and GBL_EVEN2 are shown. They can be blocked by the global bit line GBL_ODD1 and the global bit line GBL_ODD2, respectively. In the semiconductor device according to the second embodiment of the present invention, the first wiring layer M1 further includes the shield wirings VSS1 to VSS4, so that the global bit lines GBL_EVEN1 and GBL_EVEN2 are linearly connected. It is possible to more reliably block the electric lines of force that run around both sides of the connecting region.

  In the semiconductor device according to the first embodiment of the present invention, coupling capacitance is generated in the upper and lower layers of the wiring layer between the global bit lines GBL_EVEN1 and GBL_EVEN2, whereas the second embodiment of the present invention is used. In the semiconductor device according to the embodiment, a coupling capacitance is generated in a region that linearly connects the global bit line GBL_EVEN1 in the first wiring layer M1 and the GBL_EVEN2 in the second wiring layer M2.

  Here, when the process technology is miniaturized as the capacity of the memory chip is increased and the wiring width and the wiring interval of the data bus in the semiconductor device are reduced, the distance between the first wiring layer M1 and the second wiring layer M2 is increased. In comparison, the distance between the global bit lines GBL in the same wiring layer is reduced, and the influence of the coupling capacitance between the global bit lines GBL in the same wiring layer is increased. Therefore, the semiconductor device according to the second embodiment of the present invention that reduces the coupling capacitance generated between the global bit lines GBL in the same wiring layer is further different from the semiconductor device according to the first embodiment. High effectiveness.

  In addition, when a simulation was performed with a manufacturing rule of 35 nm (nanometers) in the configuration of the semiconductor device according to the first and second embodiments of the present invention, the space between the global bit lines GBL with respect to the total capacity of the global bit lines GBL was determined. The ratio of the coupling capacitance is about 4% in the semiconductor device according to the first embodiment of the present invention, but the result is about 3% in the semiconductor device according to the second embodiment of the present invention. It has been.

  Although the semiconductor device according to the embodiment of the present invention is an AG-AND type flash memory, the present invention is not limited to this. For example, the present invention can be applied to various types of memories such as a memory of NAND type and NOR type. Furthermore, the present invention can be applied to any semiconductor device having a plurality of wirings such as a data bus and an address bus.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 is a diagram schematically showing a configuration of a semiconductor device according to a first embodiment of the present invention. 1 is a diagram showing a layout of a semiconductor device according to a first embodiment of the present invention. It is sectional drawing which shows the ab cross section in FIG. 2 of the semiconductor device which concerns on the 1st Embodiment of this invention. It is a figure which shows the layout of the semiconductor device which concerns on the 2nd Embodiment of this invention. FIG. 5 is a cross-sectional view showing a cross section taken along line ab in FIG. 4 of a semiconductor device according to a second embodiment of the present invention. (A) It is a figure which shows the coupling capacitance between the global bit lines in the semiconductor device which concerns on the 1st Embodiment of this invention. (B) It is a figure which shows the coupling capacitance between global bit lines in the semiconductor device which concerns on the 2nd Embodiment of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Semiconductor substrate, 2-4 insulating layer, M1 1st wiring layer, M2 2nd wiring layer, MC, MC0A-MC4A, MC0B-MC4B Memory cell, WL, WLA, WLB Word line, CG control gate, GBL global Bit line, AGT, AGT0-3 assist gate transistor, GBL_EVEN1-GBL_EVEN4 global bit line (first wiring), GBL_ODD1-GBL_ODD4 global bit line (second wiring), AG, AG0-AG3 assist gate line, CD common voltage Line, STA, STB Voltage line, MTA, MTA0 to MTA4, MTB, MTB0 to MTB3 Select transistor, VSS1 to VSS4 Shield wiring, A, B coupling capacitance.

Claims (2)

A first wiring layer;
A second wiring layer;
Each of the first wiring layer and the second wiring layer includes a first wiring and a second wiring activated when the first wiring is not activated,
In each of the first wiring layer and the second wiring layer, the first wiring and the second wiring are alternately arranged,
The first wiring and the second wiring in the first wiring layer and the first wiring and the second wiring in the second wiring layer are arranged substantially in parallel;
In the stacking direction of the first wiring layer and the second wiring layer, when the first wiring is arranged in the first wiring layer, the second wiring is formed in the second wiring layer. A semiconductor device in which the first wiring is disposed in the second wiring layer when the second wiring is disposed in the first wiring layer.   The semiconductor device according to claim 1, wherein at least one of the first wiring layer and the second wiring layer includes a shield wiring disposed between the first wiring and the second wiring.

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