JP2007188335A - Image data processor and frame memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To avoid influences due to defective cells without using redundant storage cells. <P>SOLUTION: When a defective cell 121A is included in a non-peripheral part memory area 121 inside a frame memory 12, an address of a storage cell for one word including the defective cell 121A is regarded as a defective address. When the defective address is accessed by an external address, the address of the storage cell for one word including an alternative cell to be a nondefective storage cell in a peripheral part memory area 122 inside the frame memory 12 is used as an alternative address, and the defective address is converted into the alternative address. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  According to the present invention, a defective address which is an address of a memory cell for one word including a defective cell in the non-peripheral memory area is an address of a memory cell for one word including a non-defective cell in the peripheral memory area. The present invention relates to an image data processing apparatus and a frame memory in which adverse effects due to defective cells are avoided by replacing with alternative addresses.

  FIG. 3 shows a schematic configuration of a general image data processing apparatus. The image data generation unit 11 generates an image for one frame as a pair with an address, and the data is sorted by the address and written to the frame memory 12. The video signal generation unit 13 D / A converts the image data read from the frame memory 12 to generate a video signal. The video signal is displayed on the display panel of the display device 14.

  FIG. 4 shows an array of pixel data (gradation data represented by one word consisting of a plurality of bits) stored in the frame memory 12 in correspondence with the display position of the display device 14 on the display panel. . The pixel data is associated with the pixels of the display panel (for example, one pixel in RGB in the case of color) in a 1: 1 ratio, and is given an address. In other words, the frame memory 12 is sequentially given an address as each pixel data as data in which the upper left pixel data is represented by word 0, its right pixel data is represented by word 1, and its right pixel data is represented by word 2. It is remembered. For example, in dot sequential scanning, writing and reading are performed in the order of word 0 → word 1 →... → word h−1 →... → word h × v−1. In the example of FIG. 4, the horizontal position corresponds to the display position on the display panel with h pixels and the vertical length is v pixels.

FIG. 5 is a diagram showing a case where a memory cell for one bit in the frame memory 12, for example, is a defective cell 12A. If such a defective cell 12A exists, the image data is not normally written to the word including the defective cell 12A, and a defect occurs when the written image data is read and displayed on the display panel. As a result, display image deterioration occurs. In general memory regardless of frame memory, as a method for relieving defective cells, specially prepared redundant storage cells, and when defective cells are found in manufacturing test, logically replace the redundant cells with defective cells A method is known (for example, Patent Document 1). In the replacement method, the address of the memory cell for one word including the defective cell is stored as a defective address, and when the defective address is accessed, the address of the memory cell for one word including the redundant cell is stored. It is to convert to.
JP-A-11-159592 (paragraph 0009)

  However, the above-described countermeasure requires a special provision of redundant memory cells, and there is a problem that the manufacturing cost of the frame memory increases. An object of the present invention is to avoid the effects of defective cells without using redundant storage cells.

In order to solve the above-mentioned problem, the invention according to claim 1 is an image data processing apparatus including a frame memory for storing image data for one frame, and a defective cell in a non-peripheral memory area in the frame memory. The address of the memory cell for one word including the defective address, the address of the memory cell for one word including the good cell in the peripheral memory area in the frame as the substitute address, and the defective address as the substitute address It is characterized by replacing.
According to a second aspect of the present invention, in the image data processing apparatus according to the first aspect, an external address for accessing the frame memory is compared with the defective address and the alternative address, and the frame memory is determined according to the comparison result. An address conversion unit for generating an internal address for accessing the external address, and the address conversion unit generates the alternative address as the internal address when the external address matches the defective address, and the external address is the alternative address If it matches, the defective address is generated as the internal address.
According to a third aspect of the present invention, there is provided a frame memory for storing image data for one frame, wherein a memory cell address for one word including a defective cell in a non-peripheral memory area in the frame memory is designated as a defective address The defective address is replaced with the substitute address, with the address of the memory cell for one word including the non-defective cells in the peripheral memory area in the frame as the substitute address.
The invention according to claim 4 is the frame memory invention according to claim 3, wherein an external address for accessing the frame memory is compared with the defective address and the alternative address, and the frame memory is accessed according to the comparison result. An address conversion unit that generates an internal address that generates the alternative address as the internal address when the external address matches the defective address, and the external address matches the alternative address In this case, the defective address is generated as the internal address.

  According to the present invention, since a defective address is converted into an alternative address, an adverse effect due to a defective cell can be avoided. In addition, since the non-defective cell selected by the alternative address is a memory cell in the peripheral memory area of the frame memory, it is not necessary to provide a special redundant memory cell.

  FIG. 1 is a block diagram showing a main part of an image data processing apparatus according to one embodiment of the present invention. An address conversion unit 10 converts a specific address among external addresses accessed from the outside into a specific internal address, and accesses the frame memory 12. An address comparison unit 101, a multiplexer (selector) 102, a defective address storage unit 103, and an alternative address storage unit 104 are provided. Here, the configuration other than the address system is omitted because it is the same as the conventional one.

  In the defective address storage unit 103, for example, as shown in FIG. 2, if there is a defective cell 121A among a plurality of memory cells in the non-peripheral memory area 121 of the frame memory 12, the defective cell is displayed during the manufacturing test. 121A is found, and the address of the memory cell for one word (one image data) including the defective cell 121A is stored as the defective address A2. Further, in the alternative address storage unit 104, an address of a storage cell for one word including an arbitrary non-defective cell 122A in the peripheral memory area 122 of the frame memory 12 is stored as an alternative address A3.

  For example, when a video signal is generated according to the NTSC standard in the video signal generation unit 13 and displayed on the display device 14, there is an area (non-display area) that is not displayed in the periphery of the frame. In the present invention, a memory area corresponding to this peripheral part is used as the peripheral part memory area 122, and an alternative address is set in this peripheral part memory area 122. In the present invention, when an alternative address is replaced with a defective address, pixel data at a position corresponding to the alternative address is not normally stored. However, in the case of pixel data in a non-display area that is not actually displayed, the display image does not deteriorate even if it is not stored normally. Note that, even if there is no non-display area, it is generally difficult for human eyes to stand out even if it is not normally displayed as long as it is a pixel in the peripheral part of the frame. Therefore, even when there is no non-display area, an alternative address is set in the peripheral memory area 122 of the frame memory 12 and replaced with a conspicuous non-peripheral defective address, thereby reducing display image deterioration. Or can be substantially prevented.

  Here, referring back to FIG. 1, the address converter 10 of the present invention will be further described. The address comparison unit 101 takes in the external address A1, the defective address A2, and the alternative address A3, outputs “0” when A1 = A2, outputs “1” when A1 = A3, and satisfies A1 ≠ A2 ≠ A3 "2" is output. The multiplexer 102 selects the input ports “0”, “1”, “2” according to the outputs “0”, “1”, “2” from the address comparison unit 101, and outputs the internal address A0.

  As described above, when the external address A1 matches the defective address A2, the alternative address A3 is selected as the internal address A0. When the external address A1 matches the alternative address A3, the defective address A2 is selected as the internal address A0. If the external address A1 does not match either the defective address A2 or the alternative address A3, the external address A1 is used as it is as the internal address A0.

  Therefore, even if a defective cell 121A exists in the non-peripheral memory area 121 of the frame memory 12, when the defective cell 121A is accessed, a memory cell for one word including the defective cell 121A is selected. The defective address is converted into an alternative address for selecting a memory cell for one word including a good alternative cell 122A. For this reason, image data represented by one word can be normally written. Since address conversion is performed in the same manner when reading, normal image display can be performed.

  Further, when accessing the alternative cell 122A, the alternative address for selecting the pixel cell for one word including the alternative cell 122A is converted into a defective address for selecting the storage cell for one word including the defective cell 121A. . However, the image data written here is not actually displayed on the display panel, or is displayed in a peripheral portion that is not easily noticeable, so that no inconvenience occurs. Thus, when image data is written to or read from the frame memory 12, there is no need to change the external dress at all, and the response to the randomly generated defective cells 121 is in accordance with the individual frame memory 12. It is only necessary to set a defective address in the address storage unit 103 and set an alternative address in the alternative address storage unit 104.

  In the embodiment described above, the case where there is one defective cell in the non-peripheral memory area 121 of the frame memory 12 has been described. However, when there are a plurality of defective cells, a plurality of defective cells are stored in the peripheral memory area 122. An alternative cell may be allocated.

  The address conversion unit 10 is formed on the same semiconductor chip as the frame 12 and stores the defective address and the alternative address found in the manufacturing test in the defective address storage unit 103 and the alternative address storage unit 104. It is also possible to sell as a frame memory having Alternatively, the address conversion unit 10 may be formed on another chip and used in combination with the frame memory 12 having no address conversion function. In the latter case, the defective address and alternative address found in the acceptance test of the frame memory 12 are stored in the defective address storage unit 103 and the alternative address storage unit 104.

  One frame memory 12 may have a capacity capable of storing RGB pixel data. Alternatively, three frame memories that can store any of RGB data may be used in combination. The frame memory 12 has a capacity for storing image data for at least one frame, but may have a capacity larger than that. For example, image data of two frames or more may be stored.

It is a block diagram of the principal part of the image data processing apparatus of this invention. It is explanatory drawing of a frame memory. It is a block diagram of a general image data processing device. It is explanatory drawing of a frame memory. It is explanatory drawing of a frame memory.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10: Address conversion part, 101: Address comparator, 102: Multiplexer, 103: Defect address storage part, 104: Alternative address storage part 11: Image data generation part 12: Frame memory, 121: Memory area for non-peripheral parts, 122 : Peripheral area memory area, 121A: defective cell, 122A: alternative cell 13: video signal generator 14: display device

Claims (4)

In an image data processing apparatus having a frame memory for storing image data for one frame,
The address of the memory cell for one word including the defective cell in the non-peripheral memory area in the frame memory is defined as a defective address, and the memory cell for one word including the non-defective cell in the peripheral memory area in the frame is used. An image data processing apparatus, wherein an address is used as an alternative address, and the defective address is replaced with the alternative address. An external address for accessing the frame memory is compared with the defective address and the alternative address, and an address conversion unit for generating an internal address for accessing the frame memory according to the comparison result is provided.
The alternative address is generated as the internal address when the external address matches the defective address, and the defective address is generated as the internal address when the external address matches the alternative address. The image data processing apparatus according to claim 1. A frame memory for storing image data for one frame,
The address of the memory cell for one word including the defective cell in the non-peripheral memory area in the frame memory is defined as a defective address, and the memory cell for one word including the non-defective cell in the peripheral memory area in the frame is used. A frame memory, wherein an address is used as an alternative address, and the defective address is replaced with the alternative address. An external address for accessing the frame memory is compared with the defective address and the alternative address, and an address conversion unit for generating an internal address for accessing the frame memory according to the comparison result is provided.
The alternative address is generated as the internal address when the external address matches the defective address, and the defective address is generated as the internal address when the external address matches the alternative address. The frame memory according to claim 3.

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