JP2007150234A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

A semiconductor device having a FUSI structure having a uniform composition without depending on a gate length and a method for manufacturing the same can be realized.
In a semiconductor device having a first gate electrode and a second gate electrode with different FUSI gate lengths, the first gate electrode is connected to a second sidewall spacer. The first sidewall spacers 106 are sequentially formed, and the upper end of the first sidewall spacer 105 is lower than the upper surface of the first gate electrode 14T1 and the upper end of the second sidewall spacer 106, and the first sidewall spacer 106 is formed. The etching characteristics of 105 and the second sidewall spacer 106 are different from each other. Also in the second gate electrode 14T2, the upper end of the first sidewall spacer 105 is lower than the upper surface of the second gate electrode 14T2 and the upper end of the second sidewall spacer 106.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor device including a field effect transistor having a fully silicided (FUSI) structure and a manufacturing method thereof.

  2. Description of the Related Art Conventionally, the degree of integration of semiconductor elements integrated in a semiconductor integrated circuit device has increased. For example, a gate electrode constituting a field-effect transistor (FET) is finely formed. At the same time, a method of realizing an electrical thinning of the gate insulating film by using a high dielectric material as an insulating film material of the gate insulating film is being used. However, normally, polysilicon used for the gate electrode cannot be depleted even if impurity implantation is performed, and the gate insulating film thickness is electrically increased by the depletion, so that the performance of the FET It is a factor that hinders improvement.

  In recent years, gate electrode structures that can prevent depletion of the gate electrode have been proposed. For example, a full silicide (FUSI) structure in which a metal material is reacted with a silicon material forming the gate electrode to silicide the entire silicon material has been reported as an effective method for suppressing depletion of the gate electrode.

Non-Patent Document 1 listed below describes a method for forming a FUSI structure. Non-Patent Document 2 proposes a structure in which different materials are used for the FUSI electrode in the N-type FET and the P-type FET, for example, NiSi is used for the N-type FET and Ni ₃ Si is used for the P-type FET. .

  FIG. 23A to FIG. 23D show the cross-sectional configuration of the main part in the process of forming the FUSI electrode in the conventional MIS type FET manufacturing method shown in Non-Patent Document 1.

  First, as shown in FIG. 23A, an element isolation film 2 is formed on an upper part of a semiconductor substrate 1 made of silicon, and then N-type FET regions A and P partitioned by the element isolation film 2 of the semiconductor substrate 1 are formed. A gate insulating film 3 and a conductive polysilicon film are sequentially formed on the type FET region B. Subsequently, the formed polysilicon film is patterned to form a first gate electrode formation film 4A in the N-type FET region A, and a second gate electrode formation film 4B in the P-type FET region B. . Subsequently, insulating sidewall spacers 5 are formed on the side surfaces of the gate electrode formation films 4A and 4B, and the source / drain regions 6 are formed in the active region of the semiconductor substrate 1 using the formed sidewall spacers 5 as a mask. Respectively. Subsequently, an interlayer insulating film 7 is formed on the semiconductor substrate 1 so as to cover the gate electrode forming films 4A and 4B and the sidewall spacers 5, and the formed interlayer insulating film 7 is subjected to chemical mechanical polishing (CMP). Each gate electrode formation film 4A, 4B is exposed by a method or the like.

  Next, as shown in FIG. 23B, a resist pattern 8 that opens the P-type FET region B is formed on the interlayer insulating film 7, and the interlayer of the p-type FET region B is formed using the formed resist pattern 8 as a mask. The upper part of the second gate electrode formation film 4B exposed from the insulating film 7 is removed by etching.

  Next, as shown in FIG. 23C, after removing the resist pattern 8, a metal film 9 made of nickel is deposited on the interlayer insulating film 7 exposing the gate electrode formation films 4A and 4B.

  Next, as shown in FIG. 23D, a heat treatment is performed on the semiconductor substrate 1 so that the gate electrode formation films 4A and 4B made of polysilicon react with each other and the metal film 9 to react with each other. A first gate electrode 10A whose upper part is silicided is formed in the FET region A, and a second gate electrode 10B which is fully silicided is formed in the P-type FET region B. In Non-Patent Document 1, a part of the gate electrode formation film 4A made of polysilicon remains below the first gate electrode 10A constituting the N-type FET, and the second gate electrode constituting the P-type FET. The gate electrode formation film 4B made of polysilicon does not remain below 10B, and is all made of NiSi.

Non-Patent Document 2 describes a configuration in which the entire first gate electrode 10A is NiSi and the entire second gate electrode 10b is Ni ₃ Si by depositing a thick metal film. .
2004 IEEE, Proposal of New HfSiON CMOS Fabrication Process (HAMDAMA) for Low Standby Power Device, T. Aoyama et.al 2004 IEEE, Dual Workfunction Ni-Silicide / HfSiON Gate Stacks by Phase-Controlled Full-Silicidation (PC-FUSI) Technique for 45nm-node LSTP and LOP Devices, K. Takahashi et.al

  As a result of various studies on the conventional FUSI structure, the inventor of the present application has found a phenomenon that the full silicidation of the polysilicon film for forming the gate electrode becomes non-uniform when the gate electrode in the MISFET is made FUSI. It was. This phenomenon is particularly noticeable when the gate length is relatively large. FIG. 24A and FIG. 24B show this phenomenon.

  As shown in FIG. 24A, a first gate electrode formation film 4C made of polysilicon and a gate length longer than those of the first gate electrode formation film 4C are formed on the active region of the semiconductor substrate 1, respectively. 2 gate electrode formation film 4D. In this case, in the conventional silicidation process of the gate electrode, not only the metal atoms diffuse into the polysilicon from the metal film 9 deposited on the respective gate electrode formation films 4C and 4D, but also the sidewall spacers 5 Metal is also supplied into the polysilicon from the upper side and the vicinity thereof. That is, as a result of excessive supply of metal from both sides in the gate length direction deposited on the gate electrode formation films 4C and 4D, silicidation is overreacted in the vicinity of the sidewall spacer 5 in each polysilicon. Become.

  Accordingly, as shown in FIG. 24B, when the first gate electrode forming film 4C having a relatively small gate length is changed to FUSI to form the first gate electrode 10C having a desired composition ratio, The second gate electrode formation film 4D having a relatively large gate length cannot be entirely silicided, and the second gate electrode formation film made of polysilicon is formed under the silicided second gate electrode 10D. A part of 4D remains.

  On the other hand, when the second gate electrode 10D is formed by converting the second gate electrode formation film 4D having a relatively large gate length to FUSI, the first gate electrode formation film 4C having a relatively small gate length is formed on the first gate electrode formation film 4C. Since the metal is supplied excessively, the first gate electrode 10C rich in metal than the desired composition ratio is formed.

  Further, when the second gate electrode formation film 4D having a relatively large gate length is made into FUSI, the upper portion of the polysilicon is not formed in the central portion away from the polysilicon sidewall spacer 5 constituting the second gate electrode formation film 4D. Only the metal deposited on the part is supplied. On the other hand, not only the metal deposited on the upper part of the polysilicon but also the upper part of each side wall spacer 5 and the vicinity thereof in the vicinity of the polysilicon adjacent to the sidewall spacer 5. Is supplied in polysilicon. Accordingly, the second gate electrode 10 </ b> D has a non-uniform composition because the metal portion in the vicinity adjacent to the sidewall spacer 5 is richer than the central portion separated from the sidewall spacer 5. As described above, in the FET having a relatively large gate length, the composition of the gate electrode is different between the vicinity of the sidewall spacer 5 and the central portion of the gate electrode. Become.

  Further, when the conventional FUSI method is applied to the resistance element or the upper electrode of the capacitive element, the resistance value varies in the case of the resistive element, and the capacitance value varies in the case of the capacitive element.

  An object of the present invention is to solve the above-mentioned conventional problems and to realize a semiconductor device having a FUSI structure having a uniform composition without depending on the gate length and a method for manufacturing the same.

  In order to achieve the above object, the present invention provides a semiconductor device and a method for manufacturing the same, including a first sidewall spacer and a second sidewall spacer provided on a side surface of the gate electrode from the gate electrode side. A stacked structure is employed, and an upper portion of the first sidewall in contact with the gate electrode is removed, so that a gap is provided between the second sidewall spacer and the side surface of the gate electrode.

  Specifically, the semiconductor device according to the present invention is directed to a semiconductor device including a first MIS transistor having a first gate electrode that is fully silicided with a metal. The first MIS transistor is a semiconductor device. A first gate insulating film formed on the region; a first gate electrode formed on the first gate insulating film; and a first sidewall spacer formed on a side surface of the first gate electrode And a second sidewall spacer formed on the side surface of the first gate electrode with a first sidewall spacer interposed therebetween. The first sidewall spacer and the second sidewall spacer are The etching characteristics are different from each other, and the upper end of the first sidewall spacer is lower than the upper surface of the first gate electrode and the upper end of the second sidewall spacer. Characterized in that it is.

  According to the semiconductor device of the present invention, the upper end of the first sidewall spacer formed on the side surface of the first gate electrode is lower than the upper surface of the first gate electrode and the upper end of the second sidewall spacer. A gap is generated between the side surface of the first gate electrode and the second sidewall. Thus, in the silicidation process performed by depositing a metal film on the first gate electrode including the sidewall, the deposition is caused by the gap between the second sidewall on both side surfaces of the first gate electrode. The formed metal film is cut off on the gate electrode or the film thickness is reduced. Therefore, only the metal located above the first gate electrode is supplied, and the metal is hardly supplied from other regions. Therefore, the composition of the FUSI gate electrode becomes uniform regardless of the size (gate length dimension) of the first gate electrode.

  In the semiconductor device of the present invention, it is preferable that the upper end of the second sidewall spacer is higher than the upper surface of the first gate electrode.

  The semiconductor device of the present invention further includes a second MIS type transistor having a second gate electrode that is fully silicided with a metal and has a gate length larger than that of the first gate electrode. Includes a second gate insulating film formed on the semiconductor region, a second gate electrode formed on the second gate insulating film, and a first gate electrode formed on the side surface of the second gate electrode. A side wall spacer and a second side wall spacer formed on the side surface of the second gate electrode with the first side wall spacer interposed, and the upper end of the first side wall spacer is Are formed lower than the upper surface of the gate electrode and the upper end of the second sidewall spacer, and the conductivity type of the first MIS transistor and the conductivity type of the second MIS transistor are Identical it is preferable that.

  In this case, it is preferable that the top surface of the first gate electrode and the top surface of the second gate electrode have the same height from the top surface of the semiconductor region.

  In this case, it is preferable that the first gate electrode and the second gate electrode have the same composition.

  The semiconductor device of the present invention further includes a third MIS transistor having a third gate electrode that is fully silicided with a metal, and the third MIS transistor is a third gate formed on the semiconductor region. An insulating film; a third gate electrode formed on the third gate insulating film; a first sidewall spacer formed on a side surface of the third gate electrode; and a side surface of the third gate electrode. And the second sidewall spacer formed with the first sidewall spacer interposed therebetween, and the upper end of the first sidewall spacer is the upper surface of the third gate electrode and the second sidewall spacer. Preferably, the conductivity type of the first MIS transistor is different from the conductivity type of the third MIS transistor.

  In this case, it is preferable that the first gate electrode and the third gate electrode have different compositions.

  The semiconductor device of the present invention further includes a resistor element having a resistor that is fully silicided with a metal. The resistor element includes a resistor formed on an element isolation region provided on the semiconductor region, and a resistor element. A first sidewall spacer having a first sidewall spacer formed on the side surface; and a second sidewall spacer formed on the side surface of the resistor with the first sidewall spacer interposed therebetween. It is preferable that the upper end of is formed lower than the upper surface of the second resistor and the upper end of the second sidewall spacer.

  In this case, it is preferable that the first gate electrode and the resistor have the same composition.

  The semiconductor device of the present invention further includes a capacitive element having an upper electrode that is fully silicided with a metal. The capacitive element includes a capacitive insulating film formed on the semiconductor region and an upper electrode formed on the capacitive insulating film. And a first sidewall spacer formed on the side surface of the upper electrode, and a second sidewall spacer formed on the side surface of the upper electrode with the first sidewall spacer interposed therebetween, The upper end of one sidewall spacer is preferably formed lower than the upper surface of the upper electrode and the upper end of the second sidewall spacer.

  In this case, it is preferable that the first gate electrode and the upper electrode have the same composition.

  A method for manufacturing a semiconductor device according to the present invention is directed to a method for manufacturing a semiconductor device including a first MIS transistor having a first gate electrode on a first gate insulating film. (A) forming a first gate insulating film, (b) forming a first gate silicon film on the first gate insulating film, and a first on the side surface of the first gate silicon film. A step (c) of forming a second side wall spacer, a step (d) of forming a second side wall spacer with the first side wall spacer interposed on the side surface of the first gate silicon film, and a step After (d), etching is performed on the first sidewall spacer, and the height of the upper end of the first sidewall spacer is set to the upper surface of the first gate silicon film and the second sidewall spacer. The step (e) of lowering the upper end, the step (f) of forming a metal film on the first gate silicon film after the step (e), and the first gate silicon film with the metal film And a step (g) of forming a first gate electrode by full silicidation.

  According to the method of manufacturing a semiconductor device of the present invention, the first gate silicon film is formed, and the first sidewall spacer and the first sidewall spacer are interposed on the side surface of the formed first gate silicon. Second sidewall spacers are sequentially formed. Subsequently, etching is performed on the first sidewall spacer so that the height of the upper end of the first sidewall spacer is lower than the upper surface of the first gate electrode. In the step of forming the metal film on the first gate electrode, a gap is generated between both side surfaces of the first gate electrode and the second sidewall. Since the deposited metal film is cut off on the first gate electrode or the film thickness is reduced by this gap, only the metal located above the first gate electrode is supplied to other regions. Almost no metal is supplied. Therefore, the composition of the FUSI gate electrode can be made uniform regardless of the size (gate length dimension) of the first gate electrode. Further, conventionally, stress is applied to the semiconductor region due to the difference in expansion rate or shrinkage rate between the gate electrode material and the side wall spacer material generated during the heat treatment in the film forming process of the interlayer insulating film or the like. This stress is greatly relieved by the gap formed on the side surface of the gate electrode. Therefore, variations in transistor characteristics due to stress due to FUSI can be prevented.

  In the method for manufacturing a semiconductor device of the present invention, the step (b) includes a step of forming a protective insulating film on the first gate silicon film, and the step (c) includes the first gate silicon film and the protection. Forming a first sidewall spacer on the side surface of the insulating film, and the step (d) includes interposing the first sidewall spacer on the side surface of the first gate silicon film and the protective insulating film; Preferably, the method includes a step of forming a second sidewall spacer, and step (e) preferably includes a step of etching the protective insulating film to expose the upper surface of the first gate silicon film. .

  In the method for manufacturing a semiconductor device of the present invention, the semiconductor device further includes a second MIS transistor having a second gate electrode having a gate length larger than that of the first gate electrode on the second gate insulating film. The step (a) includes a step of forming a second gate insulating film on the semiconductor region, and the step (b) includes a step of forming a second gate silicon film on the second gate insulating film. Step (c) includes forming a first sidewall spacer on the side surface of the second gate silicon film, and step (d) includes forming the first side wall spacer on the side surface of the second gate silicon film. Forming a second sidewall spacer by interposing the first sidewall spacer, wherein the step (e) etches the first sidewall spacer to form the first sidewall spacer; The step (f) includes a step of making the height of the upper end lower than the upper surface of the second gate silicon film and the upper end of the second sidewall spacer, and the step (f) forms a metal film on the second gate silicon film. Preferably, the step (g) includes a step of forming a second gate electrode by fully siliciding the second gate silicon film with a metal film.

  In the method for manufacturing a conductor device of the present invention, the semiconductor device further includes a third MIS transistor having a third gate electrode having a composition different from the composition of the first gate electrode on the third gate insulating film. The step (a) includes a step of forming a third gate insulating film on the semiconductor region, and the step (b) includes a step of forming a third gate silicon film on the third gate insulating film. Step (c) includes forming a first sidewall spacer on the side surface of the third gate silicon film, and step (d) includes forming the first side wall spacer on the side surface of the third gate silicon film. Forming a second sidewall spacer by interposing the first sidewall spacer, wherein the step (e) etches the first sidewall spacer to form the first sidewall spacer; The step (f) includes a step of lowering the height of the upper end lower than the upper surface of the third gate silicon film and the upper end of the second sidewall spacer, and the step (f) includes forming a metal film on the third gate silicon film. The step (g) includes a step of forming a third gate electrode by fully siliciding the third gate silicon film with a metal film, and the step (f) is a step (f) after the step (b). Before the step (h), the third gate silicon film is etched to make the height of the upper surface of the third gate silicon film lower than that of the first gate silicon film. Furthermore, it is preferable to provide.

  In the semiconductor device manufacturing method of the present invention, the semiconductor device further includes a third MIS transistor having a third gate electrode having a composition different from the composition of the first gate electrode on the third gate insulating film. The step (a) includes a step of forming a third gate insulating film on the semiconductor region, and the step (b) includes a step of forming a third gate silicon film on the third gate insulating film. And step (c) includes forming a first sidewall spacer on the side surface of the third gate silicon film, and step (d) includes forming the first side wall spacer on the side surface of the third gate silicon film. A step of forming a second sidewall spacer by interposing one sidewall spacer, and the step (e) performs etching on the first sidewall spacer to form an upper surface of the first sidewall spacer. Is made lower than the upper surface of the third gate silicon film and the upper end of the second sidewall spacer, and after the step (e), another metal is formed on the third gate silicon film. Preferably, the method further includes a step (i) of forming a film and a step (j) of forming a third gate electrode by fully siliciding the third gate silicon film with another metal film.

  In the method for manufacturing a semiconductor device of the present invention, the semiconductor device further includes a resistor element having a resistor, and further includes a step (k) of forming an element isolation region above the semiconductor region before the step (a). The step (b) includes a step of forming a resistance silicon film on the element isolation region, and the step (c) includes a step of forming a first sidewall spacer on the side surface of the resistance silicon film. The step (d) includes a step of forming a second sidewall spacer by interposing a first sidewall spacer on the side surface of the resistance silicon film, and the step (e) includes a first sidewall spacer. Etching to lower the height of the upper end of the first sidewall spacer lower than the upper surface of the resistance silicon film and the upper end of the second sidewall spacer, f) includes a step of forming a metal film on the resistor silicon film, and step (g) includes a step of forming a resistor by fully siliciding the resistor silicon film with the metal film. preferable.

  In the method for manufacturing a semiconductor device of the present invention, the semiconductor device further includes a capacitor element having an upper electrode, and the step (a) includes a step of forming a capacitor insulating film on the semiconductor region, and the step (b) Forming a capacitor silicon film on the capacitor insulating film; step (c) includes forming a first sidewall spacer on a side surface of the capacitor silicon film; and step (d) Forming a second side wall spacer with a first side wall spacer interposed on the side surface of the silicon film, and the step (e) performs etching on the first side wall spacer, The step (f) includes a step of making the height of the upper end of the first sidewall spacer lower than the upper surface of the capacitor silicon film and the upper end of the second sidewall spacer, and the step (f) Includes the step of forming a metal film above, the step (g), it preferably includes the step of forming an upper electrode fully silicided with a metal film of the silicon film capacitor.

  According to the semiconductor device and the method of manufacturing the same of the present invention, a FUSI structure having a uniform gate electrode composition can be obtained regardless of the gate length dimension of the gate electrode, so that variations in threshold voltage can be suppressed. In addition, variations in transistor characteristics due to stress due to FUSI via sidewall spacers can be prevented.

(First embodiment)
A first embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 shows a cross-sectional configuration of a semiconductor device according to the first embodiment of the present invention. As shown in FIG. 1, the main surface of a semiconductor substrate 101 made of, for example, silicon (Si) is provided with an FET formation region T, a resistance element formation region R, and a capacitive element by an element isolation region 102 made of shallow trench isolation (STI). The formation region C is partitioned and formed. Here, the resistance element formation region R is provided on the element isolation region 102.

  In the FET formation region T, the first N-type FET 11 and the second N-type FET 12 having different gate lengths are formed, and in the resistance element formation region R, the first resistance element 21 and the second N-type having different widths are formed. The first capacitive element 31 and the second capacitive element 32 having different upper electrode widths are formed in the capacitive element forming region C.

The first N-type FET 11 and the second N-type FET 12 in the FET forming region T are formed on the semiconductor substrate 101 and on the gate insulating film 103, respectively, and are fully silicided. A first gate electrode 14T1 made of (FUSI) metal silicide, a second gate electrode 14T2 having a larger gate length than the first gate electrode 14T1, and both side surfaces of the gate electrodes 14T1 and 14T2 are sequentially formed. The formed first sidewall spacer 105 made of, for example, silicon oxide (SiO ₂ ) and _second sidewall spacer 106 made of silicon nitride (Si ₃ N ₄ ), and the gate electrodes 14T1 and 14T2 in the semiconductor substrate 101 are formed. N-type electrodes formed in the lateral regions and implanted with N-type impurity ions. And Pensions region 104, respectively formed in a region on the side of the second sidewall spacer 106 in the semiconductor substrate 101 is constituted by an N-type source and drain regions 107 N-type impurity ions is formed by injection.

  The first resistance element 21 and the second resistance element 22 in the resistance element formation region R are wider than the first resistance body 14R1 and the first resistance body 14R1 each made of FUSI-formed metal silicide. The second resistor 14R2 is composed of a first sidewall spacer 105 and a second sidewall spacer 106 that are sequentially formed on both side surfaces of the resistors 14R1 and 14R2.

  The first capacitive element 31 and the second capacitive element 32 in the capacitive element formation region C are MIS type capacitive elements, and a capacitive insulating film 113 formed on the semiconductor substrate 101 and the capacitive insulating film, respectively. 113, a first upper electrode 14C1 made of FUSI-formed metal silicide, a second upper electrode 14C2 having a larger width than the first upper electrode 14C1, and both sides of each of the upper electrodes 14C1 and 14C2 The first sidewall spacer 105 and the second sidewall spacer 106 sequentially formed on the surface, the regions on the sides of the upper electrodes 14C1 and 14C2 in the semiconductor substrate 101, and the lower side of the capacitor insulating film 113 are formed. , And a lower electrode 117 into which N-type impurity ions are implanted. The lower electrode 117 is formed on the lower side of the capacitor insulating film 113 in the semiconductor substrate 101, and has an N-type region 116 into which N-type impurity ions are implanted, and a lateral side of each of the upper electrodes 14 C 1 and 14 C 2 in the semiconductor substrate 101. An N-type region 104C formed in each region and implanted with N-type impurity ions and a region formed laterally to the second sidewall spacer 106 in the semiconductor substrate 101 are implanted with N-type impurity ions. The N-type region 107 </ b> C thus formed.

  As a feature of the first embodiment, the upper ends of the first sidewall spacers 105 formed on both side surfaces in the gate length direction of the gate electrodes 14T1 and 14T2 which are made FUSI are formed at the upper ends of the gate electrodes 14T1 and 14T2. It is formed lower than the upper surface and the upper end of the second sidewall spacer 106. Similarly, in each of the resistors 14R1 and 14R2 and the upper electrodes 14C1 and 14C2 that are made FUSI, the upper ends of the first sidewall spacers 105 formed on the respective side surfaces are the upper surfaces of the resistors 14R1 and 14R2. The upper electrodes 14 </ b> C <b> 1, 14 </ b> C <b> 2 are formed lower than the upper surfaces of the second sidewall spacers 106.

  In FIG. 1, for convenience, two FETs 11 and 12, resistance elements 21 and 22, and capacitive elements 31 and 32 are shown, but more elements are formed on the semiconductor substrate 101.

  FIG. 2A shows a planar configuration of the first gate electrode 14T1 that is made FUSI in the semiconductor device according to the first embodiment, and FIG. 2B shows a sectional configuration taken along the line IIb-IIb in FIG. Show. In FIG. 2, the same components as those shown in FIG. A wide portion of the first gate electrode 14T1 shown in FIG. 2A is a contact formation portion formed on the element isolation region 102. As shown in FIG. 2A, a first sidewall spacer 105 and a second sidewall spacer 106 are sequentially stacked around the first gate electrode 14T1 from the first gate electrode 14T1 side. Is formed. Further, as shown in FIG. 2B, a gap 105a formed between the first gate electrode 14T1 and the second sidewall spacer 106 is formed above the first sidewall spacer 105. ing. Here, the first gate electrode 14T1 of the N-type FET is shown as an example, but the first and second resistors 14R1 and 14R2 and the capacitors of the resistance elements 21 and 22 including the second gate electrode 14T2 are included. The first and second upper electrodes 14C1 and 14C2 of the elements 31 and 32 have the same structure.

  With this configuration, in the semiconductor device according to the first embodiment, each of the gate electrodes 14T1 and 14T2, each of the resistors 14R1 and 14R2 and each of the upper electrodes 14C1 and 14C2 that are made of FUSI and have the same structure, Regardless of the size (planar dimensions) of the gate electrodes 14T1 and 14T2, the resistors 14R1 and 14R2, and the upper electrodes 14C1 and 14C2, they have the same composition in a self-aligning manner. For this reason, for example, in the N-type FETs 11 and 12, it is possible to prevent variation in threshold voltage due to non-uniform composition due to the size of the first gate electrode 14T1 and the second gate electrode 14T2. In addition, variation in resistance value is also prevented in each of the resistance elements 21 and 22, and variation in capacitance value is also prevented in each capacitance element. As a result, improvement in performance and high integration of the semiconductor device can be realized.

  In FIG. 1, a semiconductor in which a first N-type FET 11 and a second N-type FET 12, and a first capacitive element 31 and a second capacitive element 32 are partitioned by an element isolation region 102. Although an example of forming in the same region made of the substrate 101 has been shown, each element may be formed in a region partitioned by the element isolation region 102 alone. Further, any two kinds of elements may be combined in the same region. Moreover, although the example which forms the 1st resistive element 21 and the 2nd resistive element 22 adjacent on the element isolation region 102 was shown, you may form on the element isolation region 102 mutually spaced apart. . The N-type FETs 11 and 12 may be P-type FETs. Further, the element to be formed is not limited to an FET, a resistance element, and a capacitor element, and other elements using a conductor having a FUSI structure, such as a fuse element, can be formed.

  Hereinafter, a method of manufacturing the semiconductor device configured as described above will be described with reference to the drawings.

  FIG. 3A and FIG. 3B to FIG. 6 show cross-sectional structures in the order of steps of the semiconductor device manufacturing method according to the first embodiment of the present invention.

First, as shown in FIG. 3A, an element isolation region 102 made of STI is formed on a semiconductor substrate 101 made of silicon, and then, for example, N-type impurity ions are selected for the capacitor element formation region C. Thus, an N-type region 116 that becomes a part of the lower electrode 117 is formed on the semiconductor substrate 101. The N-type region 116 becomes the lower electrode 117 immediately below the capacitor insulating film 113. Thereafter, the FET formation region T and the capacitor element formation region C on the main surface of the semiconductor substrate 101 are each made of hafnium oxide (HfO ₂ ) having a physical thickness of 3 nm by a chemical vapor deposition (CVD) method. A gate insulating film 103 and a capacitor insulating film 113 are deposited. Here, an insulating film made of hafnium oxide may be formed on the element isolation region 102 in the resistance element formation region R. Subsequently, by CVD, the gate insulating film 103 is interposed in the FET forming region T on the semiconductor substrate 101, and the capacitive insulating film 113 is interposed in the capacitive element forming region C, so that the film thickness is 75 nm. The conductive polysilicon film 114 and the protective insulating film 115 made of silicon oxide (SiO ₂ ) having a thickness of 25 nm are sequentially deposited. Note that conductive amorphous silicon can also be used for the polysilicon film 114. Thereafter, a resist pattern that masks the gate electrode formation region in the FET formation region T, the resistor formation region in the resistor element formation region R, and the upper electrode formation region in the capacitor element formation region C on the protective insulating film 115 by lithography. (Not shown). Subsequently, the protective insulating film 115 and the polysilicon film 114 are patterned by etching using the formed resist pattern as a mask to form first and second gate electrode patterns having different gate lengths in the FET formation region T, and the resistance element In the formation region R, first and second resistor patterns having different widths are used, and in the capacitor element formation region C, first and second upper electrode patterns having different widths are used. Here, when a dry etching method is used for etching, as an etching gas, for example, a gas mainly containing fluorocarbon can be used for silicon oxide, and a gas mainly containing chlorine can be used for polysilicon. . Subsequently, a silicon oxide film having a film thickness of 5 nm is deposited on the semiconductor substrate 101 so as to cover the patterned polysilicon film 114 and the protective insulating film 115 by the CVD method. By etching back, first sidewall spacers 105 made of silicon oxide are formed on both side surfaces of each gate electrode pattern, each resistor pattern, and each upper electrode pattern.

  Next, as shown in FIG. 3B, an N-type extension region 104 is formed in the FET formation region T by implanting N-type impurity ions into the semiconductor substrate 101 using each protective insulating film 115 as a mask. In the capacitive element formation region C, an N-type region 104C that becomes a part of the lower electrode 117 is formed. Thereafter, for example, a silicon nitride film is deposited on the semiconductor substrate 101 so as to cover the polysilicon film 114 and the protective insulating film 115 on which the first sidewall spacers 105 are formed, by the CVD method. Etchback is performed on the silicon nitride film to form second sidewall spacers 106 with the first sidewall spacers 105 interposed on both side surfaces of the polysilicon films 114 and the protective insulating film 115, respectively. Subsequently, N-type impurity ions are implanted into the semiconductor substrate 101 using each protective insulating film 115, the first sidewall spacer 105, and the second sidewall spacer 106 as a mask, so that an N-type impurity is formed in the FET formation region T. A source / drain region 107 is formed, and an N-type region 107 </ b> C that becomes a part of the lower electrode 117 is formed in the capacitor element formation region C. Thus, a source / drain region including an N-type extension region 104 and an N-type source / drain region 107 is formed in the FET formation region T, and an N-type region 104C, an N-type region 107C, and an N-type region are formed in the capacitor element formation region C. A lower electrode 117 composed of the mold region 116 is formed. Thereafter, the surfaces of the N-type source / drain region 107 and the N-type region 107C in the lower electrode 117 may be silicided with nickel (Ni) or the like. Here, the first sidewall spacer 105 is formed only on the side surfaces of the gate insulating film 103, the polysilicon film 114, and the protective insulating film 115, for example, but the lower portion of the first sidewall spacer 105 is the second sidewall spacer 105. The side wall spacer 106 may have an L-shaped cross section bent between the bottom of the side wall spacer 106 and the semiconductor substrate 101. Further, although the second sidewall spacer 106 is made of silicon nitride, it may have a two-layer structure made of silicon oxide and silicon nitride, or a three-layer structure made of silicon oxide, silicon nitride, and silicon oxide.

  Next, as shown in FIG. 4A, an interlayer insulating film made of, for example, silicon oxide so as to cover the protective insulating film 115 and the side wall spacers 105 and 106 on the semiconductor substrate 101 by the CVD method. 108 is deposited, and the deposited interlayer insulating film 108 is planarized by, for example, a chemical mechanical polishing (CMP) method to expose the upper surface of each protective insulating film 115.

Next, as shown in FIG. 4B, the respective protective insulating films 115 are removed by wet etching, for example, and the polysilicon films 114 located below the respective protective insulating films 115 are exposed. At this time, since both the first sidewall 105 and the protective insulating film 115 are made of silicon oxide, etching is performed so that the upper end of each first sidewall spacer 105 is lower than the upper surface of the polysilicon film 114 adjacent thereto. To do. At this time, the distance from the upper surface of the polysilicon film 114 to the upper end of the first sidewall spacer 105 (the depth of the gap 105a) is equal to or greater than the width of the first sidewall spacer 105. It is preferable. In the first embodiment, since the interlayer insulating film 108 is formed of silicon oxide, the interlayer insulating film 108 is also etched at the same time when the protective insulating film 115 and the first sidewall spacer 105 are etched. However, even if the interlayer insulating film 108 is etched at the same time, there is no particular problem because the etching can be controlled so that the semiconductor substrate 101 is not exposed. For the protective insulating film 115 and the interlayer insulating film 108, materials or deposition conditions having different etch rates may be used. For example, by adding phosphorus (P) or boron (B) to silicon oxide that forms the protective insulating film 115, the etching rate of the protective insulating film 115 can be increased as compared with the interlayer insulating film 108; Etching selectivity can be given to the insulating film 108. In order to provide etching selectivity between the polysilicon film 114 and the silicon nitride constituting the second sidewall spacer 106 with silicon oxide, hydrofluoric acid is mainly used in wet etching. An etchant as a component may be used. In the case of dry etching, as an example, C ₅ F _{8 with} a flow rate of 15 ml / min (standard state), O _{2 with} a flow rate of 18 ml / min (standard state), and a flow rate of 950 ml / min (standard state). Reactive ion etching may be used in which Ar is supplied at a pressure of 6.7 Pa, the RF output (T / B) is 1800 W / 1500 W, and the substrate temperature is 0 ° C. As a result, a gap 105 a having a high aspect ratio is formed between each second sidewall spacer 106 and each polysilicon film 114. In the first embodiment, the protective insulating film 115 is deposited on the polysilicon film 114 in advance, and when the protective insulating film 115 is removed by etching, the upper portion of the first sidewall spacer 105 is exposed. However, the protective insulating film 115 and the first sidewall spacer 105 may be made of different materials, and the protective insulating film 115 and the first sidewall spacer 105 may be etched separately. . Further, without depositing the protective insulating film 115, the interlayer insulating film 108 is deposited directly on each polysilicon film 114, and the first side is exposed after the upper surface of each polysilicon film 114 is exposed by CMP or the like. The upper portion of the wall spacer 105 may be removed by etching.

  Next, as shown in FIG. 5A, for example, nickel (Ni) having a film thickness of 45 nm is formed on the interlayer insulating film 108 including the exposed sidewalls 105 and 106 and the polysilicon film 114 by sputtering. A metal film 109 made of is deposited. The deposition of the metal film 109 generally has a low step coverage (step coverage), that is, high directivity. Therefore, the deposition of the first sidewall spacer 105 between the second sidewall spacer 106 and the polysilicon film 114 is difficult. Regardless of the size of the polysilicon film 114, the metal film 109 is hardly deposited in the gaps 105a formed on the upper side. For this reason, each gap | interval part 105a remains. However, the metal film 109 may be deposited so as to straddle the upper side of the gap portion 105a. However, even in this case, there is no problem because the thickness of the metal film 109 is small.

  Next, as shown in FIG. 5B, the semiconductor substrate 101 is heat-treated in a nitrogen atmosphere at a temperature of 400 ° C., for example, by a rapid heat treatment (RTA) method. The entire polysilicon film 114 is silicided by causing a silicidation reaction with 109. Thereby, in the FET formation region T on the semiconductor substrate 101, the first gate electrode 14T1 and the second gate electrode 14T2 having a FUSI structure and having different gate lengths are formed, and in the resistance element formation region R, The first resistor 14R1 and the second resistor 14R2 having a FUSI structure and different widths are formed, and in the capacitor formation region C, a first upper portion having a FUSI structure and different widths is formed. An electrode 14C1 and a second upper electrode 14C2 are formed.

  As a feature of the first embodiment, in the silicidation process, a void formed by removing the upper portion of the first sidewall spacer 105 between the second sidewall spacer 106 and the polysilicon film 114. By 105a, the metal film 109 is isolated on each polysilicon film 114, or the film thickness of the metal film 109 becomes smaller than the other portions. Therefore, the metal for silicide is not excessively supplied to each polysilicon film 114 from the upper side of the second sidewall spacer 106 and the vicinity thereof. Therefore, the reactable volume ratio between each polysilicon film 114 and the metal film 109 does not depend on the gate length, that is, the planar dimension, of each gate electrode 14T1, 14T2, etc. That is, the reactable volume ratio between each polysilicon film 114 and the metal film 109 was deposited in the process shown in FIG. 5A and the polysilicon film 114 exposed in the process shown in FIG. It is determined by the film thickness of both the metal film 109 and is almost constant. In other words, the silicidation reaction for each polysilicon film 114 shifts from reaction rate control to supply rate control. As a result, a FUSI structure having a uniform composition can be realized for each of the gate electrodes 14T1 and 14T2, the resistors 14R1 and 14R2, and the upper electrodes 14C1 and 14C2 having different plane dimensions. . At this time, silicidation occurs between the polysilicon film 114 and the metal film 109 on the polysilicon film 114, so that the growth in the lateral direction (in-plane direction of the semiconductor substrate 101) hardly occurs. Therefore, the upper portions of the fully silicided gate electrodes 14T1, 14T2, and the like are separated from the second sidewall spacer 106, and the gap portion 105a is maintained. Note that the silicidation reaction does not occur in the metal film 109 deposited on the N-type source / drain region 107 and the lower electrode 117 because the interlayer insulating film 108 is interposed.

  Next, as shown in FIG. 6, the unreacted metal film 109 remaining above the interlayer insulating film 108 and the like is removed by etching, for example, with a mixed solution of sulfuric acid and hydrogen peroxide. Thereafter, an upper interlayer insulating film is deposited on the interlayer insulating film 108 including the gate electrodes 14T1, 14T2 and the like that have been changed to FUSI to form contact holes and wirings.

  As described above, according to the manufacturing method of the semiconductor device according to the first embodiment, the first sidewall spacer 105 and the second sidewall spacer 106 are sequentially formed on the side surface of the polysilicon film 114 to be silicided. After the formation, the upper portion of the first sidewall spacer 105 is removed, and a gap portion 105 a is provided between the second sidewall spacer 106 and the polysilicon film 114. Thereby, the metal film 109 can be isolated on each polysilicon film 114 when the metal film 109 is deposited on the polysilicon film 114. Even if the metal film 109 is not isolated, the film thickness of the upper portion of the gap portion 105a of the metal film 109 is thinner than the other portions. Thereby, it is possible to prevent an excessive supply of metal from the metal film 109 formed on the interlayer insulating film 108 and the second sidewall spacer 106 to each polysilicon film 114. As a result, the gate electrodes 14T1 and 14T2, the resistors 14R1 and 14R2, and the upper electrodes 14C1 and 14C2 can be uniformly formed with the same composition regardless of the dimensions.

  Further, conventionally, stress is applied to the semiconductor substrate through the side wall spacer due to the difference in expansion rate or contraction rate between the gate electrode and the side wall spacer. However, in the present embodiment, the stress on the semiconductor substrate 101 via the second sidewall spacer 106 by the gate electrodes 14T1 and 14T2 is caused by the gaps 105a formed on the side surfaces of the gate electrodes 14T1 and 14T2. Regardless of the planar dimensions of 14T1 and 14T2, it is greatly relaxed. Moreover, even if it contacts, stress is relieved by the space | gap part 105a. Therefore, variations in transistor characteristics due to stress due to FUSI can be prevented.

  Further, in the manufacturing method according to the first embodiment, the first N-type FET 11 and the second N-type FET 12, both of which have the same and uniform FUSI structure on one semiconductor substrate 101, The first resistor element 21 and the second resistor element 22, and the first capacitor element 31 and the second capacitor element 32 can be formed simultaneously.

  Although the N-type FETs 11 and 21 are formed in the FET formation region T, a P-type FET may be provided.

Further, although hafnium oxide (HfO ₂ ) is used for the gate insulating film 103 and the capacitor insulating film 113, HfSiO, HfSiON, SiO ₂ , SiON, or the like can be used instead. Although the gate insulating film 103 and the capacitor insulating film 113 are formed in the same step here, they may be formed in different steps.

  In the first embodiment, after the protective insulating film 115 is exposed from the planarized interlayer insulating film 108 in the step shown in FIG. 4A, the protective insulating film 115 and the first sidewall spacer 105 are exposed. However, the present invention is not limited to this, and the protective insulating film 115 and the first sidewall spacer 105 may be etched without providing the interlayer insulating film 108.

(Second Embodiment)
Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

  FIG. 7A to FIG. 7C show cross-sectional configurations of a semiconductor device according to the second embodiment of the present invention. In FIG. 7A to FIG. 7C, the same components as those shown in FIG. 7A to 7C are divided into three ways for convenience of drawing, and the semiconductor device according to this embodiment is formed on one semiconductor substrate 101.

  As shown in FIGS. 7A to 7C, the semiconductor device according to the second embodiment includes a plurality of regions separated by element isolation regions 102 selectively formed on an upper portion of a semiconductor substrate 101. As an element formation region, an N-type FET formation region T1, a P-type FET formation region T2, a first resistance element formation region R1, a second resistance element formation region R2, a first capacitor element formation region C1, and a second capacitor. It has an element formation region C2. Here, each of the resistance element formation regions R <b> 1 and R <b> 2 is provided on the element isolation region 102.

  As shown in FIG. 7A, in the N-type FET formation region T1, a first N-type FET 111 and a second N-type FET 121 having different gate lengths are formed, and in the P-type FET formation region T2, A first P-type FET 112 and a second P-type FET 122 having different gate lengths are formed.

  As shown in FIG. 7B, in the first resistor element formation region R1, the first resistor element 211 and the second resistor element 221 having different widths are formed, and the second resistor element formation region R2 is formed. The third resistor element 212 and the fourth resistor element 222 having different widths are formed.

  As shown in FIG. 7C, a first capacitor element 311 and a second capacitor element 321 having different widths are formed in the first capacitor element formation region C1, and the second capacitor element formation region C2 is formed. The third capacitor element 312 and the fourth capacitor element 322 having different widths are formed.

  The first N-type FET 111 and the second N-type FET 121 in the N-type FET forming region T1 are formed on the gate insulating film 103 formed on the semiconductor substrate 101 and the gate insulating film 103, respectively. The first gate electrode 14T1 made of FUSI-formed NiSi, the second gate electrode 14T2 having a larger gate length than the first gate electrode 14T1, and the gate electrodes 14T1 and 14T2 are sequentially formed on both side surfaces. A first sidewall spacer 105 and a second sidewall spacer 106; an N-type extension region 104N formed in a region of each side of the gate electrodes 14T1 and 14T2 in the semiconductor substrate 101; and a second in the semiconductor substrate 101. N type formed in the side region of each side wall spacer 106 It is constituted by a Sudorein region 107N.

The first P-type FET 112 and the second P-type FET 122 in the P-type FET formation region T2 are formed on the gate insulating film 103 formed on the semiconductor substrate 101 and the gate insulating film 103, respectively. A third gate electrode 14T3 made of FUSI-formed Ni ₃ Si, a fourth gate electrode 14T4 having a gate length larger than that of the third gate electrode 14T3, and both side surfaces of the gate electrodes 14T3 and 14T4 are sequentially formed. The first sidewall spacer 105 and the second sidewall spacer 106, the P-type extension region 104P formed in the region of each side of the gate electrodes 14T3 and 14T4 in the semiconductor substrate 101, and the semiconductor substrate 101 P formed in the lateral region of the second sidewall spacer 106, respectively. It is constituted by the source drain regions 107P.

  The first resistance element 211 and the second resistance element 221 in the first resistance element formation region R1 are wider than the first resistance body 14R1 and the first resistance body 14R1 each made of NiSi that has been made into FUSI. The second resistor 14R2 having a large thickness, and the first and second sidewall spacers 105 and 106 sequentially formed on both side surfaces of the resistors 14R1 and 14R2.

The third resistor element 212 and the fourth resistor element 222 in the second resistor element formation region R2 are respectively composed of the third resistor 14R3 and the third resistor 14R3 made of Ni ₃ Si made of FUSI. The first resistor 14R4 has a large width, and the first sidewall spacer 105 and the second sidewall spacer 106 are sequentially formed on both side surfaces of the resistors 14R3 and 14R4.

  The first capacitor element 311 and the second capacitor element 321 in the first capacitor element formation region C1 are MIS type capacitor elements, and the capacitor insulating film 113 formed on the semiconductor substrate 101 and the capacitor A first upper electrode 14C1 made of NiSi that has been made into FUSI, each formed on the insulating film 113, a second upper electrode 14C2 having a width wider than the first upper electrode 14C1, and each upper electrode 14C1, The first sidewall spacer 105 and the second sidewall spacer 106 sequentially formed on both side surfaces of 14C2, the lateral region of each of the upper electrodes 14C1 and 14C2 in the semiconductor substrate 101, and the lower side of the capacitive insulating film 113 And an N-type lower electrode 117N into which N-type impurity ions are implanted. The N-type lower electrode 117N is formed below the capacitive insulating film 113 in the semiconductor substrate 101. The N-type region 116N into which N-type impurity ions are implanted and the upper electrodes 14C1 and 14C2 side in the semiconductor substrate 101 are formed. Formed in each of the two regions, and formed in each of the N-type region 104NC into which the N-type impurity ions are implanted and the region on the side of the second sidewall spacer 106 in the semiconductor substrate 101, and the N-type impurity ions. And an N-type region 107NC into which is implanted.

The third capacitor element 312 and the fourth capacitor element 322 in the second capacitor element formation region C2 are MIS type capacitor elements, the capacitor insulating film 113 formed on the semiconductor substrate 101, and the capacitor A third upper electrode 14C3 made of Ni ₃ Si which is formed on the insulating film 113 and made of FUSI, a fourth upper electrode 14C4 having a width wider than the third upper electrode 14C3, and each upper electrode The first sidewall spacer 105 and the second sidewall spacer 106 sequentially formed on both side surfaces of 14C3 and 14C4, the lateral regions of the upper electrodes 14C3 and 14C4 in the semiconductor substrate 101, and the capacitance insulating film 113 The P-type lower electrode 117P is formed on the lower side and is implanted with P-type impurity ions. The P-type lower electrode 117P is formed below the capacitive insulating film 113 in the semiconductor substrate 101. The P-type region 116P into which P-type impurity ions are implanted, and the upper electrodes 14C3 and 14C4 side of the semiconductor substrate 101 P-type impurity ions are formed in a P-type region 104PC formed by implantation of P-type impurity ions and in regions adjacent to the second sidewall spacer 106 in the semiconductor substrate 101, respectively. And an N-type region 107PC formed by implantation.

  As described above, in the semiconductor device according to the second embodiment, the first and second gate electrodes 14T1 and 14T2 in the N-type FET formation region T1 and the P-type FET formation region T2, and the third and fourth The composition (Ni composition) of nickel silicide differs between the gate electrodes 14T3 and 14T4. Similarly, between each of the first and second resistors 14R1, 14R2 and each of the third and fourth resistors 14R3, 14R4, and each of the first and second upper electrodes 14C1, 14C2, The composition (Ni composition) of nickel silicide is made different between the third and fourth upper electrodes 14C3 and 14C4. Further, the first sidewall spacer 105 and the second sidewall spacer 106 stacked on both side surfaces of each of the gate electrodes 14T1 to 14T4, the resistors 14R1 to 14R4, and the upper electrodes 14C1 to 14C4 that are made FUSI. Of these, the upper ends of the first sidewall spacers 105 are the upper surfaces of the gate electrodes 14T1 to 14T4, the upper surfaces of the resistors 14R1 to 14R4, the upper surfaces of the upper electrodes 14C1 to 14C4, and the upper ends of the second sidewall spacers 106. Each lower.

  With this configuration, in the semiconductor device according to the second embodiment, the N-type FET formation region T1, the first resistor element formation region R1, and the first capacitor element formation region C1 have the size (planar dimension) of the FUSI structure. The P-type FET formation region T2, the second resistor element formation region R2, and the second capacitor element formation region C2 are the same regardless of the size (planar dimension) of the FUSI structure. The composition is as follows. For this reason, in the FET, it is possible to prevent variation in threshold voltage due to non-uniform composition due to the size of each gate electrode, so that improvement in performance and high integration of the semiconductor device can be realized. .

  In addition, each of the resistance elements 211 to 222 and the capacitance elements 311 to 222 can also prevent variations in resistance value and capacitance value.

  7A to 7C, each of the N-type FETs 111 and 121, the P-type FETs 112 and 122, and the capacitive elements 311, 321, 312, and 322 are divided by element isolation regions 102, respectively. Although an example of forming in the same region made of the substrate 101 has been shown, each element may be formed independently in a region partitioned by the element isolation region 102, and any two kinds of elements may be formed in the same region. They may be formed in combination. Further, although the example in which the resistance elements 211, 221, 212, and 222 are formed adjacent to each other on the element isolation region 102 is shown, they may be formed on the element isolation regions 102 that are separated from each other. In addition, the size of each element is set to two types of gate lengths in, for example, FETs, but may be three or more types.

Here, two types of materials, NiSi and Ni ₃ Si, are shown as materials for the gate electrodes 14T1 and 14T3 and the resistors 14R1 and 14R3, but three or more types may be used.

  Further, in each FET, regardless of the size (gate length) of the gate electrode, due to the difference in expansion coefficient between the silicide material and the second sidewall spacer 106 during the heat treatment applied after the FUSI process. Since stress on the semiconductor substrate 101 is greatly relieved by the gap 105a provided on the upper side of the first sidewall spacer 105, variations in FET characteristics due to differences in stress can be prevented.

  Also, in the second embodiment, FETs, resistance elements, and capacitive elements are shown as examples as elements, but the present invention can also be applied to other elements using a conductor having a FUSI structure, such as fuse elements.

  Hereinafter, a method of manufacturing the semiconductor device configured as described above will be described with reference to the drawings.

  FIG. 8A to FIG. 8C to FIG. 13A to FIG. 13C show cross-sectional structures in the order of steps of the semiconductor device manufacturing method according to the second embodiment of the present invention.

First, as shown in FIGS. 8A to 8C, as in the first embodiment, the element isolation region 102 is selectively formed on the upper part of the semiconductor substrate 101 made of silicon. Subsequently, an N-type impurity is selectively implanted into the first capacitor element formation region C1 of the semiconductor substrate 101 to form an N-type region 116N that becomes a part of the N-type lower electrode 117N. A P-type impurity is selectively implanted into the second capacitor element formation region C2 to form a P-type region 116P that becomes a part of the P-type lower electrode 117P. Subsequently, a gate insulating film 103 and a capacitor insulating film 113 made of, for example, HfO ₂ are deposited on the main surface of the semiconductor substrate 101 by CVD. At this time, an insulating film made of hafnium oxide may be formed on the element isolation region 102 in the resistance element formation region R. Subsequently, the gate insulating film 103 is interposed in the N-type FET formation region T1 and the P-type FET formation region T2 on the semiconductor substrate 101 by the CVD method, and the first capacitor element formation region C1 and the second capacitance element formation region C2 are formed. In the capacitor element formation region C2, a polysilicon film 114 having a thickness of 75 nm and a protective insulating film 115 made of silicon oxide having a thickness of 25 nm are sequentially deposited with a capacitor insulating film 113 interposed therebetween. Thereafter, the protective insulating film 115 and the polysilicon film 114 are patterned by a lithography method and an etching method, and the first and second gate lengths of the N-type and P-type FET formation regions T1 and T2 are different from each other. And third and fourth gate electrode patterns having different gate lengths are formed. In each of the first and second resistance element forming regions R1 and R2, the first and second resistor patterns having different widths and the third and fourth resistor patterns having different widths are formed. To do. In each of the first and second capacitor element formation regions C1 and C2, first and second upper electrode patterns having different widths and third and fourth upper electrode patterns having different widths are formed. To do. Subsequently, a first sidewall spacer 105 made of silicon oxide having a thickness of 5 nm is formed on both side surfaces of the patterned polysilicon film 114 and protective insulating film 115 by CVD. Subsequently, using the first sidewall spacer 105 and the protective insulating film 115 as a mask, an N-type extension region 104N is formed in the N-type FET formation region T1, and a part of the N-type lower electrode 117N is formed in the first capacitor element formation region C1. N-type regions 104NC are formed. Thereafter, a P-type extension region 104P is formed in the P-type FET formation region T2, and a P-type region 104PC that becomes a part of the P-type lower electrode 117P is formed in the second capacitor element formation region C2. The order of implantation of the N-type impurity ion implantation step and the P-type impurity ion implantation step is not limited. Subsequently, second sidewall spacers 106 made of silicon nitride are formed on both sides of each polysilicon film 114 and protective insulating film 115 with a first sidewall spacer 105 interposed therebetween. Thereafter, an N-type source / drain region 107N and an N-type region 107NC that becomes a part of the N-type lower electrode 117N are formed using the protective insulating film 115, the first sidewall spacer 105, and the second sidewall spacer 106 as a mask. Subsequently, a P-type source / drain region 107P and a P-type region 107PC to be a part of the P-type lower electrode 117P are formed. Thereafter, the exposed surfaces of the N-type source / drain region 107N, the P-type source / drain region 107P, the N-type region 107NC in the N-type lower electrode 117N, and the P-type region 107PC in the P-type lower electrode 117P are silicided with nickel (Ni) or the like. May be. Thereafter, an interlayer insulating film 108 made of silicon oxide is deposited on the semiconductor substrate 101 by the CVD method so as to cover the protective insulating films 115 and the side wall spacers 105, and the upper surface thereof is planarized by the CMP method to form each of them. The upper surface of the protective insulating film 115 is exposed.

  Next, as shown in FIGS. 9A to 9C, the protective insulating films 115 are removed by wet etching, for example, and the polysilicon film 114 positioned below the protective insulating films 115 is removed. Each is exposed. At this time, since the first sidewall 105 and the protective insulating film 115 are both made of silicon oxide, etching is performed so that the upper end of each first sidewall spacer 105 is lower than the upper surface of the polysilicon film 114 adjacent thereto. . In this etching, dry etching may be used instead of wet etching. As a result, a gap 105 a having a high aspect ratio is formed between each second sidewall spacer 106 and each polysilicon film 114. At this time, the distance from the upper surface of the polysilicon film 114 to the upper end of the first sidewall spacer 105 (the depth of the gap 105a) is equal to or greater than the width of the first sidewall spacer 105. It is preferable. In the second embodiment, the protective insulating film 115 is deposited on the polysilicon film 114 in advance, and the upper portion of the first sidewall spacer 105 is etched when the protective insulating film 115 is removed by etching. However, different materials may be used for the protective insulating film 115 and the first sidewall spacer 105, and the protective insulating film 115 and the first sidewall spacer 105 may be etched separately. Further, without depositing the protective insulating film 115, the interlayer insulating film 108 is deposited directly on each polysilicon film 114, and the first side is exposed after the upper surface of each polysilicon film 114 is exposed by CMP or the like. The upper portion of the wall spacer 105 may be removed by etching.

  Next, as shown in FIGS. 10A to 10C, the N-type FET formation region T1, the first resistor element formation region R1, and the first capacitor element formation region C1 are masked by lithography. A resist film 119 is formed, and the polysilicon film 114 in the P-type FET formation region T2, the second resistance element formation region R2, and the second capacitance element formation region C2 is formed using the formed resist film 119 as a mask. Dry etching using an etching gas mainly containing chlorine or hydrogen bromide is performed to obtain a polysilicon film 114a having a thickness of 40 nm. At this time, in the P-type FET formation region T2, the second resistance element formation region R2, and the second capacitance element formation region C2, the upper end of each first sidewall spacer 105 is lower than the upper surface of each polysilicon film 114a. It is necessary. Here, the distance from the upper surface of the polysilicon film 114a to the upper end of the first sidewall spacer 105 (depth of the gap 105a) is equal to or greater than the width of the first sidewall spacer 105. Preferably there is. Accordingly, in the step shown in FIG. 9, the upper end of the first sidewall spacer 105 in the P-type FET formation region T2 or the like may be lowered in advance. In the step shown in FIG. Etching for adjusting the height of the wall spacer 105 may be performed.

  Next, as shown in FIGS. 11A to 11C, for example, a film is formed on the interlayer insulating film 108 including the exposed sidewalls 105 and 106 and the polysilicon films 114 and 114a by sputtering. A metal film 109 made of nickel (Ni) having a thickness of 45 nm is deposited. As described above, since the deposition of the metal film 109 is generally low in step coverage, it is formed on the upper side of the first sidewall spacer 105 between the second sidewall spacer 106 and the polysilicon films 114 and 114a. Regardless of the size of the polysilicon films 114, 114a, the metal film 109 is hardly deposited in the gap 105a. For this reason, each gap | interval part 105a remains. However, the metal film 109 may be deposited so as to straddle the upper side of the gap portion 105a. However, even in this case, there is no problem because the thickness of the metal film 109 is small.

Next, as shown in FIGS. 12A to 12C, the semiconductor substrate 101 is subjected to a heat treatment in a nitrogen atmosphere at a temperature of 400 ° C. by, for example, a rapid heat treatment (RTA) method. By causing a silicidation reaction between the silicon films 114 and 114a and the metal film 109, the entire polysilicon films 114 and 114a are silicided. As a result, the N-type FET formation region T1, the first resistance element formation region R1, and the first capacitance element formation region C1 on the semiconductor substrate 101 have a FUSI structure in which the composition is NiSi. The first gate electrode 14T1 and the second gate electrode 14T2 having different gate lengths, the first resistor 14R1 and the second resistor 14R2 having different widths, and the first upper electrode 14C1 having different widths from each other The second upper electrode 14C2 is formed. On the other hand, each of the P-type FET formation region T2, the second resistance element formation region R2, and the second capacitance element formation region C2 has a FUSI structure in which the composition is Ni ₃ Si, and the gate lengths are different from each other. The third gate electrode 14T3 and the fourth gate electrode 14T4, the third resistor 14R3 and the fourth resistor 14R4 having different widths, the third upper electrode 14C3 and the fourth resistor having different widths from each other An upper electrode 14C4 is formed.

  As a feature of the second embodiment, it is formed by removing the upper portion of the first sidewall spacer 105 between the second sidewall spacer 106 and the polysilicon films 114 and 114a in the silicidation process. Due to the gap 105a, the metal film 109 is isolated on each of the polysilicon films 114 and 114a, or the film thickness of the metal film 109 is smaller than the other portions. Therefore, the metal for silicide is not excessively supplied to the polysilicon films 114 and 114a from the upper side of the second sidewall spacer 106 and the vicinity thereof. Therefore, the reactable volume ratio between the polysilicon films 114 and 114a and the metal film 109 does not depend on the gate lengths of the gate electrodes 14T1 and 14T2, etc., that is, the planar dimensions. That is, the reactable volume ratio between the polysilicon films 114 and 114a and the metal film 109 is deposited in the process shown in FIG. 11 and the polysilicon films 114 and 114a exposed in the process shown in FIGS. It is determined by the thickness of both the metal film 109 and the metal film 109, and is almost constant. As a result, the gate electrodes 14T1, 14T2 and 14T3, 14T4, the resistors 14R1, 14R2, 14R3, and 14R4, and the upper electrodes 14C1, 14C2, and 14C3, and 14C4, which have different plane dimensions, can be used. A FUSI structure having a uniform composition can be realized. At this time, silicidation occurs between the polysilicon films 114 and 114a and the metal film 109 thereon, so that the growth in the lateral direction (in-plane direction of the semiconductor substrate 101) hardly occurs. Therefore, the upper portions of the fully silicided gate electrodes 14T1 to 14T4 and the like are separated from the second sidewall spacer 106, and the gap portion 105a is maintained. The metal film 109 deposited on the N-type and P-type source / drain regions 107N and 107P and the N-type and P-type lower electrodes 117N and 117P has an interlayer insulating film 108 interposed therebetween, so that silicidation reaction is performed. Does not happen.

Furthermore, in the second embodiment, for example, the thickness of the polysilicon film 114a for forming the gate electrode in the P-type FET formation region T2 is changed to the gate electrode formation in the N-type FET formation region T1 in the step shown in FIG. The thickness is smaller than the thickness of the polysilicon film 114 for use. For this reason, the volume ratio of the metal film 109 to the polysilicon film 114a in the P-type FET formation region T2 is higher than that in the N-type FET formation region T1. The same applies to the resistor element formation regions R1 and R2 and the capacitor element formation regions C1 and C2. As a result, when nickel is used for the metal film 109, NiSi is formed in the FUSI structure in the N-type FET formation region T1, the first resistance element formation region R1, and the first capacitance element formation region C1, In the P-type FET forming region T2, the second resistor element forming region R2, and the second capacitor element forming region C2, Ni ₃ Si is formed in the FUSI structure, and FUSI structures having different compositions can be simultaneously formed. .

  Next, as shown in FIGS. 13A to 13C, the unreacted metal film 109 remaining above the interlayer insulating film 108 or the like is etched by, for example, a mixed solution of sulfuric acid and hydrogen peroxide solution. To remove. After that, an upper interlayer insulating film is deposited on the interlayer insulating film 108 including the FUSI gate electrodes 14T1 to 14T4 and the like to form contact holes and wirings.

  As described above, according to the method of manufacturing the semiconductor device according to the second embodiment, the first sidewall spacer 105 and the second sidewall are formed on the side surfaces of the polysilicon films 114 and 114a to be silicided. After sequentially forming the spacers 106, the upper portions of the first sidewall spacers 105 are removed, and gaps 105a are provided between the second sidewall spacers 106 and the polysilicon films 114 and 114a. Thereby, when the metal film 109 is deposited on the polysilicon films 114 and 114a, the metal film 109 can be isolated on the polysilicon films 114 and 114a. Even when the metal film 109 is not isolated, the film thickness of the upper part of the gap 105a in the metal film 109 is thinner than the other parts.

As a result, the composition of the first and second gate electrodes 14T1, 14T2, the first and second resistance elements 14R1, 14R2 and the first and second upper electrodes 14C1, 14C2 made FUSI by NiSi is changed. The composition can be the same regardless of the size (planar dimension). Similarly, the third and fourth gate electrodes 14T3 and 14T4, the third and fourth resistance elements 14R3 and 14R4, and the third and fourth upper electrodes 14C3 and 14C4 that are made FUSI by Ni ₃ Si. The composition can be the same composition regardless of its size (planar dimension). Furthermore, the N-type FETs 111 and 121, the P-type FETs 112 and 122, the resistance elements 211, 221, 212, and 222, and the capacitance elements 311, 321, 312, and 322 can be formed simultaneously.

In the second embodiment, for example, the mutual silicide composition of the first resistance element 211 and the third resistance element 212 is changed, but it may be adjusted to either NiSi or Ni ₃ Si. In the capacitive element, the silicide composition of the first capacitive element 311 and the third capacitive element 312 is changed, but the same composition may be used.

  Also in the second embodiment, after the protective insulating film 115 is exposed from the planarized interlayer insulating film 108 in the step shown in FIG. 8, the protective insulating film 115 and the first sidewall spacer 105 are exposed. Although the etching is performed, the present invention is not limited to this, and the protective insulating film 115 and the first sidewall spacer 105 may be etched without providing the interlayer insulating film 108.

(Third embodiment)
Hereinafter, a third embodiment of the present invention will be described with reference to the drawings.

  FIG. 14A to FIG. 14C show cross-sectional configurations of the semiconductor device according to the third embodiment of the present invention. In FIG. 14A to FIG. 14C, the same components as those shown in FIG. 7A to FIG. 14A to 14C are divided into three ways for convenience of drawing, and the semiconductor device according to this embodiment is formed on one semiconductor substrate 101.

  The difference of the third embodiment from the second embodiment is that the third gate electrode 15T3 and the fourth gate electrode 15T4 formed in the P-type FET formation region T2 and the second resistance element formation region R2 The third resistor 15R3 and the fourth resistor 15R4 formed in the second capacitor element 15R3, and the third upper electrode 15C3 and the fourth upper electrode 15C4 formed in the second capacitor element formation region C2 are respectively platinum silicide ( PtSi) is FUSI.

  Furthermore, in the second embodiment, the height of each patterned polysilicon film 114 formed in the P-type FET forming region T2, the second resistor element forming region R2, and the second capacitor element forming region C2 is reduced. Although the etching is performed, in the third embodiment, it remains the same as the N-type FET formation region T1 and the like.

  14A to 14C, the N-type FETs 111 and 121, the P-type FETs 112 and 122, the resistance elements 211, 221, 212, and 222 and the capacitive elements 311, 321, 312, and 322 Is formed on one semiconductor substrate 101, but each element may be formed alone, or any two kinds of elements among FET, resistor element and capacitor element may be combined. .

  In addition, the size of each element is set to two types of gate lengths in, for example, FETs, but may be three or more types.

  In the third embodiment, FETs, resistor elements, and capacitor elements are shown as examples of elements, but the present invention can also be applied to other elements using a conductor having a FUSI structure, such as fuse elements.

  Hereinafter, a method of manufacturing the semiconductor device configured as described above will be described with reference to the drawings.

  FIG. 15A to FIG. 15C to FIG. 22A to FIG. 22C show cross-sectional structures in the order of steps of the method of manufacturing a semiconductor device according to the third embodiment of the present invention.

  First, FIG. 15A to FIG. 15C show interlayer insulation formed on the semiconductor substrate 101 in the same manner as FIG. 9A to FIG. 9C in the manufacturing method according to the second embodiment. The film 108 and each first sidewall spacer 105 are removed by etching, and the height of the upper end of each first sidewall spacer 105 is set to the upper end of each second sidewall spacer 106 and each polysilicon film 114. The state is shown as being lower than the upper surface.

  Next, as shown in FIGS. 16A to 16C, for example, a film thickness is formed on the interlayer insulating film 108 including the exposed sidewalls 105 and 106 and the polysilicon film 114 by sputtering. A first metal film 109 made of 45 nm nickel (Ni) is deposited. As described above, the deposition of the first metal film 109 is generally formed on the upper side of the first sidewall spacer 105 between the second sidewall spacer 106 and the polysilicon film 114 because the step coverage is low. Regardless of the size of the polysilicon film 114, the first metal film 109 is hardly deposited in the gap 105a. For this reason, each gap | interval part 105a remains. However, the first metal film 109 may be deposited so as to straddle the upper side of the gap portion 105a. However, even in this case, there is no problem because the thickness of the first metal film 109 is small.

  Next, as shown in FIGS. 17A to 17C, the N-type FET formation region T1, the first resistor element formation region R1, and the first capacitor element formation region C1 are masked by lithography. The first resist film 129 is formed, and the first resist film 129 is used as a mask to cover the P-type FET formation region T2, the second resistance element formation region R2, and the second capacitor element formation region C2. The metal film 109 is removed using, for example, a mixed solution of sulfuric acid and hydrogen peroxide solution.

  Next, as shown in FIGS. 18A to 18C, after removing the first resist film 129, the temperature of the semiconductor substrate 101 is set to 400 ° C. by, for example, rapid thermal processing (RTA). Is performed between the polysilicon film 114 and the first metal film 109 in the N-type FET formation region T1, the first resistance element formation region R1, and the first capacitance element formation region C1. By causing a silicidation reaction, the entire polysilicon film 114 is silicided. As a result, the N-type FET formation region T1, the first resistance element formation region R1, and the first capacitance element formation region C1 have a FUSI structure in which the composition is NiSi, and the gate lengths are different from each other. One gate electrode 14T1 and second gate electrode 14T2, first resistor 14R1 and second resistor 14R2 having different widths, and first upper electrode 14C1 and second upper portion having different widths from each other Electrode 14C2 is formed.

  As a feature of the third embodiment, it is formed by removing the upper portion of the first sidewall spacer 105 between the second sidewall spacer 106 and the polysilicon film 114 in the first silicidation step. Due to the gap 105a, the first metal film 109 is isolated on each polysilicon film 114, or the thickness of the first metal film 109 is smaller than that of the other portions. Therefore, the metal for silicidation is not excessively supplied to each polysilicon film 114 from the upper side of the second sidewall spacer 106 and the vicinity thereof. Accordingly, the reactable volume ratio between each polysilicon film 114 and the first metal film 109 is the same as that of the polysilicon film 114 exposed in the step shown in FIG. 15 and the first deposited in the step shown in FIG. It is determined by the film thickness of both the metal film 109 and is almost constant. As a result, a FUSI structure having a uniform composition can be realized for each of the gate electrodes 14T1 and 14T2, the resistors 14R1 and 14R2, and the upper electrodes 14C1 and 14C2 having different plane dimensions. . At this time, silicidation occurs between the polysilicon film 114 and the first metal film 109 thereon, so that almost no lateral growth occurs. Therefore, the upper portions of the fully silicided gate electrodes 14T1, 14T2, and the like are separated from the second sidewall spacer 106, and the gap portion 105a is maintained. Note that the silicidation reaction does not occur in the first metal film 109 deposited above the N-type source / drain region 107N and the N-type region 107NC because the interlayer insulating film 108 is interposed therebetween.

  Next, as shown in FIGS. 19A to 19C, the unreacted first metal film 109 is removed by, for example, a mixed solution of sulfuric acid and hydrogen peroxide, and then exposed by sputtering. On the interlayer insulating film 108 including the sidewalls 105 and 106, the gate electrodes 14T1 and 14T2, the resistors 14R1 and 14R2, the upper electrodes 14C1 and 14C2, and the polysilicon films 114, for example, a film thickness of 45 nm A second metal film 110 made of platinum (Pt) is deposited. Even in the deposition of the second metal film 110, since the step coverage is low, the gap 105a formed on the upper side of the first sidewall spacer 105 between the second sidewall spacer 106 and the polysilicon film 114 is formed. Regardless of the size of the polysilicon film 114, the second metal film 110 is hardly deposited. For this reason, each gap | interval part 105a remains. However, the second metal film 110 may be deposited so as to straddle the upper side of the gap portion 105a. However, even in this case, there is no problem because the thickness of the second metal film 110 is small.

  Next, as shown in FIGS. 20A to 20C, the P-type FET formation region T2, the second resistor element formation region R2, and the second capacitor element formation region C2 are masked by lithography. A second resist film 139 is formed, and the second resist film 139 thus formed is used as a mask to cover the N-type FET formation region T1, the first resistance element formation region R1, and the first capacitor element formation region C1. The metal film 110 is removed using, for example, a mixed solution of sulfuric acid and hydrogen peroxide solution.

  Next, as shown in FIGS. 21A to 21C, after the second resist film 139 is removed, the temperature of the semiconductor substrate 101 is set to 400 ° C. by, for example, rapid thermal processing (RTA). Is performed between the polysilicon film 114 and the second metal film 110 in the P-type FET formation region T2, the second resistor element formation region R2, and the second capacitor element formation region C2. By causing a silicidation reaction, the entire polysilicon film 114 is silicided. As a result, the P-type FET formation region T2, the second resistance element formation region R2, and the second capacitance element formation region C2 have the FUSI structure in which the composition is PtSi, and the gate lengths are different from each other. Third gate electrode 15T3 and fourth gate electrode 15T4, third resistor 15R3 and fourth resistor 15R4 having different widths, and third upper electrode 15C3 and fourth upper portion having mutually different widths Electrode 15C4 is formed.

  As a feature of the third embodiment, it is formed by removing the upper portion of the first sidewall spacer 105 between the second sidewall spacer 106 and the polysilicon film 114 in the second silicidation step. Due to the gap 105a, the second metal film 110 is isolated on each polysilicon film 114, or the thickness of the second metal film 110 is smaller than that of the other portions. Therefore, the metal for silicidation is not excessively supplied to each polysilicon film 114 from the upper side of the second sidewall spacer 106 and the vicinity thereof. Therefore, the reactive volume ratio between each polysilicon film 114 and the second metal film 110 is the same as the polysilicon film 114 exposed in the step shown in FIG. 18 and the second deposited in the step shown in FIG. It is determined by the film thickness of both of the metal film 110 and becomes almost constant. As a result, a FUSI structure having a uniform composition can be realized for each of the gate electrodes 15T3 and 15T4, the resistors 15R3 and 15R4, and the upper electrodes 15C3 and 15C4 having different plane dimensions. . At this time, silicidation occurs between the polysilicon film 114 and the second metal film 110 on the polysilicon film 114, so that the lateral growth hardly occurs. Therefore, the upper portions of the fully silicided gate electrodes 15T3, 15T4 and the like are separated from the second sidewall spacer 106, and the gap portion 105a is maintained. Note that the silicidation reaction does not occur in the second metal film 110 deposited above the P-type source / drain region 107P and the P-type lower electrode 117P because the interlayer insulating film 108 is interposed therebetween.

  Next, as shown in FIGS. 22A to 22C, the unreacted second metal film 110 is removed by etching using, for example, a mixed solution of sulfuric acid and hydrogen peroxide solution. Thereafter, an upper interlayer insulating film is deposited on the interlayer insulating film 108 including the gate electrodes 14T1, 14T2, 15T3, 15T4 and the like that have been changed to FUSI to form contact holes and wirings.

  As described above, according to the manufacturing method of the semiconductor device according to the third embodiment, the first sidewall spacer 105 and the second sidewall spacer 106 are formed on each side surface of the polysilicon film 114 to be silicided. Are sequentially formed, and the upper portion of the first sidewall spacer 105 is removed to provide a gap 105 a between the second sidewall spacer 106 and the polysilicon film 114. As a result, when the first metal film 109 or the second metal film 110 is deposited on the polysilicon film 114, the metal films 109 and 110 can be isolated on each polysilicon film 114. Even if the metal films 109 and 110 are not isolated, the thickness of the upper part of the gap 105a in the metal films 109 and 110 is thinner than the other parts.

  As a result, the composition of the first and second gate electrodes 14T1, 14T2, the first and second resistance elements 14R1, 14R2 and the first and second upper electrodes 14C1, 14C2 made FUSI by NiSi is changed. The composition can be the same regardless of the size (planar dimension). Similarly, the compositions of the third and fourth gate electrodes 15T3 and 15T4, the third and fourth resistance elements 15R3 and 15R4, and the third and fourth upper electrodes 15C3 and 15C4 that are made FUSI by PtSi are set. The composition can be the same regardless of the size (planar dimension). As a result, in the FET, it is possible to prevent variation in threshold voltage due to non-uniform composition due to the size of each gate electrode 14T1, 14T2, 15T3, and 15T4, thereby improving the performance and high integration of the semiconductor device. Can be realized.

  Furthermore, the N-type FETs 111 and 121, the P-type FETs 112 and 122, the resistance elements 211, 221, 212, and 222, and the capacitance elements 311, 321, 312, and 322 can be formed simultaneously.

  In each FET, regardless of the size of the gate electrode, the semiconductor substrate 101 is caused by a difference in expansion coefficient between the silicide material and the second sidewall spacer 106 applied during heat treatment after the FUSI process. Is significantly relieved by the gap 105a provided on the upper side of the first sidewall spacer 105, so that variations in FET characteristics due to the difference in stress can be prevented.

  In the third embodiment, for example, the mutual silicide composition of the first resistance element 211 and the third resistance element 212 is changed, but may be adjusted to either NiSi or PtSi. In the capacitive element, the silicide composition of the first capacitive element 311 and the third capacitive element 312 is changed, but the same composition may be used.

As a modification of the manufacturing method according to the third embodiment, after the first metal film 109 shown in FIG. 16 is deposited, the P-type FET formation region T2, the second resistance element formation region R2, and the second By selectively laminating the first metal film 109 selectively only in the capacitor element formation region C2, the third gate electrodes 15T3, 15T4, etc. in the P-type FET formation region T2 are made metal rich, for example, as Ni ₃ Si Also good.

  INDUSTRIAL APPLICABILITY The semiconductor device and the manufacturing method thereof according to the present invention have an effect that a uniform FUSI structure can be obtained, and are particularly useful for a semiconductor device including a field effect transistor having a FUSI gate electrode and a manufacturing method thereof. .

1 is a schematic cross-sectional view showing a semiconductor device according to a first embodiment of the present invention. (A) And (b) shows typically the gate electrode in the semiconductor device which concerns on the 1st Embodiment of this invention, (a) is a top view, (b) is the IIb-IIb line | wire of (a) FIG. (A) And (b) is sectional drawing of the order of a process which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. (A) And (b) is sectional drawing of the order of a process which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. (A) And (b) is sectional drawing of the order of a process which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. FIG. 6 is a cross-sectional view in order of the steps showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention. (A)-(c) is typical sectional drawing which shows the semiconductor device which concerns on the 2nd Embodiment of this invention. (A)-(c) is sectional drawing of the order of a process which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. (A)-(c) is sectional drawing of the order of a process which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. (A)-(c) is sectional drawing of the order of a process which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. (A)-(c) is sectional drawing of the order of a process which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. (A)-(c) is sectional drawing of the order of a process which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. (A)-(c) is sectional drawing of the order of a process which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. (A)-(c) is typical sectional drawing which shows the semiconductor device which concerns on the 3rd Embodiment of this invention. (A)-(c) is sectional drawing of the order of a process which shows the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention. (A)-(c) is sectional drawing of the order of a process which shows the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention. (A)-(c) is sectional drawing of the order of a process which shows the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention. (A)-(c) is sectional drawing of the order of a process which shows the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention. (A)-(c) is sectional drawing of the order of a process which shows the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention. (A)-(c) is sectional drawing of the order of a process which shows the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention. (A)-(c) is sectional drawing of the order of a process which shows the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention. (A)-(c) is sectional drawing of the order of a process which shows the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention. (A)-(d) is sectional drawing of the order of a process which shows the manufacturing method of FET with the conventional FUSI electrode structure. (A) And (b) is sectional drawing which shows the subject of the manufacturing method of FET with the conventional FUSI electrode structure.

Explanation of symbols

T FET formation region R Resistance element formation region C Capacitance element formation region T1 N-type FET formation region T2 P-type FET formation region R1 First resistor element formation region R2 Second resistor element formation region C1 First capacitor element formation region C2 Second capacitor element formation region 11 First N-type FET
12 Second N-type FET
21 1st resistive element 22 2nd resistive element 31 1st capacitive element 32 2nd capacitive element 14T1 1st gate electrode 14T2 2nd gate electrode 14T3 3rd gate electrode 14T4 4th gate electrode 14R1 4th 1 resistor 14R2 second resistor 14R3 third resistor 14R4 third resistor 14C1 first upper electrode 14C2 second upper electrode 14C3 third upper electrode 14C4 fourth upper electrode 15T3 third Gate electrode 15T4 Fourth gate electrode 15R3 Third resistor 15R4 Third resistor 15C3 Third upper electrode 15C4 Fourth upper electrode 101 Semiconductor substrate 102 Element isolation region 103 Gate insulating film 104 N-type extension region 104C N Type region 104N N type extension region 104P P type extension region 104NC N type region 104PC P-type region 105 First sidewall spacer 106 Second sidewall spacer 107 N-type source / drain region 107C N-type region 107NC N-type region 107PC P-type region 107N N-type source / drain region 107P P-type source / drain region 108 Interlayer Insulating film 109 (first) metal film 110 second metal film 113 capacitive insulating film 114 polysilicon film 114a polysilicon film 115 protective insulating film 116 N-type region 117 lower electrode 117N N-type lower electrode 117P P-type lower electrode 119 Resist film 129 First resist film 139 Second resist film 111 First N-type FET
121 Second N-type FET
112 First P-type FET
122 Second P-type FET
211 1st resistive element 221 2nd resistive element 212 3rd resistive element 222 4th resistive element 311 1st capacitive element 321 2nd capacitive element 312 3rd capacitive element 322 4th capacitive element

Claims (18)

A semiconductor device comprising a first MIS transistor having a first gate electrode fully silicided with a metal,
The first MIS transistor is
A first gate insulating film formed on the semiconductor region;
The first gate electrode formed on the first gate insulating film;
A first sidewall spacer formed on a side surface of the first gate electrode;
A second sidewall spacer formed on the side surface of the first gate electrode with the first sidewall spacer interposed therebetween,
The first sidewall spacer and the second sidewall spacer have different etching characteristics.
The semiconductor device according to claim 1, wherein an upper end of the first sidewall spacer is formed lower than an upper surface of the first gate electrode and an upper end of the second sidewall spacer. The semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein an upper end of the second sidewall spacer is higher than an upper surface of the first gate electrode. The semiconductor device according to claim 1 or 2,
A second MIS transistor having a second gate electrode that is fully silicided with the metal and has a gate length larger than that of the first gate electrode;
The second MIS type transistor is:
A second gate insulating film formed on the semiconductor region;
The second gate electrode formed on the second gate insulating film;
The first sidewall spacer formed on the side surface of the second gate electrode;
The second sidewall spacer formed on the side surface of the second gate electrode with the first sidewall spacer interposed therebetween,
The upper end of the first sidewall spacer is formed lower than the upper surface of the second gate electrode and the upper end of the second sidewall spacer,
The semiconductor device according to claim 1, wherein a conductivity type of the first MIS transistor is the same as a conductivity type of the second MIS transistor. The semiconductor device according to claim 3.
The upper surface of the first gate electrode and the upper surface of the second gate electrode have the same height from the upper surface of the semiconductor region. The semiconductor device according to claim 3 or 4,
The semiconductor device, wherein the first gate electrode and the second gate electrode have the same composition. The semiconductor device according to any one of claims 1 to 5,
A third MIS transistor having a third gate electrode fully silicided with the metal;
The third MIS type transistor is:
A third gate insulating film formed on the semiconductor region;
The third gate electrode formed on the third gate insulating film;
The first sidewall spacer formed on the side surface of the third gate electrode;
And the second sidewall spacer formed on the side surface of the third gate electrode with the first sidewall spacer interposed therebetween,
The upper end of the first sidewall spacer is formed lower than the upper surface of the third gate electrode and the upper end of the second sidewall spacer,
A semiconductor device characterized in that a conductivity type of the first MIS transistor is different from a conductivity type of the third MIS transistor. The semiconductor device according to claim 6.
The semiconductor device, wherein the first gate electrode and the third gate electrode have different compositions. The semiconductor device according to any one of claims 1 to 7,
A resistance element having a resistor fully silicided with the metal;
The resistance element is
The resistor formed on an element isolation region provided on the semiconductor region;
The first sidewall spacer formed on the side surface of the resistor;
The second sidewall spacer formed on the side surface of the resistor with the first sidewall spacer interposed therebetween,
The semiconductor device according to claim 1, wherein an upper end of the first sidewall spacer is formed lower than an upper surface of the second resistor and an upper end of the second sidewall spacer. The semiconductor device according to claim 8,
The semiconductor device according to claim 1, wherein the first gate electrode and the resistor have the same composition. The semiconductor device according to any one of claims 1 to 9,
A capacitor element having an upper electrode fully silicided with the metal;
The capacitive element is
A capacitive insulating film formed on the semiconductor region;
The upper electrode formed on the capacitive insulating film;
The first sidewall spacer formed on the side surface of the upper electrode;
The second sidewall spacer formed on the side surface of the upper electrode with the first sidewall spacer interposed therebetween,
The semiconductor device according to claim 1, wherein an upper end of the first sidewall spacer is formed lower than an upper surface of the upper electrode and an upper end of the second sidewall spacer. The semiconductor device according to claim 10.
The semiconductor device, wherein the first gate electrode and the upper electrode have the same composition. A method of manufacturing a semiconductor device including a first MIS transistor having a first gate electrode on a first gate insulating film,
Forming the first gate insulating film on the semiconductor region (a);
A step (b) of forming a first gate silicon film on the first gate insulating film;
Forming a first sidewall spacer on a side surface of the first gate silicon film;
Forming a second sidewall spacer on the side surface of the first gate silicon film by interposing the first sidewall spacer;
After the step (d), the first sidewall spacer is etched so that the height of the upper end of the first sidewall spacer is the upper surface of the first gate silicon film and the second gate spacer. A step (e) lower than the upper end of the sidewall spacer;
A step (f) of forming a metal film on the first gate silicon film after the step (e);
A step (g) of forming the first gate electrode by fully siliciding the first gate silicon film with the metal film. In the manufacturing method of the semiconductor device according to claim 12,
The step (b) includes a step of forming a protective insulating film on the first gate silicon film,
The step (c) includes a step of forming the first sidewall spacer on the side surfaces of the first gate silicon film and the protective insulating film,
The step (d) includes forming a second sidewall spacer with the first sidewall spacer interposed on the side surfaces of the first gate silicon film and the protective insulating film,
The step (e) includes a step of etching the protective insulating film to expose an upper surface of the first gate silicon film. In the manufacturing method of the semiconductor device according to claim 12 or 13,
The semiconductor device further includes a second MIS transistor having a second gate electrode having a gate length larger than that of the first gate electrode on the second gate insulating film,
The step (a) includes a step of forming the second gate insulating film on the semiconductor region,
The step (b) includes a step of forming a second gate silicon film on the second gate insulating film,
The step (c) includes the step of forming the first sidewall spacer on the side surface of the second gate silicon film,
The step (d) includes a step of forming the second sidewall spacer on the side surface of the second gate silicon film with the first sidewall spacer interposed therebetween,
In the step (e), the first sidewall spacer is etched so that the height of the upper end of the first sidewall spacer is set to the upper surface of the second gate silicon film and the second gate spacer. Including a step of lowering the upper end of the sidewall spacer,
The step (f) includes a step of forming the metal film on the second gate silicon film,
The method (g) includes a step of forming the second gate electrode by fully siliciding the second gate silicon film with the metal film. In the manufacturing method of the semiconductor device according to any one of claims 12 to 14,
The semiconductor device further includes a third MIS transistor having a third gate electrode having a composition different from that of the first gate electrode on a third gate insulating film,
The step (a) includes a step of forming the third gate insulating film on the semiconductor region,
The step (b) includes a step of forming a third gate silicon film on the third gate insulating film,
The step (c) includes a step of forming the first sidewall spacer on the side surface of the third gate silicon film,
The step (d) includes a step of forming the second sidewall spacer on the side surface of the third gate silicon film with the first sidewall spacer interposed therebetween,
In the step (e), the first sidewall spacer is etched so that the height of the upper end of the first sidewall spacer is set to the upper surface of the third gate silicon film and the second gate spacer. Including a step of lowering the upper end of the sidewall spacer,
The step (f) includes a step of forming the metal film on the third gate silicon film,
The step (g) includes a step of forming the third gate electrode by fully siliciding the third gate silicon film with the metal film,
After the step (b) and before the step (f), the third gate silicon film is etched so that the height of the upper surface of the third gate silicon film is the first height. A method of manufacturing a semiconductor device, further comprising a step (h) of lowering the upper surface of the gate silicon film. In the manufacturing method of the semiconductor device according to any one of claims 12 to 14,
The semiconductor device further includes a third MIS transistor having a third gate electrode having a composition different from the composition of the first gate electrode on a third gate insulating film,
The step (a) includes a step of forming the third gate insulating film on the semiconductor region,
The step (b) includes a step of forming a third gate silicon film on the third gate insulating film,
The step (c) includes a step of forming the first sidewall spacer on the side surface of the third gate silicon film,
The step (d) includes a step of forming the second sidewall spacer on the side surface of the third gate silicon film with the first sidewall spacer interposed therebetween,
In the step (e), the first sidewall spacer is etched so that the height of the upper end of the first sidewall spacer is set to the upper surface of the third gate silicon film and the second gate spacer. Including a step of lowering the upper end of the sidewall spacer,
After the step (e), a step (i) of forming another metal film on the third gate silicon film, and the third gate silicon film is fully silicided with the other metal film. And a step (j) of forming the third gate electrode. In the manufacturing method of the semiconductor device according to any one of claims 12 to 16,
The semiconductor device further includes a resistance element having a resistor,
Before the step (a), further comprising a step (k) of forming an element isolation region above the semiconductor region;
The step (b) includes a step of forming a resistance silicon film on the element isolation region,
The step (c) includes a step of forming the first sidewall spacer on a side surface of the resistance silicon film,
The step (d) includes a step of forming the second sidewall spacer by interposing the first sidewall spacer on a side surface of the resistance silicon film,
In the step (e), the first sidewall spacer is etched, and the height of the upper end of the first sidewall spacer is set to the upper surface of the resistance silicon film and the second sidewall spacer. Including lowering the upper end of the
The step (f) includes a step of forming the metal film on the resistance silicon film,
The step (g) includes a step of forming the resistor by fully siliciding the resistance silicon film with the metal film. In the manufacturing method of the semiconductor device of any one of Claims 12-17,
The semiconductor device further includes a capacitive element having an upper electrode,
The step (a) includes a step of forming the capacitive insulating film on the semiconductor region,
The step (b) includes a step of forming a capacitive silicon film on the capacitive insulating film,
The step (c) includes a step of forming the first sidewall spacer on a side surface of the capacitor silicon film,
The step (d) includes a step of forming the second sidewall spacer by interposing the first sidewall spacer on a side surface of the capacitor silicon film,
In the step (e), the first sidewall spacer is etched, and the height of the upper end of the first sidewall spacer is set to the upper surface of the capacitive silicon film and the second sidewall spacer. Including lowering the upper end of the
The step (f) includes a step of forming the metal film on the capacitor silicon film,
The step (g) includes a step of forming the upper electrode by fully siliciding the capacitor silicon film with the metal film.

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