JP2007140623A - Memory failure detection device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory failure detection device for preventing a memory from being decided to be defective even when partial memory blocks break down in detecting the failure of a memory equipped with a plurality of memory blocks, and for acquiring information for specifying the defective memory block even during its use. <P>SOLUTION: The number of defective memory blocks 2 is counted by a counter 4 based on the detection result of a block failure detection part 3, and when the number exceeds a preliminarily set comparison value, it is decided that the memory block is defective by a memory failure determination part 5. Also, this memory failure detection device is provided with a block failure information acquisition part 6 for acquiring information for specifying the defective memory block from the outside based on the detection result of the block failure detection part 3. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a memory failure detection device, and more particularly to a memory failure detection device configured by a plurality of memory blocks.

  The memory of a device that stores a large amount of setting information is usually composed of a plurality of memory blocks. For example, in a transmission apparatus that needs to store a lot of information such as apparatus settings and transmission path settings, the information is stored in a main backup memory. The main backup memory is generally composed of a plurality of memory chips, and each memory chip is composed of a plurality of memory blocks. That is, the main backup memory is composed of a plurality of memory blocks, and the setting information and the like are stored in each memory block. In detecting a failure of a memory such as a main backup memory, a method of detecting a failure in units of memory blocks is used.

  Specifically, before writing data to the memory block, failure detection confirmation data such as a checksum or CRC is added to the data. Then, this data is written and stored in the memory block, and after further reading, the failed memory block is detected depending on whether or not the failure detection confirmation data before and after storage is different.

  The conventional memory failure detection device performs the above-described failure detection periodically or at the timing of writing or reading with respect to a plurality of memory blocks constituting the memory, and when even one failure is detected, The entire memory is configured to be determined as a failure. And when it determines with a failure, it has the structure which notifies a failure to the apparatus main body using memory.

  A failure detection method using a checksum is disclosed in Patent Document 1.

JP 2001-0777816 A

  In a memory failure detection apparatus using a conventional failure detection method, even if the minimum necessary number of memory blocks functioning as a memory can be used, it is determined that a failure of the entire memory occurs even if one memory block failure occurs. Therefore, there is a problem that the apparatus using this memory has to be stopped. In addition, there is a problem in that information for identifying a failed memory block cannot be acquired even though a failure is detected in units of memory blocks.

  The present invention has been made to solve the above-mentioned problem. When there are few failed memory blocks, it is not necessary to interrupt the use of the memory, and the memory that can acquire information for identifying the failed memory block is obtained. An object is to provide a failure detection apparatus.

  The memory failure detection device according to claim 1 is a memory failure detection device including a plurality of memory blocks, the block failure detection unit detecting the memory failure in units of the memory blocks, and the block failure detection unit. A counter that counts the number of the memory blocks that have failed based on the detection result in the memory, a memory failure determination unit that determines a failure when the number counted by the counter exceeds a preset comparison value, and the block A block failure information acquisition unit that enables acquisition of information specifying the memory block that has failed based on the detection result of the failure detection unit from the outside.

  According to the memory failure detection device according to claim 1, even if a part of a memory including a plurality of memory blocks fails, it is determined that a failure occurs until the number of failed memory blocks exceeds a preset value. Therefore, the memory can be used continuously. In addition, even when the memory is in use, information for identifying the defective memory block can be acquired from the outside, so that it is possible to perform planned repair and replacement of the memory, which improves work quality. it can.

<Embodiment 1>
The memory failure detection apparatus according to the present embodiment will be described with reference to the block diagram of FIG. In the present embodiment, main components of the present invention are extracted.

  A memory 1 that stores a large amount of information includes a plurality of memory blocks 2. The memory failure detection apparatus according to the present invention includes a block failure detection unit 3, a counter 4, a memory failure determination unit 5, and a block failure information acquisition unit 6, and is connected to the memory 1.

  The block failure detection unit 3 detects a failure in the memory 1 in units of memory blocks using a failure detection method such as checksum or CRC. Further, since the above-described failure detection is performed on all the memory blocks 2 in the memory 1 periodically or at the timing of writing / reading, the memory 1 is used without being affected by the failure detection. Can continue.

  The counter 4 receives the detection result of the memory block 2 that has failed in the memory 1 from the block failure detection unit 3, and counts the number of memory blocks 2 that have failed based on the result.

  The number counted by the counter 4 is compared with a comparison value by the memory failure determination unit 5, and when the comparison value is exceeded, the entire memory 1 is determined as a failure. The comparison value is a value preset in the memory failure detection device.

  A block failure information acquisition unit 6 is connected to the block failure detection unit 3. Based on the detection result of the block failure detection unit 3, the block failure information acquisition unit 6 acquires, from the outside, information for specifying a failure of the memory 1 in units of memory blocks, for example, by means such as storage and lighting display described later. This is the part that makes it possible.

  The operation of the memory failure detection apparatus of the present embodiment configured as described above will be described.

  When a failure occurs in the memory 1, the block failure detection unit 3 detects the failure in the memory 1 in units of memory blocks. This detection is performed so as not to affect the use of the memory 1.

  The counter 4 counts the number of failed memory blocks 2 in the memory 1 based on the result of the block failure detection unit 3. Then, the memory failure determination unit 5 compares this number with a preset comparison value, and if the comparison value is exceeded, it is determined that there is a failure. That is, when the number of failed memory blocks 2 in the entire memory 1 exceeds the comparison value, the memory failure detection device according to the present embodiment determines that the memory 1 is failed.

  In parallel with the above operation, the block failure information acquisition unit 6 identifies a failure of the memory 1 in units of memory blocks by means of storage, lighting display, etc., which will be described later, based on the detection result of the block failure detection unit 3 Information can be obtained from outside.

  With the above operation, according to the memory failure detection device according to the present embodiment, even if a part of the memory 1 fails, the memory 1 is kept until the number of failures in the memory block 2 exceeds the comparison value set in the device. Therefore, the memory 1 can be used continuously.

  In addition, since the block failure information acquisition unit 6 can acquire information for specifying a failure of the memory 1 in units of memory blocks by various means even when the memory 1 is being used, Repair and replacement can be performed, and work quality is improved.

  In this embodiment, the main components of the present invention are extracted. As a practical embodiment, there is a memory failure detection device used for the memory of a transmission device that needs to store a lot of setting information. is assumed. Hereinafter, an embodiment using the above-described technical concept as a memory failure detection device used for a main backup memory and a memory chip of a transmission device will be described below.

<Embodiment 2>
A block diagram of the invention according to this embodiment is shown in FIG. Here, the memory 1 corresponds to a main backup memory or a memory chip of the transmission apparatus. Compared with FIG. 1, FIG. 2 includes a switch 7 and a failure notification processing unit 8, and further includes a block failure information storage unit 9 as a block failure information acquisition unit 6 and a memory failure lighting display unit 10.

  The switch 7 is connected to the memory failure determination unit 5 and enables setting of a comparison value from the outside. In addition, the failure notification processing unit 8 connected to the memory failure determination unit 5 notifies the failure to the CPU that controls the transmission device or its host control unit when receiving a failure determination from the memory failure determination unit 5. To do. Based on the notification, the CPU and its upper control device control the transmission device itself and the memory 1.

  Further, the block failure information storage unit 9 stores and stores information for identifying the failed memory block 2 based on the detection result from the block failure detection unit 3. The memory failure lighting display unit 10 is connected to the counter 4 and lights up when the counter 4 counts 1 or more. For example, an LED or the like is used for the memory failure lighting display unit 10.

  The operation of the memory failure detection apparatus of the present embodiment configured as described above will be described.

  When a failure occurs in the memory 1, the block failure detection unit 3 detects the failure in the memory 1 in units of memory blocks. This detection is performed so as not to affect the use of the memory 1.

  The counter 4 counts the number of failed memory blocks 2 in the memory 1 based on the result of the block failure detection unit 3. Then, the memory failure determination unit 5 compares this number with the comparison value set by the switch 7, and determines that a failure occurs when the comparison value is exceeded. That is, when the number of failed memory blocks 2 in the entire memory 1 exceeds the comparison value set from the switch 7, the memory failure detection apparatus according to the present embodiment determines that the memory 1 is failed. When the memory failure determination unit 5 determines a failure, the failure notification processing unit 8 notifies the CPU or the host control device of the device failure. Based on the notification, the CPU and its upper control device control the transmission device itself and the memory 1.

  In parallel with the above operation, the block failure information storage unit 9 stores and stores information for specifying a failure of the memory 1 in units of memory blocks based on the detection result of the block failure detection unit 3. The memory failure lighting display unit 10 lights up when the counter 4 counts 1 or more, that is, when even one memory block 2 fails.

  With the above operation, according to the memory failure detection device according to the present embodiment, even when a part of the memory 1 fails, the memory until the number of failures in the memory block 2 exceeds the comparison value set by the user. Since 1 is not determined to be a failure, and the CPU and its host control device are not notified of the failure, the use of the memory 1 and the operation of the transmission device can be continued. As a result, the comparison value is increased from the switch 7 when the continuous operation of the transmission apparatus is necessary even if a part of the memory 1 is out of order, and the comparison is performed when the continuous operation of the transmission apparatus is unnecessary and the failure detection accuracy of the memory 1 is to be increased. As the value is lowered, the operability of the memory 1, the transmission device, and the failure detection accuracy of the memory 1 can be changed according to the user's request.

  Further, since the block failure information storage unit 9 stores information for specifying a failure of the memory 1 in units of memory blocks, even if the memory 1 is in use, the information can be stored by connecting an external terminal or the like. Can be obtained from outside. As a result, planned repair and replacement of the memory 1 can be performed, and work quality is improved.

  The memory failure lighting display unit 10 lights up when even one memory block fails, that is, when a failure occurs in the memory 1. Thereby, it can always be confirmed whether the memory 1 has failed. Furthermore, if a failure is confirmed in the memory failure lighting display unit 10 and then the information in the block failure information storage unit 9 is confirmed, a quick investigation can be performed regarding the failure of the memory 1.

<Embodiment 3>
A block diagram of the invention according to this embodiment is shown in FIG. Compared with the configuration of the invention of FIG. 2, the CPU 11 and the external terminal 12 are connected to the memory failure determination unit 5 instead of the switch 7.

  The value set by the external terminal 12 is transmitted to the memory failure determination unit 5 via the communication network and the CPU 11 and used as a comparison value.

  The operation of the memory failure detection apparatus of the present embodiment configured as described above will be described.

  When a failure occurs in the memory 1, the block failure detection unit 3 detects the failure in the memory 1 in units of memory blocks. This detection is performed so as not to affect the use of the memory 1.

  The counter 4 counts the number of failed memory blocks 2 in the memory 1 based on the result of the block failure detection unit 3. Then, the memory failure determination unit 5 compares this number with the comparison value set by the external terminal 12, and determines that a failure occurs when the comparison value is exceeded. That is, when the number of failed memory blocks 2 in the entire memory 1 exceeds the comparison value set remotely from the external terminal 12 via the communication network and the CPU 11, the memory failure detection according to the present embodiment The apparatus determines that the memory 1 is faulty. When the memory failure determination unit 5 determines a failure, the failure notification processing unit 8 notifies the CPU or the host control device of the device failure. Based on the notification, the CPU and its upper control device control the transmission device itself and the memory 1.

  In parallel with the above operation, the block failure information storage unit 9 stores and stores information for specifying a failure of the memory 1 in units of memory blocks based on the detection result of the block failure detection unit 3. The memory failure lighting display unit 10 lights up when the counter 4 counts 1 or more, that is, when even one memory block 2 fails.

  With the above operation, according to the memory failure detection device according to the present embodiment, even if a part of the memory 1 fails, the comparison value set by the user who is far away from the number of failures in the memory block 2 is obtained. The memory 1 is not determined to be out of order until it exceeds, and the CPU and its host control device are not notified of the failure, so that the use of the memory 1 and the operation of the transmission device can be continued. As a result, even if some of the memories 1 fail, the comparison value is remotely increased from the external terminal 12 when continuous operation of the transmission apparatus is necessary, and the continuous detection of the transmission apparatus is unnecessary and the failure detection accuracy of the memory 1 The memory 1, the operability of the transmission apparatus, and the failure detection accuracy of the memory 1 can be changed according to the user's request so that the comparison value is lowered when it is desired to increase the value. In the case of a transmission apparatus, there are often no users nearby. Therefore, it becomes possible to set the comparison value from a remote location, thereby quickly changing the comparison value and deleting the time required for the user to move to the transmission device.

  Further, since the block failure information storage unit 9 stores information for specifying a failure of the memory 1 in units of memory blocks, even if the memory 1 is in use, the information can be stored by connecting an external terminal or the like. Can be obtained from outside. As a result, planned repair and replacement of the memory 1 can be performed, and work quality is improved.

  The memory failure lighting display unit 10 lights up when even one memory block fails, that is, when a failure occurs in the memory 1. Thereby, it can always be confirmed whether the memory 1 has failed. Furthermore, if a failure is confirmed in the memory failure lighting display unit 10 and then the information in the block failure information storage unit 9 is confirmed, a quick investigation can be performed regarding the failure of the memory 1.

<Embodiment 4>
FIG. 4 shows a block diagram of the invention according to this embodiment. Compared with the configuration of the invention of FIG. 2, a block failure lighting display unit 13 is connected to the block failure detection unit 3 instead of the block failure information storage unit 9 and the memory failure lighting display unit 10.

  Based on the detection result from the block failure detection unit 3, the block failure lighting display unit 13 lights and displays information for specifying the failed memory block 2. For example, the block failure lighting display unit 13 is configured by the same number of LEDs 14 as the memory block 2, and the failed memory block 2 is lit and displayed in a one-to-one correspondence with the memory block 2. Or if this correspondence is made to correspond to the combination of lighting by a plurality of LEDs 14, the number of LEDs can be reduced.

  The operation of the memory failure detection apparatus of the present embodiment configured as described above will be described.

  When a failure occurs in the memory 1, the block failure detection unit 3 detects the failure in the memory 1 in units of memory blocks. This detection is performed so as not to affect the use of the memory 1.

  The counter 4 counts the number of failed memory blocks 2 in the memory 1 based on the result of the block failure detection unit 3. Then, the memory failure determination unit 5 compares this number with the comparison value set by the switch 7, and determines that a failure occurs when the comparison value is exceeded. That is, when the number of failed memory blocks 2 in the entire memory 1 exceeds the comparison value set from the switch 7, the memory failure detection apparatus according to the present embodiment determines that the memory 1 is failed. When the memory failure determination unit 5 determines a failure, the failure notification processing unit 8 notifies the CPU or the host control device of the device failure. Based on the notification, the CPU and its upper control device control the transmission device itself and the memory 1.

  In parallel with the above operation, the block failure lighting display unit 13 lights and displays information for specifying a failure of the memory 1 in units of memory blocks based on the detection result of the block failure detection unit 3.

  With the above operation, according to the memory failure detection device according to the present embodiment, even when a part of the memory 1 fails, the memory until the number of failures in the memory block 2 exceeds the comparison value set by the user. Since 1 is not determined to be a failure, and the CPU and its host control device are not notified of the failure, the use of the memory 1 and the operation of the transmission device can be continued. As a result, the comparison value is increased from the switch 7 when the continuous operation of the transmission apparatus is necessary even if a part of the memory 1 is out of order, and the comparison is performed when the continuous operation of the transmission apparatus is unnecessary and the failure detection accuracy of the memory 1 is to be increased. As the value is lowered, the operability of the memory 1, the transmission device, and the failure detection accuracy of the memory 1 can be changed according to the user's request.

  Further, since the block failure lighting display unit 13 lights and displays information for specifying a failure of the memory 1 in units of memory blocks, the information can be acquired from the outside even when the memory 1 is in use. . Further, if even one memory block 2 fails, it is lit and displayed, so it is possible to always check whether or not the memory 1 has failed. As a result, planned repairs and replacements can be performed, and work quality is improved. Although the obtained effect is almost the same as the configuration of FIG. 2, which configuration is to be determined may be determined according to requests such as circuit simplification and cost.

1 is a block diagram of a memory failure detection device according to a first embodiment. 6 is a block diagram of a memory failure detection apparatus according to Embodiment 2. FIG. FIG. 10 is a block diagram of a memory failure detection device according to a third embodiment. FIG. 10 is a block diagram of a memory failure detection device according to a fourth embodiment.

Explanation of symbols

1 memory, 2 memory block, 3 block failure detection unit, 4 counter, 5 memory failure determination unit, 6 block failure information acquisition unit, 7 switch, 8 failure notification processing unit, 9 block failure information storage unit, 10 memory failure lighting display Part, 11 CPU, 12 external terminal, 13 block failure lighting display part, 14 LED.

Claims (8)

A memory failure detection apparatus comprising a plurality of memory blocks,
A block failure detection unit for detecting a failure of the memory in units of the memory block;
A counter that counts the number of the memory blocks that have failed based on the detection result in the block failure detection unit;
A memory failure determination unit that determines failure when the number counted by the counter exceeds a preset comparison value;
A block failure information acquisition unit that enables external acquisition of information identifying the memory block that has failed based on the detection result in the block failure detection unit;
A memory failure detection apparatus comprising: The memory failure detection device according to claim 1, further comprising a switch for setting the comparison value from the outside. The memory failure detection device according to claim 1, further comprising means for remotely setting the comparison value via a communication network. The memory failure detection device according to claim 1, wherein the block failure information acquisition unit includes a block failure information storage unit that stores failure information in units of the memory blocks. The memory failure detection device according to claim 4, further comprising a memory failure lighting display unit for lighting and displaying the failure of the memory when the counter counts 1 or more. The memory failure detection device according to claim 1, wherein the block failure information acquisition unit includes a block failure lighting display unit that lights and displays a failure in units of the memory blocks. A memory failure detection apparatus comprising a plurality of memory blocks,
A block failure detection unit for detecting a failure of the memory in units of the memory block;
A counter that counts the number of the memory blocks that have failed based on the detection result in the block failure detection unit;
A memory failure determination unit that determines failure when the number counted by the counter exceeds a preset comparison value;
A memory failure detection apparatus comprising: A memory failure detection apparatus comprising a plurality of memory blocks,
A block failure detection unit for detecting a failure of the memory in units of the memory block;
A block failure information acquisition unit that enables external acquisition of information identifying the memory block that has failed based on the detection result in the block failure detection unit;
A memory failure detection apparatus comprising:

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