JP2007134567A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which effectively prevents the signal delay of wiring by effectively reducing a wiring capacity, and also to provide its manufacturing method. <P>SOLUTION: A trench 116 for forming a second wiring layer, and a first via hole 117 for forming a connection layer are formed on a third insulating film 105. A barrier layer 108 is subsequently formed on the inner side surfaces of the trench and the first via hole 117. A second via hole 117 which reaches a first wiring layer 101 is formed on a second insulating film 104 via the trench 116, and the first via hole 117 with the barrier layer 108 is formed on the inner side surfaces. An oxide layer 119 formed on the surface of the first wiring layer 101 is removed. It is prevented on the barrier layer 108 that permittivity is extremely increased by extreme change in the quality of the third insulating film with etching in forming the second via hole 117 or with plasma for removing the oxide layer 119. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  In recent years, with high integration and reduction in chip size, semiconductor devices have been miniaturized and multi-layered. In a semiconductor device having a miniaturized multilayer wiring, signal delay of the wiring becomes a problem. Since the signal delay is proportional to the product of the wiring resistance and the wiring capacitance, it is necessary to reduce the wiring resistance and the wiring capacitance in order to improve the signal delay.

  As a method for reducing the wiring resistance of a semiconductor device, there is a method of using copper having a resistivity lower than that of aluminum instead of aluminum as a wiring material. However, even if low resistance copper is used as the wiring material, there is a problem that the resistance value tends to be high due to the miniaturization of the wiring in the multilayer wiring. This problem of the resistance value is particularly noticeable when the diameter of the via hole connecting the upper layer wiring and the lower layer wiring is reduced by miniaturization. This increase in resistance value in the via hole is caused by a barrier metal formed at the bottom of the via hole and having a higher resistivity than copper, and an oxide layer formed on the surface of the lower wiring. As a method for solving the problem of the via hole resistance value, conventionally, a method of removing the barrier metal at the bottom of the via hole by an Ar sputtering method (see JP 2001-284449 A: Patent Document 1), or an oxide layer on the surface of the lower layer wiring There is a method of reducing by hydrogen plasma treatment (see Japanese Patent Application Laid-Open No. 2001-18884: Patent Document 2).

  As a method for reducing the wiring capacitance of a semiconductor device, a low dielectric constant film having a dielectric constant lower than that of the silicon oxide film is used as the insulating film instead of the silicon oxide film having a relative dielectric constant of about 4. There is a way.

However, in the conventional semiconductor device, even when a low dielectric constant film is used as an insulating film between the upper layer wiring and the lower layer wiring, a trench or via hole for forming the upper layer wiring is formed in the insulating film. The dielectric film is improved by etching, sputtering when removing the barrier metal at the bottom of the via hole, and plasma treatment when removing the oxide layer on the surface of the lower layer wiring. Therefore, there is a problem that the effect of reducing the wiring capacitance of the insulating film is diminished and signal delay occurs in the multilayer wiring.
JP 2001-284449 A JP 2001-118846 A

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device that can effectively reduce wiring capacitance and effectively prevent signal delay of wiring, and a method for manufacturing the same.

In order to solve the above problems, a semiconductor device of the present invention includes a first wiring layer formed by embedding a first wiring material in a first insulating film,
A second insulating film formed on the first wiring layer and preventing diffusion of the first wiring material;
A third insulating film formed on the second insulating film and made of a low dielectric constant material;
A second wiring layer formed by burying a second wiring material in a trench formed in the third insulating film;
A portion of the third insulating film that is closer to the second insulating film than the bottom surface of the trench and the second insulating film, the second wiring material is embedded, and the first wiring layer A via hole connecting the second wiring layer;
And a barrier layer covering the side and bottom surfaces of the trench formed in the third insulating film and the side surface of the portion of the via hole formed in the third insulating film.

  According to the above configuration, the barrier layer is formed on the side surface and bottom surface of the trench and the side surface of the via hole after forming the trench and the via hole portion in the third insulating film. Another portion of the via hole can be formed in the second insulating film through the trench and the via hole formed on the inner surface of the barrier layer. Therefore, when the other part of the via hole is formed by etching, for example, the barrier layer can prevent the etchant from coming into contact with the third insulating film. As a result, it is possible to prevent the third insulating film from being significantly modified and the dielectric constant from being significantly increased.

  Further, when forming the via hole portion in the second insulating film, an oxide layer is formed on the surface portion of the first wiring layer exposed on the bottom surface of the via hole by, for example, etching processing for forming the via hole. May be. Even in this case, for example, plasma treatment for removing the oxide layer can be performed through a trench and a via hole in which the barrier layer is formed on the inner surface. Therefore, it is possible to prevent the dielectric constant from being significantly increased due to the significant modification of the third insulating film due to the plasma treatment. In addition, since there is no barrier layer between the bottom of the via hole of the second insulating film and the surface of the first wiring layer, the wiring resistance is not increased by the barrier layer.

  As described above, the semiconductor device of the present invention can prevent an increase in the dielectric constant of the third insulating film, and can also provide wiring at the contact portion between the second wiring material and the first wiring layer at the bottom of the via hole. An increase in resistance can be prevented. As a result, it is possible to effectively prevent a delay of a signal transmitted between the first wiring layer and the second wiring layer.

  In the semiconductor device according to an embodiment, the portion of the third insulating film adjacent to the barrier layer increases at a rate of 10% or less with respect to the dielectric constant of other regions of the third insulating film. A dielectric constant increasing region having a dielectric constant is formed.

  According to the embodiment, the other portion of the via hole is formed in the second insulating film in the presence of the barrier layer, so that the dielectric of the increased dielectric constant region formed in the third insulating film is formed. The rate is suppressed to an increase rate of 10% or less with respect to the dielectric constant of other regions of the third insulating film. Thereby, with respect to the second wiring layer formed in the third insulating film and a part of the via hole, the effect of reducing the wiring capacitance by the third insulating film can be exerted, so that signal delay can be prevented. Can be done effectively.

  In the semiconductor device of one embodiment, the second wiring material is copper or a copper alloy.

  According to the embodiment, the wiring resistance between the first wiring layer and the second wiring layer can be reduced by filling the trench and the via hole with copper or a copper alloy.

  In one embodiment, the third insulating film is made of a low dielectric constant material having a relative dielectric constant of 1 or more and 4 or less.

  According to the embodiment, the wiring capacity can be effectively reduced for the second wiring layer formed in the third insulating film and the second wiring material in the via hole of the third insulating film. .

  In one embodiment, the barrier layer includes at least one of Ti, Ta, W, and Ru, or a nitrogen compound thereof.

  According to the embodiment, it is possible to effectively prevent the second wiring material embedded in the trench and the via hole of the third insulating film from diffusing into the third insulating film.

According to a second aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: a second wiring layer that prevents diffusion of the first wiring material on a first wiring layer formed by burying a first wiring material in a first insulating film; Forming an insulating film;
Forming a third insulating film made of a low dielectric constant material on the second insulating film;
A trench located on the surface portion of the third insulating film, and a portion of the third insulating film located on the second insulating film side from the bottom surface of the trench through the bottom surface of the trench, Forming a first via hole reaching the surface of the two insulating films;
Forming a barrier layer on the side and bottom surfaces of the trench and the side surface of the first via hole;
Forming a second via hole that penetrates the second insulating film from the bottom surface of the first via hole and reaches the surface of the first wiring layer;
Removing the surface portion of the first wiring layer exposed at the bottom of the second via hole;
And a step of burying a second wiring material in the trench, the first via hole, and the second via hole.

  According to the above configuration, the second insulating film is formed on the first wiring layer formed on the first insulating film, and the third insulating film is formed on the second insulating film. Is done. A trench is formed in the surface portion of the third insulating film. A first via hole that penetrates from the bottom surface of the trench to a portion of the third insulating film located on the second insulating film side of the bottom surface of the trench and reaches the surface of the second insulating film is formed. It is formed. Any of the formation order of the trench and the first via hole may be first. Barrier layers are formed on the side and bottom surfaces of the trench and the side surface of the first via hole. From the bottom surface of the first via hole, a second via hole penetrating the second insulating film and reaching the surface of the first wiring layer is formed. The second via hole is formed by, for example, etching through the trench and the first via hole. At this time, the barrier layer formed on the inner surface of the trench and the first via hole prevents the third insulating film from contacting the etchant. As a result, the third insulating film is significantly modified, and the dielectric constant is prevented from significantly increasing.

  When the second via hole is formed, for example, an oxide layer is formed on the surface of the first wiring layer exposed at the bottom of the second via hole. This oxide layer is removed by the removal process of the surface portion of the first wiring layer. This prevents an increase in wiring resistance between the first wiring layer and the second wiring material embedded in the second via hole.

  Further, the removal of the surface portion of the first wiring layer can be performed by, for example, plasma processing through the trench and the first via hole. Even in this case, the barrier layer formed on the inner surface of the trench and the first via hole prevents the third insulator from being significantly modified by plasma and the dielectric constant from being significantly increased. .

  In addition, since the barrier layer is not formed between the second wiring material embedded in the second via hole and the first wiring layer, the barrier layer does not increase the wiring resistance.

  Thus, according to the method for manufacturing a semiconductor device of the present invention, an increase in wiring resistance between the connection layer and the first wiring layer can be prevented, and the third insulating film can be greatly modified. Thus, a semiconductor device that can prevent an increase in the dielectric constant due to the above is manufactured. Therefore, it is possible to obtain a semiconductor device that can effectively prevent delay of a signal transmitted between the first wiring layer and the second wiring layer.

  In one embodiment of the method for manufacturing a semiconductor device, the second wiring material is copper or a copper alloy.

  According to the embodiment, the trench and the first and second via holes are filled with copper or a copper alloy, thereby effectively reducing the wiring resistance between the first wiring layer and the second wiring layer. it can.

  In one embodiment, the third insulating film is formed of a low dielectric constant material having a relative dielectric constant of 1 or more and 4 or less.

  According to the embodiment, the wiring capacitance can be effectively reduced with respect to the second wiring layer formed in the third insulating film and the second wiring material in the first via hole.

  In one embodiment, the barrier layer includes at least one of Ti (titanium), Ta (tantalum), W (tungsten), and Ru (ruthenium), or a nitrogen compound thereof.

  According to the above embodiment, it is possible to effectively prevent the second wiring material embedded in the trench and the first via hole in the third insulating film from diffusing into the third insulating film.

  In one embodiment of the method of manufacturing a semiconductor device, in the step of forming the barrier layer, the barrier layer material is deposited by sputtering on the inner surface of the trench and the first via hole, and the bottom surface of the first via hole is formed. The material of the barrier layer deposited on is removed by Ar sputtering.

  According to the embodiment, the barrier layer is formed on the side surface and the bottom surface of the trench and the side surface of the first via hole without forming the barrier layer on the bottom surface of the first via hole by a small number of steps. Can do.

  In one embodiment of the method of manufacturing a semiconductor device, the step of forming the second via hole removes a portion of the second insulating film from the bottom surface of the first via hole by a plasma etching method.

  According to the embodiment, since the plasma etching method is performed through the trench and the first via hole in which the barrier layer is formed on the inner surface, the third insulating film is prevented from being significantly modified. The dielectric constant can be prevented from significantly increasing.

  As described above, the semiconductor device of the present invention has a barrier layer that covers the bottom and side surfaces of the trench formed in the third insulating film and the side surface of the portion of the via hole formed in the third insulating film. In the state where the third insulating film is protected by this barrier layer, another part of the via hole is formed in the second insulating film by, for example, etching process through the trench and the via hole part, and For example, the surface portion of the first wiring layer can be removed by plasma treatment. Therefore, it is possible to prevent the third insulating film from being significantly modified, to prevent a large increase in the dielectric constant, and to effectively prevent signal delay in the semiconductor device.

  Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.

  FIG. 1 is a diagram showing a semiconductor device according to an embodiment of the present invention. This semiconductor device includes a first insulating film 100, and a first wiring layer 101 is embedded in the surface portion of the first insulating film 100. In the first wiring layer 101, for example, a trench is formed in the first insulating film 100, an inner surface of the trench is covered with a first barrier metal 102, and a first wiring material is formed in the trench. It is formed by filling.

  On the surface of the first insulating film 100 and on the surface of the first wiring layer 101, a second insulating film 104 for preventing diffusion of the first wiring material is laminated. The second insulating film 104 is made of SiC. In addition to SiC, the second insulating film may be formed using, for example, SiN or SiCN obtained by adding N to SiC. A third insulating film 105 made of SiOC, which is a low dielectric constant material, is laminated on the second insulating film 104. In addition to SiOC, the third insulating film may be formed of, for example, SiOF.

  A second wiring layer 107 is embedded in the surface portion of the third insulating film 105. The second wiring layer 107 covers the second barrier metal 108 as a barrier layer on the side and bottom surfaces of the trench formed in the third insulating film 105, and the second barrier metal 108 is covered. A second wiring material is embedded in the trench. A connection layer 112 is formed between the second wiring layer 107 and the first wiring layer 101. The connection layer 112 is formed in a via hole that penetrates the portion of the third insulating film 105 from the bottom surface of the trench in which the second wiring layer 107 is formed, and further penetrates the second insulating film 104. ing. The connection layer 112 is formed integrally with the second wiring layer 107 by the second wiring material. A second barrier metal 108 in contact with the second wiring layer 107 extends and contacts the side surface of the connection layer 112. The second barrier metal 108 is provided in a portion where the via hole penetrates the third insulating film 105, but is not provided in a portion where the via hole penetrates the second insulating film 104. Therefore, the connection layer 112 is in contact with the second insulating film 104. A dielectric constant increasing region 114 is formed in the vicinity of the portion of the third insulating film 105 in contact with the second barrier metal 108. The dielectric constant increasing region 114 has a dielectric constant that is about 10% larger than the dielectric constant of other regions of the third insulating film 105 at the maximum.

  The semiconductor device of this embodiment is manufactured as follows.

  First, as shown in FIG. 2, a trench is formed in the surface portion of the first insulating film 100, and the inner surface of the trench is covered with a first barrier metal 102, and the first barrier metal 102 is covered. A first wiring layer 101 is formed by embedding a first wiring material in the trench. A second insulating film 104 and a third insulating film 105 are deposited on the first insulating film 100 on which the first wiring layer 101 is formed. The second insulating film 104 is formed of a SiC film having a thickness of about 50 nm, for example. The third insulating film 105 is formed of, for example, a SiOC film (relative dielectric constant is about 2.9) or a SiOF film (relative dielectric constant is about 3.7) having a thickness of about 600 nm. Note that the film thickness 105 of the third insulating film can be appropriately set in the range of 300 to 700 nm.

  Next, as shown in FIG. 3, a trench 116 is formed in the surface portion of the third insulating film 105 by a known photo and etching technique, and the surface of the second insulating film 104 is further formed from the bottom of the trench 116. A first via hole 117 reaching the above is formed. The depth of the trench 116 can be set to about 400 nm from the surface of the third insulating film 105, for example. The depth of the first via hole 117 can be set to about 200 nm from the bottom surface of the trench 116, for example. At this time, a dielectric constant increasing region 114 is formed in the surface portion of the third insulating film 105, in the vicinity of the side surface and bottom surface of the trench 116, and in the vicinity of the side surface of the first via hole 117. The increased dielectric constant region 114 is formed by modifying the third insulating film 105 by an etching process for forming the trench 116 and the first via hole 117 and a plasma process performed for removing the resist film. The However, the rate of increase of the dielectric constant in the dielectric constant increasing region 114 is relatively small, about 10% or less with respect to the original third insulating film 105.

  Next, as shown in FIG. 4, the second barrier metal 108 is deposited so as to cover the inner surface of the trench 116 and the first via hole 117 formed in the third insulating film 105. At the same time, the barrier metal material deposited at the bottom of the first via hole 117 is removed, and the second insulating film 104 is exposed at the bottom of the first via hole 117. The second barrier metal 108 is formed, for example, by depositing TaN to a thickness of about 30 nm by reactive sputtering. The barrier metal material deposited on the bottom of the first via hole 117 is removed by Ar sputtering. In this Ar sputtering method, TaN deposited on the bottom of the first via hole 117 is sputter-etched using Ar plasma that has been applied with a high-frequency bias to improve straightness. The film thickness of TaN deposited on the bottom of the first via hole 117 by the reactive sputtering method is thinner than the film thickness of TaN deposited on the surface of the third insulating film 105 and the bottom of the trench 116. Therefore, even if TaN at the bottom of the first via hole 117 is removed by the Ar sputtering method, a TaN film remains on the surface of the third insulating film 105 and the bottom of the trench 116. In addition to TaN, any one of Ti, Ta, W, and Ru, or a nitrogen compound thereof may be used for the second barrier metal 108.

  Next, as shown in FIG. 5, a second via hole 118 that is continuous with the first via hole 117 is formed in the second insulating film 104 exposed at the bottom of the first via hole 117. The second via hole 118 is formed to a depth reaching the surface of the first wiring layer 101 from the bottom surface of the first via hole 117. The second via hole 118 is formed by removing the portion of the second insulating film 104 exposed on the bottom surface of the first via hole 117 through the first via hole 117 by reactive ion etching. Note that chemical etching may be used in combination when the surface of the first wiring layer 101 is exposed.

  When the second via hole 118 is formed by the reactive ion etching method, the inner surface of the trench 116 and the first via hole 117 formed in the third insulating film 105 having a low dielectric constant is formed on the second barrier metal 108. Therefore, an increase in dielectric constant due to exposure to plasma is effectively prevented.

Subsequently, as shown in FIG. 6, the oxide layer 119 formed on the surface portion of the first wiring layer 101 exposed on the bottom surface of the second via hole 118 is removed. The oxide layer 119 of the first wiring layer 101 is removed, for example, by reduction by H ₂ plasma treatment. At this time, since the inner surface of the trench 116 and the first via hole 117 formed in the third insulating film 105 having a low dielectric constant is covered with the second barrier metal 108, the dielectric constant by the H ₂ plasma treatment is used. Is effectively prevented from rising. Note that when the third insulating film 105 is not covered with the second barrier metal 108 as in the conventional manufacturing process, the increase rate of the dielectric constant by the H ₂ plasma treatment is 20 to 30%, The wiring capacity is greatly increased.

  Subsequently, as shown in FIG. 7, a metal wiring material 120 is filled in the trench 116 and the first and second via holes 117 and 118. Specifically, for example, an electrode copper seed layer for electrolytic plating is deposited to a thickness of 100 nm by sputtering at the bottom of the second via hole 118, and then copper is deposited to 600 nm by copper electrolytic plating on the electrode copper seed layer. Deposited to a thickness of. This copper deposition is performed until the second barrier metal 108 formed on the surface of the third insulating film 105 is covered.

  Finally, as shown in FIG. 8, the dielectric constant increasing region 114 on the surface portion of the third insulating film 105, the surplus second barrier metal 108 formed on the surface of the third insulating film 105, and the wiring material 120 is removed by a CMP (Chemical Mechanical Polishing) method. As a result, the second wiring layer 107 is formed in the third insulating film 105 and the connection layer 112 is formed in the third and second insulating films 105 and 104.

  The semiconductor device manufactured as described above is formed in the vicinity of the surface (the side surface and the bottom surface of the trench 116 and the side surface of the first via hole 117) in contact with the second barrier metal 108 of the third insulating film 105. In the dielectric constant increasing region 114, the rate of increase in the dielectric constant is 10% or less with respect to the dielectric constant of other regions of the third insulating film 105. Therefore, the second wiring layer 107 and the connection layer 112 that are adjacent to the dielectric constant increasing region 114 with the second barrier metal 108 therebetween are effectively prevented from increasing the wiring capacitance. Further, since there is no barrier metal between the bottom of the connection layer 112 and the surface of the first wiring layer 101, an increase in wiring resistance between the connection layer 112 and the first wiring layer 101 is prevented. it can. As a result, this semiconductor device can effectively prevent signal delay with respect to signals transmitted through the first wiring layer 101, the connection layer 112, and the second wiring layer 107.

  The second barrier metal 108 as the barrier layer is formed of TaN, but may be a barrier layer formed using a material other than metal. In short, the diffusion of the second wiring material into the third insulating film 105 can be prevented, and the third insulating film 105 can be greatly reduced during the etching of the second insulating film 104 and the plasma treatment of the oxide layer 119. Any material may be used as long as it is possible to prevent any modification.

It is a figure which shows the semiconductor device of embodiment of this invention. It is a figure which shows a mode that the 2nd insulating film and the 3rd insulating film were formed on the 1st insulating film in which the 1st wiring layer was formed. It is a figure which shows a mode that the trench and the via hole were formed in the 3rd insulating film. It is a figure which shows a mode that the barrier metal was formed in the inner surface of a trench and a via hole. It is a figure which shows a mode that the 2nd via hole continuing to the 1st via hole formed in the 3rd insulating film was formed in the 2nd insulating film. It is a figure which shows a mode that the oxide layer formed in the surface of the 1st wiring layer was removed. It is a figure which shows a mode that the metal wiring material was filled in the trench and the 1st and 2nd via hole. It is a figure which shows a mode that the dielectric constant increase area | region of the surface part of the 3rd insulating film, the excess barrier metal, and the wiring material were removed.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 1st insulating film 101 1st wiring layer 102 Barrier metal 104 2nd insulating film 105 3rd insulating film 107 2nd wiring layer 108 2nd barrier metal 112 Connection layer 115 3rd insulating film 116 Trench 117 First via hole 118 Second via hole 119 Oxide layer 120 Metal wiring material

Claims (11)

A first wiring layer formed by embedding a first wiring material in a first insulating film;
A second insulating film formed on the first wiring layer and preventing diffusion of the first wiring material;
A third insulating film formed on the second insulating film and made of a low dielectric constant material;
A second wiring layer formed by burying a second wiring material in a trench formed in the third insulating film;
A portion of the third insulating film that is closer to the second insulating film than the bottom surface of the trench and the second insulating film, the second wiring material is embedded, and the first wiring layer A via hole connecting the second wiring layer;
A semiconductor device comprising: a barrier layer that covers a side surface and a bottom surface of a trench formed in the third insulating film and a side surface of a portion of the via hole formed in the third insulating film. The semiconductor device according to claim 1,
A dielectric constant increasing region having a dielectric constant increased at a rate of 10% or less with respect to a dielectric constant of other regions of the third insulating film in a portion of the third insulating film adjacent to the barrier layer. A semiconductor device characterized in that is formed. The semiconductor device according to claim 1,
The semiconductor device according to claim 2, wherein the second wiring material is copper or a copper alloy. The semiconductor device according to claim 1,
The semiconductor device, wherein the third insulating film is formed of a low dielectric constant material having a relative dielectric constant of 1 or more and 4 or less. The semiconductor device according to claim 1,
The barrier layer includes at least one of Ti, Ta, W, and Ru, or a nitrogen compound thereof. Forming a second insulating film for preventing diffusion of the first wiring material on the first wiring layer formed by embedding the first wiring material in the first insulating film;
Forming a third insulating film made of a low dielectric constant material on the second insulating film;
A trench located on the surface portion of the third insulating film, and a portion of the third insulating film located on the second insulating film side from the bottom surface of the trench through the bottom surface of the trench, Forming a first via hole reaching the surface of the two insulating films;
Forming a barrier layer on the side and bottom surfaces of the trench and the side surface of the first via hole;
Forming a second via hole that penetrates the second insulating film from the bottom surface of the first via hole and reaches the surface of the first wiring layer;
Removing the surface portion of the first wiring layer exposed at the bottom of the second via hole;
And a step of burying a second wiring material in the trench, the first via hole, and the second via hole. In the manufacturing method of the semiconductor device according to claim 6,
The method for manufacturing a semiconductor device, wherein the second wiring material is copper or a copper alloy. In the manufacturing method of the semiconductor device according to claim 6,
The method of manufacturing a semiconductor device, wherein the third insulating film is formed of a low dielectric constant material having a relative dielectric constant of 1 or more and 4 or less. In the manufacturing method of the semiconductor device according to claim 6,
The method for manufacturing a semiconductor device, wherein the barrier layer contains at least one of Ti, Ta, W, and Ru, or a nitrogen compound thereof. In the manufacturing method of the semiconductor device according to claim 6,
The step of forming the barrier layer includes depositing a barrier layer material on the inner side surfaces of the trench and the first via hole by sputtering, and applying an Ar sputtering method to the barrier layer material deposited on the bottom surface of the first via hole. A method for manufacturing a semiconductor device, characterized in that the semiconductor device is removed by: In the manufacturing method of the semiconductor device according to claim 6,
The method of forming a second via hole comprises removing a portion of the second insulating film from the bottom surface of the first via hole by a plasma etching method.

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