JP2007122766A - LCD driver - Google Patents

Abstract

In a semiconductor integrated circuit incorporating a non-volatile memory for electrically writing and erasing data, the reliability of the non-volatile memory by applying a voltage outside the proper range from the outside in order to write or erase data Prevent sexual defects.
In this semiconductor integrated circuit, a nonvolatile memory 27 in which data can be electrically written and erased, and a write voltage and an erase voltage input from the outside to be applied to the nonvolatile memory are respectively first. A determination signal having a predetermined level when the write voltage is within the first setting range and the erasing voltage is within the second setting range; A voltage comparison circuit 28 to be generated, and a logic circuit 22 that holds a determination signal generated by the voltage comparison circuit and controls writing and erasing of data in the nonvolatile memory are provided.
[Selection] Figure 2

Description

  The present invention generally relates to a semiconductor integrated circuit incorporating a nonvolatile memory such as an EEPROM (Electronically Erasable Programmable Read Only Memory) for electrically writing and erasing data, and more particularly to a display device such as a liquid crystal panel. The present invention relates to a semiconductor integrated circuit (such as a liquid crystal driver IC).

  For example, in a liquid crystal driver, a nonvolatile memory such as an EEPROM is built in, and setting information that has been written in an external memory in the past is written in the built-in nonvolatile memory. As a result, the reduction of the external memory and the price reduction of the liquid crystal module are realized.

  In a liquid crystal module manufacturer that manufactures a liquid crystal module using such a liquid crystal driver, at the time of initial setting of the liquid crystal module in a factory, setting information such as a destination ID for product shipment management and data for liquid crystal panel adjustment, It is written in advance in a non-volatile memory built in the liquid crystal driver.

  However, the nonvolatile memory built in the liquid crystal driver has a specification in which a writing voltage, an erasing voltage, a writing time, or the like differs depending on each semiconductor manufacturer. Therefore, when the liquid crystal module manufacturer writes the setting information in the nonvolatile memory, the nonvolatile memory is caused by applying an insufficient or excessive write voltage or erase voltage to the nonvolatile memory in a mistake with the specifications of another semiconductor manufacturer. There was a problem of poor reliability.

As a related technique, Patent Document 1 discloses an LCD driver provided with a writable non-volatile memory circuit unit for storing electronic volume data for setting the density of the LCD. Sharing voltage from the circuit is disclosed. However, the problem of poor reliability of the nonvolatile memory due to application of an insufficient or excessive write voltage or erase voltage has not been solved.
Japanese Patent No. 3554135 (2nd page, FIG. 1)

  Therefore, in view of the above points, in a semiconductor integrated circuit incorporating a nonvolatile memory for electrically writing and erasing data, by applying a voltage outside the proper range from the outside in order to write or erase data. An object of the present invention is to provide a semiconductor integrated circuit capable of preventing a reliability failure of a nonvolatile memory.

  In order to solve the above problems, a semiconductor integrated circuit according to one aspect of the present invention includes a nonvolatile memory in which data can be electrically written and erased, and a write input from the outside for application to the nonvolatile memory When it is determined whether the voltage and the erase voltage are within the first setting range and the second setting range, respectively, and the write voltage is within the first setting range and the erase voltage is within the second setting range Are provided with a voltage comparison circuit that generates a determination signal having a predetermined level, and a logic circuit that holds the determination signal generated by the voltage comparison circuit and controls writing and erasing of data in the nonvolatile memory.

  Here, when the voltage comparison circuit divides the write voltage input from the outside, compares the divided voltage with the first reference voltage, and the divided voltage is lower than the first reference voltage. A first comparator that generates an output signal indicating that the write voltage is within the first set range, and an erase voltage input from the outside are divided, and the divided voltage is compared with a second reference voltage. A second comparator for generating an output signal indicating that the erase voltage is within the second set range when the divided voltage is lower than the second reference voltage, and the first and second comparators A determination circuit that generates a determination signal based on the output signal may be included.

  Alternatively, the voltage comparison circuit divides the externally input write voltage, compares the divided voltage with the first reference voltage and the second reference voltage, and the divided voltage is the first reference. A first window comparator for generating an output signal indicating that the write voltage is within the first set range when having a level between the voltage and the second reference voltage, and an erase voltage input from the outside Dividing and comparing the divided voltage with the third reference voltage and the fourth reference voltage, and the divided voltage has a level between the third reference voltage and the fourth reference voltage. A second window comparator that generates an output signal indicating that the erase voltage is within the second setting range, and a determination circuit that generates a determination signal based on the output signals of the first and second window comparators. It may be included.

Further, the logic circuit may include a register that holds a determination signal generated by the voltage comparison circuit, and the determination signal held in the register may be output to the outside.
Alternatively, the logic circuit includes a register that holds a determination signal generated by the voltage comparison circuit, and the determination signal held in the register has a write voltage within the first setting range and an erase voltage set to the second setting When it indicates that it is within the range, writing and erasing of data in the nonvolatile memory may be permitted.

  In the above, the semiconductor integrated circuit displays an image on the display panel based on the MPU interface for receiving image data and setting information from the outside, the display memory for storing the image data, and the image data stored in the display memory. A segment driver that generates a segment signal for display; and a common driver that generates a timing signal for controlling image display on the display panel. The logic circuit receives image data and setting information received by the MPU interface. You may make it store in a display memory and a non-volatile memory, respectively.

  According to the present invention, data is written or erased by generating a determination signal having a predetermined level when the write voltage is within the first set range and the erase voltage is within the second set range. Therefore, it is possible to prevent a reliability failure of the nonvolatile memory due to application of a voltage outside the appropriate range from the outside.

Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to the drawings. The same constituent elements are denoted by the same reference numerals, and the description thereof is omitted.
FIG. 1 is a block diagram showing a configuration of a liquid crystal driver as a semiconductor integrated circuit and peripheral circuits thereof according to the first embodiment of the present invention. In this embodiment, a liquid crystal driver is described as an example of a semiconductor integrated circuit. However, the present invention can be applied to a semiconductor integrated circuit including a nonvolatile memory that electrically writes and erases data. .

  As shown in FIG. 1, the liquid crystal driver 20 is connected to an MPU (microprocessor) 10 and a liquid crystal panel 30. The liquid crystal driver 20 is mounted on the liquid crystal panel 30, and these constitute a liquid crystal module. The MPU 10 performs calculation and control of image data representing image information, and displays various types of image data including display image data obtained by the calculation, an address for controlling a storage area of the image data, a write control signal, and a read control signal. Control signal.

  The liquid crystal driver 20 is stored in the MPU interface 21 that receives display image data and the like from the MPU 10, a logic circuit 22 that controls each circuit, a display memory 23 that stores image data, and a display memory 23. A segment driver 24 that generates a segment signal for driving the liquid crystal panel 30 based on the image data that is present, a common driver 25 that generates a timing signal for controlling image display on the liquid crystal panel 30, and a power supply voltage supplied from the outside The power supply circuit 26 generates various power supply voltages based on the power supply voltage and supplies the power supply voltages to the segment driver 24 and the common driver 25. The logic circuit 22 stores the image data received by the MPU interface 21 in the display memory 23.

  Further, the liquid crystal driver 20 stores a setting information such as a destination ID for product shipment management and liquid crystal panel adjustment data at the time of factory shipment, and writes the setting information in the nonvolatile memory 27. And a voltage comparison circuit 28 for detecting a write voltage and an erase voltage input from the outside. The logic circuit 22 stores the setting information received by the MPU interface 21 in the nonvolatile memory 27.

FIG. 2 is a block diagram showing the configuration of the voltage comparison circuit in the first embodiment of the present invention.
As shown in FIG. 2, the voltage comparator circuit 28, the reference voltage and the resistor R1 and R2 for dividing the write voltage _{V W} inputted from the outside, and voltage _V W obtained by partial pressure R2 / (R1 + R2) compared with comparator 41 to be compared with the V _REF1, and resistors R3 and R4 for dividing the erase voltage _{V E} which is input from the outside, the voltage _V E · R4 / obtained by the partial pressure (R3 + R4) and the reference voltage _{V REF2} and And a determination circuit that determines whether or not the write voltage V _W and the erase voltage _VE are within a set range based on the comparison results of the comparators 41 and 42, and outputs a determination signal S1 representing the determination result 43. The determination signal S1 output from the determination circuit 43 is stored in the status register in the logic circuit 22 shown in FIG.

Next, the operation of the semiconductor integrated circuit according to the present embodiment will be described with reference to FIGS.
When writing setting information such as a destination ID for product shipment management and liquid crystal panel adjustment data in the nonvolatile memory 27, a setting information writing device is connected to the liquid crystal driver 20, and a writing voltage and an erasing voltage are connected. Is input to the liquid crystal driver 20.

Referring to FIG. 2, in the comparator 41 included in the voltage comparison circuit 28, the voltage V _W · R2 / (R1 + R2) obtained by dividing the write voltage V _W by the resistors R1 and R2 is greater than the reference voltage V _REF1 . When it is large, a high level signal is output, and when the voltage _VW · R2 / (R1 + R2) is smaller than the reference voltage _VREF1 , a low level signal is output. The comparator 42 outputs a high level signal when the voltage _{V E · R4 / (R3 +} R4) is larger than the reference voltage _{V REF2} obtained by dividing the erase voltage _{V E} by resistors R3 and R4, the voltage _{V E} When R4 / (R3 + R4) is smaller than the reference voltage _VREF2 , a low level signal is output.

As a result, the externally input write voltage V _W and erase voltage _VE are compared with the first set voltage and the second set voltage. The determination circuit 43 is configured by, for example, an OR circuit, and outputs a low-level determination signal S1 when both the output signal of the comparator 41 and the output signal of the comparator 42 are at a low level. When one of the output signals of the comparator 42 is at a high level, the determination signal S1 at a high level is output. Therefore, if the determination signal S1 is at a low level, the write voltage _VW is within a setting range smaller than the first setting voltage, and the erasing voltage _VE is within a setting range smaller than the second setting voltage. I know that there is. In addition, the determination circuit 43 stores the determination signal S <b> 1 in a status register in the logic circuit 22.

  The setting information writing device receives the determination signal S1 stored in the status register in the logic circuit 22 via the MPU interface 21, and the write voltage and the erase voltage are within the set range based on the determination signal S1. Displays whether or not it exists. As a result, the operator can write or erase data in the nonvolatile memory 27 after confirming that the write voltage and the erase voltage are within the set range. The apparatus for writing setting information outputs setting information and a write command to the logic circuit 22 via the MPU interface 21 according to the operation of the operator, and the logic circuit 22 writes the setting information to the nonvolatile memory 27.

  Alternatively, when the determination signal S1 indicating that the write voltage and the erase voltage are within the setting range is stored in the status register, the logic circuit 22 permits the data write and erase to the nonvolatile memory 27. May be. As a result, a write voltage or erase voltage outside the set range is not applied to the nonvolatile memory 27.

  As a result, it is possible to prevent a defective reliability of the nonvolatile memory caused by the application of a write voltage or an erase voltage outside the set range and improve the yield in mounting. Further, when a transparent wiring using an ITO (Indium Tin Oxide) thin film using a sputtering method is used, the voltage applied to the nonvolatile memory 27 can be detected even if the resistance value of the wiring is somewhat large. .

  Next, a second embodiment of the present invention will be described. The second embodiment is different from the first embodiment in the configuration of the voltage comparison circuit, and is otherwise the same as the first embodiment.

FIG. 3 is a block diagram showing the configuration of the voltage comparison circuit in the second embodiment of the present invention. In this embodiment, the reference voltage for determining the lower limit value of the write voltage setting range is V _W1 , the reference voltage for determining the upper limit value of the write voltage setting range is (V _W1 + V _W2 ), and the erase voltage setting range is The reference voltage for determining the lower limit value is V _E1 , and the reference voltage for determining the upper limit value of the erase voltage setting range is (V _E1 + V _E2 ).

As shown in FIG. 3, the voltage comparator circuit 50, the reference voltage and the resistor R5 and R6 for dividing the write voltage _{V W} inputted from the outside, and voltage _V W obtained by partial pressure R6 / a (R5 + R6) V _W1 and _(V W1 ₊ V _W2) as the window comparator 51 to be compared with, resistors R7 and R8 for dividing the erase voltage _{V E} which is input from outside, a voltage obtained by voltage dividing _{V E · R8 / (R7 +} R8 ) With the reference voltages V _E1 and (V _E1 + V _E2 ), and based on the comparison results of the window comparators 51 and 52, whether or not the write voltage V _W and the erase voltage V _E are within the set range. And a determination circuit 53 that outputs a determination signal S2 representing the determination result. The determination signal S2 output from the determination circuit 53 is stored in the status register in the logic circuit 22 shown in FIG.

Window comparator 51 includes a comparator 44 for comparing the resistors R5 and R6 voltage obtained by dividing the write voltage _{V W} min by _{V W · R6 / (R5 +} R6) and the reference voltage _{V W1,} voltage _{V W · R6 / (R5 +} R6 ) _Is compared with a reference voltage (V _W1 + V _W2 ), and a NAND circuit 46 that obtains the logical product of the output signals of the comparators 44 and 45, inverts the logical product, and outputs the logical product.

The window comparator 52 compares the voltage V _E · R8 / (R7 + R8) obtained by dividing the erase voltage V _E with the resistors R7 and R8 with the reference voltage V _E1 , and the voltage V _E · R8 / A comparator 48 that compares (R7 + R8) with a reference voltage (V _E1 + V _E2 ), and a NAND circuit 49 that obtains a logical product of the output signals of the comparators 47 and 48, inverts the logical product, and outputs the logical product.

Next, the operation of the semiconductor integrated circuit according to the present embodiment will be described with reference to FIGS.
When writing setting information such as a destination ID for product shipment management and liquid crystal panel adjustment data in the nonvolatile memory 27, a setting information writing device is connected to the liquid crystal driver 20, and a writing voltage and an erasing voltage are connected. Is supplied to the liquid crystal driver 20.

Referring to FIG. 3, in the comparator 44 included in the window comparator 51, the voltage V _W · R6 / (R5 + R6) obtained by dividing the write voltage V _W by the resistors R5 and R6 is larger than the reference voltage V _W1. Sometimes a high level signal is output, and when the voltage _VW · R6 / (R5 + R6) is smaller than the reference voltage _VW1 , a low level signal is output. The comparator 45, the voltage _{V W · R6 / (R5 +} R6) outputs a high level signal is smaller than the reference voltage _(V W1 ₊ V _W2), the voltage _{V W · R6 / (R5 +} R6) the reference voltage _{(V W1} When larger than + V _W2 ), a low level signal is output.

Accordingly, the write voltage V _W inputted from the outside is compared with a lower limit and the upper limit of the set range. Based on the comparison results of the comparators 44 and 45, the NAND circuit 46 outputs a low-level signal when the voltage V _W · R6 / (R5 + R6) is within the set range, and the voltage V _W · R6 / (R5 + R6). ) Is outside the set range, a high level signal is output.

The comparator 47 included in the window comparator 52 of the voltage comparison circuit 50 is configured such that when the voltage V _E · R8 / (R7 + R8) obtained by dividing the erase voltage V _E by the resistors R7 and R8 is greater than the reference voltage V _E1. A high level signal is output, and a low level signal is output when the voltage V _E · R8 / (R7 + R8) is smaller than the reference voltage V _E1 . The comparator 48, the voltage _{V E · R8 / (R7 +} R8) outputs a high level signal when the reference voltage _(V E1 _{+ V E2)} is smaller, the voltage _{V E · R8 / (R7 +} R8) is a reference voltage (V When it is larger than _E1 + V _E2 ), a low level signal is output.

Thus, the erase voltage V _E to be inputted from the outside is compared with a lower limit and the upper limit of the set range. Based on the comparison results of the comparators 47 and 48, the NAND circuit 49 outputs a low-level signal when the voltage V _E · R8 / (R7 + R8) is within the set range, and the voltage V _E · R8 / (R7 + R8). ) Is outside the set range, a high level signal is output.

The determination circuit 53 is configured by, for example, an OR circuit, and outputs a low-level determination signal S2 when both the output signal of the NAND circuit 46 and the output signal of the NAND circuit 49 are at a low level. When one of the output signal and the output signal of the NAND circuit 49 is at a high level, a high level determination signal S2 is output. Accordingly, the determination signal S2 if the low level, it can be seen that the write voltage V _W and the erase voltage V _E is within the set range. Further, the determination circuit 53 stores the determination signal S2 in a status register in the logic circuit 22.

  The setting information writing device receives the determination signal S2 stored in the status register in the logic circuit 22 via the MPU interface 21, and the write voltage and the erase voltage are within the setting range based on the determination signal S2. Displays whether or not it exists. Thereby, the operator can write or erase data in the nonvolatile memory 27 after confirming that the write voltage and the erase voltage are within the set range. The apparatus for writing setting information outputs setting information and a write command to the logic circuit 22 via the MPU interface 21 according to the operation of the operator, and the logic circuit 22 writes the setting information to the nonvolatile memory 27.

  Alternatively, when the determination signal S2 indicating that the write voltage and the erase voltage are within the setting range is stored in the status register, the logic circuit 22 permits the data write and erase to the nonvolatile memory 27. May be. As a result, a write voltage or erase voltage outside the set range is not applied to the nonvolatile memory 27.

1 is a block diagram showing a configuration of a semiconductor integrated circuit and the like according to a first embodiment of the present invention. The block diagram which shows the structure of the voltage comparison circuit in the 1st Embodiment of this invention. The block diagram which shows the structure of the voltage comparison circuit in the 2nd Embodiment of this invention.

Explanation of symbols

  10 MPU, 20 liquid crystal driver, 21 MPU interface, 22 logic circuit, 23 display memory, 24 segment driver, 25 common driver, 26 power supply circuit, 27 nonvolatile memory, 28, 50 voltage comparison circuit, 30 liquid crystal panel, 41, 42 , 44, 45, 47, 48 Comparator, 43, 53 Judgment circuit, 46, 49 NAND circuit, 51, 52 Window comparator, R1-R8 resistance

Claims (6)

A nonvolatile memory capable of electrically writing and erasing data;
It is determined whether a write voltage and an erase voltage input from the outside for application to the nonvolatile memory are within a first setting range and a second setting range, respectively, and the writing voltage is within the first setting range. A voltage comparison circuit that generates a determination signal having a predetermined level when the erase voltage is within the second set range, and
A logic circuit that holds a determination signal generated by the voltage comparison circuit and controls data writing and erasing in the nonvolatile memory;
A semiconductor integrated circuit comprising: The voltage comparison circuit is
The write voltage inputted from the outside is divided, and the divided voltage is compared with the first reference voltage. When the divided voltage is lower than the first reference voltage, the write voltage is in the first setting range. A first comparator for generating an output signal representing being within,
The erase voltage input from the outside is divided, and the divided voltage is compared with the second reference voltage. When the divided voltage is lower than the second reference voltage, the erase voltage is in the second setting range. A second comparator for generating an output signal representing being within,
A determination circuit that generates a determination signal based on output signals of the first and second comparators;
The semiconductor integrated circuit according to claim 1, comprising: The voltage comparison circuit is
The write voltage inputted from the outside is divided, the divided voltage is compared with the first reference voltage and the second reference voltage, and the divided voltage becomes the first reference voltage and the second reference voltage. A first window comparator that generates an output signal indicating that the write voltage is within a first set range when having a level between
The erase voltage input from the outside is divided, the divided voltage is compared with the third reference voltage and the fourth reference voltage, and the divided voltage is compared with the third reference voltage and the fourth reference voltage. A second window comparator for generating an output signal indicating that the erase voltage is within a second set range when having a level between
A determination circuit that generates a determination signal based on output signals of the first and second window comparators;
The semiconductor integrated circuit according to claim 1, comprising:   4. The semiconductor according to claim 1, wherein the logic circuit includes a register that holds a determination signal generated by the voltage comparison circuit, and outputs the determination signal held in the register to the outside. Integrated circuit.   The logic circuit includes a register that holds a determination signal generated by the voltage comparison circuit, and the determination signal held in the register has a write voltage within a first setting range and an erase voltage of a second 4. The semiconductor integrated circuit according to claim 1, wherein writing and erasing of data with respect to the non-volatile memory are permitted when it indicates that it is within a set range. 5. An MPU interface for receiving image data and setting information from outside;
A display memory for storing image data;
A segment driver that generates a segment signal for displaying an image on a display panel based on image data stored in the display memory;
A common driver that generates a timing signal for controlling image display on the display panel;
Further comprising
The semiconductor integrated circuit according to claim 1, wherein the logic circuit stores image data and setting information received by the MPU interface in the display memory and the nonvolatile memory, respectively.

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