JP2007115976A - Solid-state imaging element and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging element having a high condensing efficiency to a photoelectric converter, and also a method for manufacturing the imaging element. <P>SOLUTION: A photoelectric conversion element 1 and pixel region having switch elements and a plurality of pixels arranged therein for reading out a signal from the photoelectric conversion element 1 are formed on a Si substrate 2. A plurality of wiring layers 3, 4, and 6 are formed on the pixel region, and an interlayer insulating film is provided at the wiring layers 3, 4, and 6 to thereby isolate therebetween. At least one of the wiring layers provided on the pixel region is contacted at its upper side with the interlayer insulating film through an antireflective layer, and is contacted at its lower side directly with the interlayer insulating film. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a structure and a manufacturing method of a solid-state imaging device formed on a semiconductor substrate.

  Semiconductor devices such as CCD (Charge Coupled Device) and CMOS (Complementary Metal Oxide Semiconductor) sensors are used as imaging devices for video cameras and digital still cameras. These elements make light from a lens incident on a plurality of photoelectric conversion elements (for example, photodiodes) arranged one-dimensionally or two-dimensionally, and transfer a charge signal photoelectrically converted by the photoelectric conversion elements. The basic function is to amplify and read.

  In recent years, in these semiconductor elements, the total number of photoelectric conversion units (pixels) has increased to several million, or more than 10 million, so that the size of each pixel itself has changed from 10 μm to several μm on a side. And the demand for reduction is remarkable.

  Under such circumstances, in order to obtain an imaging signal having a small pixel size and a high S / N ratio, it is important to collect as much light as possible and increase the sensitivity of photoelectric conversion.

  In order to improve the sensitivity of photoelectric conversion, it is important to first increase the light intake, that is, the opening area for the photoelectric conversion element as much as possible. Therefore, it is necessary to reduce the area occupied by the metal wiring layer in order to prevent the metal wiring layer formed above the photoelectric conversion element from hindering the incidence of light on the photoelectric conversion element. In order to reduce the area occupied by the metal wiring layer, it is necessary to increase the degree of integration of the metal wiring constituting the metal wiring layer. In these elements having a pixel size of 10 μm or less, the width of each wiring is miniaturized to at least 1 μm or less, usually 0.5 μm or less, thereby securing an opening area for the photoelectric conversion element.

  In forming a metal wiring layer composed of the fine metal wiring as described above, it is necessary to pay attention to ensuring pattern fidelity in the exposure process and ensuring wiring reliability. There are also restrictions on the plug formation process for connecting the upper and lower wirings. Therefore, it has been common to employ a laminated structure as described below.

  FIG. 4 is an explanatory view showing the structure of a conventional metal wiring layer, and shows an example in which the number of stacked layers is two upper and lower layers.

  The upper and lower metal wiring layers 100 and 200 shown in the figure basically have the same laminated structure, and barrier metals 101 and 201 are disposed in the lower layers. Most generally, reliability is secured by using a sputtered laminated film of Ti (titanium) and TiN (titanium nitride) (hereinafter also referred to as “TiN / Ti film”) as the barrier metal. The metal wirings 102 and 202 are made of a sputtered film containing 1.0% or less of Cu (copper) in Al (aluminum) (hereinafter also referred to as “Al-Cu film”). In order to faithfully form the fine metal wirings 102 and 202 by the photolithography technique, antireflection films (hereinafter also referred to as “ARL films”) 103 and 203 are formed on the uppermost layers of the wiring layers 100 and 200, respectively. Are stacked. The ARL films 103 and 203 have a role of preventing reflection at the time of resist exposure, and most commonly, a laminated film and a TiN / Ti film similar to the barrier metals 101 and 201 are used.

  The upper and lower metal wirings 102 and 202 are electrically connected by a W (molybdenum) plug 300. The method for forming the W plug 300 is as follows.

  First, after opening a hole, a barrier metal (TiN / Ti film or the like) 301 is formed on the inner surface of the hole. Next, a W film is deposited, but since a filling property to holes is required, a CVD method is used in which the W film is deposited by reducing WF6 gas with H2 gas or the like. The barrier metal 301 formed on the inner surface of the hole prevents corrosion of the base due to HF (hydrogen fluoride) generated at this time. Next, the W plug 300 embedded in the hole is completed by removing the W film deposited on the flat surface other than the inner surface of the hole by etch back.

  Next, an Al—Cu film constituting the upper metal wiring 202 is formed, and an ARL film 203 similar to the ARL film 103 is formed thereon. Thereafter, the metal wiring 202 is formed by photolithography and etching.

  As described above, the metal wiring layer including the fine metal wiring is formed through a number of processes. Further, the following method has been proposed as a method for increasing the light collection efficiency and increasing the sensitivity.

An example of the CCD described in Patent Document 1 is shown in FIG. In the example shown in FIG. 5, the insulating layer 402 is recessed immediately above the photodiode 401 provided in the Si substrate 400. The reflective metal film 403 formed on the insulating layer 402 extends to the inner surface of the recess 404. As a result, light 405 incident from above the element is reflected by the reflective metal film 403 and guided to the photodiode. In other words, FIG. 5 discloses an element having a light guide structure for increasing the light collection efficiency. As shown in FIG. 5, a light shielding layer 406 is disposed under the reflective metal film 403, and an electrode 407 for charge transfer is disposed therebelow.
JP 2002-94038 A

  As described above, in the solid-state imaging device, the performance of the device is improved by miniaturizing the wiring structure and preventing the incident light amount to the photoelectric conversion device as much as possible. However, in order to reduce the area occupied by the wiring structure while miniaturizing the element dimensions, it is essential to further increase the number of wiring layers. However, when the number of wiring layers increases, even if the opening area for the photoelectric conversion element can be secured, vignetting of incident light occurs, and the effective light amount eventually decreases. Specifically, as shown in FIG. 6, light incident from an oblique direction is blocked by the end of the wiring structure 500 and cannot reach the photoelectric conversion element 502 formed on the surface of the substrate 501.

  Further, in the conventional example shown in FIG. 5, the metal film surface formed on the side surface of the concave portion of the insulating layer 402 is used as the reflecting surface. However, a metal film formed by depositing a metal material generally has fine roughness generated on the surface as crystal grains grow. In particular, as in the conventional example shown in FIG. 5, when metal atoms from above are deposited on the side surfaces, surface roughness is promoted by the shadowing effect. Therefore, the reflectivity of light by the metal reflection film 403 formed on the side surface of the concave portion of the insulating layer 402 is low, and the improvement in light collection efficiency cannot be obtained as expected.

  In the conventional example shown in FIG. 5, a light shielding film 406 is separately provided in addition to the reflective metal film 403. In order to advance the miniaturization of element dimensions, it is advantageous to make the wiring multilayer. However, when the shielding film 406 and the reflective metal film 403 are further stacked on the multi-layered wiring, stacking in the height direction increases, and the above-described increase in light vignetting is caused.

  One of the solid-state imaging devices of the present invention is a pixel area in which a plurality of pixels including a photoelectric conversion element and a switch element for reading a signal from the photoelectric conversion element are arranged on a semiconductor substrate, and the pixel area A solid-state imaging device having a plurality of wiring layers disposed thereon and an interlayer insulating film for insulating between the wiring layers, wherein at least one wiring layer disposed on the pixel region includes: The upper part is in contact with the interlayer insulating film through an antireflection film, and the lower part is in direct contact with the interlayer insulating film.

  Another one of the solid-state imaging devices of the present invention is a solid-state imaging device in which a plurality of photoelectric conversion elements and a plurality of wiring layers are formed on a semiconductor substrate, wherein at least one wiring layer is the photoelectric conversion Formed on a sloped or curved surface of an insulating layer surrounding the element, and the sloped or curved surface of the insulating layer is closer to the photoelectric conversion element than a side having a higher height relative to the semiconductor substrate. It is characterized by being.

  One of the solid-state imaging device manufacturing methods of the present invention is a solid-state imaging device manufacturing method in which a plurality of photoelectric conversion elements and a wiring structure divided into a plurality of layers are formed on a semiconductor substrate. In the layer forming step, the W film formed on the insulating layer is CMPed to remove the W film and the barrier metal film formed on the flat surface of the insulating layer, thereby forming a W plug. And a step of forming a wiring by depositing a metal material immediately above the insulating layer after forming the W plug.

  According to another aspect of the present invention, there is provided a solid-state imaging device manufacturing method in which a plurality of photoelectric conversion elements and a wiring structure divided into a plurality of layers are formed on a semiconductor substrate. Before forming the wiring layer, etching the underlying insulating layer to form a slope or curved surface, depositing a wiring layer material on the slope or curved surface of the formed insulating layer, It is characterized by including.

  According to the present invention, even if the size of each photoelectric conversion element is fine, a solid-state imaging element having high light collection efficiency and high sensitivity that contributes to photoelectric conversion can be realized at low cost.

(First embodiment)
FIG. 1 shows an example of an embodiment of a solid-state imaging device of the present invention. The solid-state image sensor in this example is manufactured as follows.

  An oxide film such as BPSG (Boron Phosphorus Silicon Glass) is formed on the semiconductor substrate 2 on which the photoelectric conversion element 1 is formed by a CVD (Chemical Vapor Deposition) method. In addition, the photoelectric conversion element 1 in this example is a photodiode, and the semiconductor substrate 2 is a Si substrate.

  Next, after planarizing the surface of the formed oxide film by CMP, a contact hole (not shown) for electrical connection with the active region of the device and Poly-Si such as a gate electrode is opened. Thereafter, TiN / Ti is deposited by sputtering or other methods to form a barrier metal of about 100 nm. Next, a W film is formed on the entire surface of the barrier metal by a CVD method. Thereafter, the W film formed on the plane of the oxide film is removed by CMP instead of etch back. At this time, since W and TiN / Ti cannot be selected in the polishing, the barrier metal is scraped (overpolished). As a result, no barrier metal (metal film) remains on the plane of the oxide film, and W and TiN / Ti remain only on the inner surface of the contact hole, completing a W plug for contact connection (not shown).

  Next, an Al—Cu film of approximately 200 to 400 nm and a TiN / Ti film (ARL film) of 30 to 60 nm are continuously formed by sputtering or the like, and processed into a wiring shape by photolithography and etching. Thus, the formation of the first metal wiring layer 3 shown in FIG. 1 is completed.

  Next, a via plug 5 for connecting the first metal wiring layer 3 and the second metal wiring layer 4 is formed. Again, the W film is flattened by CMP to form a W plug so that no barrier metal remains on the oxide film plane. Thereafter, similarly to the first metal wiring layer 3, an Al—Cu film and a TiN / Ti film (ARL film) are continuously deposited and processed by sputtering or the like to form a second metal wiring layer 4. .

  By forming the metal wiring layer as described above, the lower surface of each wiring layer becomes Al-Cu, and the lower surface is directly deposited on the oxide film (interlayer insulating film 8) planarized by CMP. Therefore, a wiring structure having a lower surface with high light reflectance can be obtained.

  The third metal wiring layer 6 can be formed in the same manner, and the reflectance of the lower surface can be increased. The third metal wiring layer 6 also serves as a light shielding layer and is formed so as to cover other than the opening of the photodiode 1.

  After the third metal wiring layer 6 is formed, a protective film 7 is formed by a CVD method, and a planarization process such as CMP is performed as necessary. Further, although not shown in the drawing, the solid-state imaging device of this example is completed through a process of forming a configuration necessary for realizing an imaging function such as a color filter and a microlens.

  According to this structure, the light reflected at the interface between the oxide film and the Si substrate 2 in the incident light is reflected again by the lower surfaces of the wiring layers 3 to 6, and a part thereof is taken into the photodiode 1. It can contribute to photoelectric conversion. As a result, it has been confirmed that the sensitivity of the solid-state imaging device of this example is increased by about 7% to 10% compared to the conventional case. In addition, since there is no layer corresponding to the barrier metal formed in the lower layer of the conventional wiring, suppression of the height of the element is achieved at the same time.

  In this example, the W film was removed by CMP, but the metal film on the oxide film can also be removed by bringing the etching rate of W and the barrier metal closer by the conventional etch-back method using dry etching. It is. In any case, there is almost no cost increase due to the sensitivity increase by this structure.

Although not described and illustrated, the photodiode 1 constitutes a pixel together with a switch element for reading a signal from the photodiode 1. Further, a plurality of the pixels are arranged on the Si substrate to form a pixel region, and the plurality of metal wiring layers are formed above the pixel region. The number of metal wiring layers stacked is not limited to three. These points are the same in other embodiments.
(Second embodiment)
Another example of the embodiment of the solid-state imaging device of the present invention will be described with reference to FIGS. 2 shows a cross-sectional structure of the completed solid-state imaging device of this example, and FIG. 3 shows a cross-sectional composition in the middle of manufacture.

  The solid-state image sensor of this example is manufactured as follows. That is, the first metal wiring layer 10 and the second metal wiring layer 11 shown in FIG. Accordingly, barrier metals 12 and 13 are disposed on the lowermost layer of these metal wiring layers 10 and 11, respectively.

After the formation of the metal wiring layers 10 and 11, as shown in FIG. 3, an insulating layer (interlayer insulating film 14) such as SiO ₂ is formed on the metal wiring layer 11 by the CVD method, and planarized by CMP. I do.

  Next, a W plug (not shown) for connecting the second metal wiring layer 11 and the third metal wiring layer 15 (FIG. 2) is formed. In forming the W plug, as described in the first embodiment, after depositing the W film, the planar W film and the W underlying barrier metal are simultaneously removed by CMP.

  Next, a resist 16 is applied and exposed on the flat interlayer insulating film 14 to provide slit-like openings 17. The opening 17 is provided so as to surround a region immediately above the formation region of the photodiode 1. In this step, by applying an appropriate post-bake, the end portion of the resist 16 generates a thermal sag and becomes a shape having a substantially arc-shaped cross section. Thereafter, the entire surface is etched back by dry etching with the etching rate of the resist 16 and the interlayer insulating film 14 adjusted, and the resist shape is transferred to the shape of the interlayer insulating film 14 so that the interlayer insulation as shown in FIG. An upper surface shape of the film 14 is obtained.

  Thereafter, an Al—Cu film and an ARL film are continuously deposited and processed by sputtering or the like to form the third metal wiring layer 15. The metal wiring layer 15 has a thickness of 200 nm to 400 nm because it also serves as a wiring and a light shielding layer. However, when only the function as a light shielding layer is given, it can be formed thinner. Further, since the light shielding layer has a function, it is formed so as to cover the lower wiring layer, in this example, the metal wiring layers 10 and 11.

  By forming the metal wiring layer 15 and the underlying interlayer insulating film 14 in this way, the lower surface of the metal wiring layer 15 can be made a reflective surface having high reflectivity and curvature. As a result, the incident light can be effectively guided to the photoelectric conversion unit as compared with the first embodiment. Moreover, since the lower surface of the wiring structure is used as the reflecting surface as in the first embodiment, high reflectance can be stably achieved regardless of the thickness of the wiring layer and the cross-sectional shape. Specifically, the sensitivity can be improved by about 10% compared to the conventional structure.

  On the other hand, unlike the first embodiment, in this example, the photodiode 1 is formed so as to be surrounded by the inclined or curved lower surface of the metal wiring layer 15. As a result, stray light due to scattering from adjacent elements can be suppressed, and an image sensor with excellent S / N can be obtained.

  Further, the wiring structure from which the barrier metal is removed is employed only in the uppermost metal wiring layer 15 which also serves as a light shielding layer, and barrier metals 12 and 13 are provided under the other metal wiring layers 10 and 11. It has a structure to leave. For this reason, resistance to electromigration can be increased, reliability can be further increased, and design freedom is increased.

  If the current density and the load factor (duty) in the wiring of the second metal wiring layer 11 are small in terms of element design and the reliability can be secured, the barrier metal 13 under the metal wiring layer 11 is removed. It can also be used as a reflective layer. That is, the features shown in the first and second embodiments can be appropriately combined. In this case, the metal wiring layer 11 may be formed on an insulating layer that is inclined or curved so as to surround each photodiode 1.

  In this embodiment, the lower surface of the metal wiring layer 15 is formed to have a substantially arc-shaped cross section. However, any shape other than the arc shape may be used as long as it surrounds the photodiode 1 and can return the reflected light from the Si interface to the photodiode 1. For example, if it is formed with an inclined surface (tapered surface) where the photodiode 1 is desired, the same light collecting effect as described above can be obtained.

  So far, the embodiments of the present invention have been described taking the case where the photoelectric conversion element is a photodiode as an example. However, it is clear from the above description that the type of the photoelectric conversion element is not an essential matter of the present invention, and a photoelectric conversion element other than the photodiode can be used.

It is typical sectional drawing which shows an example of embodiment of the solid-state image sensor of this invention. It is typical sectional drawing which shows the other example of embodiment of the solid-state image sensor of this invention. FIG. 5 is a schematic cross-sectional view showing a part of the manufacturing process for the solid-state imaging element shown in FIG. 2. It is typical sectional drawing which shows the wiring structure in the conventional solid-state image sensor. FIG. 6 is a schematic cross-sectional view showing a wiring structure of a solid-state imaging device disclosed in Patent Document 1. It is typical sectional drawing which shows one of the problems of the conventional wiring structure.

Explanation of symbols

1 Photodiode 2 Si substrate 3, 4, 6, 10, 11 Metal wiring layer 5 W plug 8, 14 Interlayer insulating film 12, 13 Barrier metal

Claims (8)

On a semiconductor substrate, a pixel area in which a plurality of pixels including a photoelectric conversion element and a switch element for reading a signal from the photoelectric conversion element are arranged, a plurality of wiring layers arranged on the pixel area, A solid-state imaging device formed with an interlayer insulating film for insulating between the wiring layers,
At least one wiring layer disposed on the pixel region has an upper portion in contact with the interlayer insulating film through an antireflection film and a lower portion in direct contact with the interlayer insulating film. element.   2. The solid-state imaging device according to claim 1, wherein a barrier metal is not interposed between at least one wiring line and a plug for electrically connecting the wiring layer and another wiring layer.   3. The solid-state imaging device according to claim 1, wherein a surface of the interlayer insulating film in direct contact with the at least one wiring layer is inclined or curved. In a method for manufacturing a solid-state imaging device in which a plurality of photoelectric conversion elements and a wiring structure divided into a plurality of layers are formed on a semiconductor substrate,
In the process of forming at least one wiring layer, the W film formed on the insulating layer is removed by CMP to remove the W film and the barrier metal film formed on the flat surface of the insulating layer. Forming a plug;
And a step of forming a wiring by depositing a metal material immediately above the insulating layer after the W plug is formed. A solid-state imaging device in which a plurality of photoelectric conversion elements and a plurality of wiring layers are formed on a semiconductor substrate,
At least one wiring layer is formed in direct contact with the inclined or curved surface of the insulating layer surrounding the photoelectric conversion element,
The solid-state imaging device, wherein the inclined or curved surface of the insulating layer is closer to the photoelectric conversion device than a side having a higher height relative to the semiconductor substrate.   The end portion of the wiring layer formed in direct contact with the inclined or curved surface of the insulating layer is formed so as to cover the other wiring layer in the planar shape, and is the most of the plurality of wiring layers. The solid-state imaging device according to claim 5, further comprising an end portion close to the photoelectric conversion device.   The solid-state imaging device according to claim 5, wherein the wiring layer formed in direct contact with the inclined or curved surface of the insulating layer is formed in the uppermost layer among the plurality of wiring layers. In a method for manufacturing a solid-state imaging device in which a plurality of photoelectric conversion elements and a wiring structure divided into a plurality of layers are formed on a semiconductor substrate,
Before forming at least one wiring layer, etching the underlying insulating layer to form a slope or curved surface, and depositing a wiring layer material on the slope or curved surface of the formed insulating layer And a method of manufacturing a solid-state imaging device.

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