JP2007115830A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device capable of accurately patterning nickel silicide, and also to provide the semiconductor device. <P>SOLUTION: On a principal surface of a semiconductor substrate 1, there are formed an insulating film, a polysilicon film, and a nickel layer. A nickel silicide layer is formed and an unreacted nickel layer is removed by applying lamp annealing processing, and a hard mask 9 is formed on the nickel silicide layer. By alternately performing anisotropic plasma etching using a gas containing NH<SB>3</SB>and CO and anisotropic plasma etching using Cl<SB>2</SB>gas while employing a hard mask 9 as a mask there are formed a nickel silicide layer 8a becoming a gate electrode and a polysilicon film 5a. Thereafter, source to drain regions are formed, and the nickel silicide layer is formed in the source to drain regions. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a manufacturing method of a semiconductor device to which nickel silicide is applied and a semiconductor device obtained by the manufacturing method.

  Conventionally, a silicide technique has been used in which metal silicide is formed in a self-aligned manner on the surfaces of the gate electrode and source / drain regions of a transistor. By applying this salicide technique, the wiring resistance of the gate electrode made of polycrystalline silicon and the parasitic resistance of the source / drain regions are reduced, thereby suppressing the wiring delay and the conductance deterioration in the transistor.

Recently, with the miniaturization of semiconductor devices, it has been demanded to shorten the gate length and narrow the junction width. For example, Patent Documents 1 to 3 disclose conventional cobalt silicide as a metal silicide. It has been proposed to apply nickel silicide (NiSi) from (CoSi). The application of nickel is also being considered.
JP 2002-319670 A JP 2004-134687 A Special table 2004-511103 gazette

  However, the conventional semiconductor device has the following problems. Both cobalt silicide and nickel silicide have a difficult etching property. Therefore, the gate electrode is not patterned after the formation of cobalt silicide or nickel silicide, but after the gate electrode of cobalt or nickel is patterned, the silicide of the gate electrode together with the source / drain regions is performed by the salicide process.

  An object of the present invention is to provide a method for manufacturing a semiconductor device capable of accurately patterning nickel silicide, and another object is to provide a semiconductor device obtained by such a manufacturing method. .

A manufacturing method of a semiconductor device according to the present invention includes the following steps. A predetermined conductive layer including either a nickel silicide layer or a nickel layer is formed on the main surface of the semiconductor substrate. A mask member is formed on the conductive layer. The conductive layer is patterned into a predetermined shape by performing predetermined etching on the conductive layer using the mask member as a mask. The predetermined etching in the patterning step of patterning the conductive layer includes first plasma etching using a gas containing ammonia (NH ₃ ) and carbon monoxide (CO).

  The semiconductor device according to the present invention includes a gate electrode portion including a first nickel silicide layer and a pair of second nickel silicide layers. The gate electrode portion is formed on the main surface of the semiconductor substrate. The pair of second nickel silicide layers includes a semiconductor substrate region located on one side of the gate electrode portion with the gate electrode portion interposed therebetween, and a semiconductor substrate located on the other side of the gate electrode portion. It is formed in the area. The first nickel silicide layer and the second nickel silicide layer differ in at least one of film thickness and film quality.

According to the method for manufacturing a semiconductor device of the present invention, a conductive layer including a nickel silicide layer is etched into a predetermined shape by first plasma etching using a gas including ammonia (NH ₃ ) and carbon monoxide (CO). Can be patterned.

  In the semiconductor device according to the present invention having the gate electrode portion formed by etching the nickel silicide layer, the film thicknesses of the first nickel silicide layer and the second nickel silicide layer are changed, or the process conditions are changed. By changing the film quality, the resistance of the gate electrode can be reduced and junction leakage can be reduced.

Embodiment 1
In the first embodiment of the present invention, a method for manufacturing a semiconductor device targeting nickel silicide as a salicide process will be described. First, as shown in FIG. 1, an insulating film 3 to be a gate insulating film is formed on the main surface of the semiconductor substrate 1 by performing, for example, a thermal oxidation process. A polysilicon film 5 is formed on the insulating film 3 by, for example, a CVD (Chemical Vapor Deposition) method.

Next, as shown in FIG. 2, a nickel (Ni) layer 7 having a thickness of 20 to 30 nm is formed on the polysilicon film 5 by, for example, sputtering. Next, lamp annealing is performed at a temperature of about 320 ° C. for about 30 seconds in a nitrogen (N ₂ ) atmosphere to react silicon in the polysilicon film 5 with nickel in the nickel layer 7. As shown in FIG. 3, a nickel silicide (NiSi) layer 8 having a thickness of about 70 nm is formed. Thereafter, lamp annealing is performed under a nitrogen (N ₂ ) atmosphere at a temperature of about 550 ° C. for a time of about 30 seconds. Next, by immersing the semiconductor substrate 1 in a mixed solution of phosphoric acid, nitric acid, acetic acid and water, the unreacted nickel layer 7 is removed and the surface of the nickel silicide layer 8 is exposed as shown in FIG. .

  Next, a silicon oxide film or silicon nitride film (not shown) serving as a hard mask is formed on the nickel silicide layer 8. By subjecting the silicon oxide film or silicon nitride film to predetermined photolithography and processing, a hard mask 9 for patterning the gate electrode is formed as shown in FIG.

Next, anisotropic plasma etching using a gas containing ammonia (NH ₃ ) and carbon monoxide (CO) is performed using the hard mask 9 as a mask. For example, the flow rate of ammonia (NH ₃ ) is about 75 cm ³ / min, the flow rate of carbon monoxide (CO) is about 25 cm ³ / min, the pressure is about 0.6 Pa, and the source / bias = 1500 W / 300 W, By performing anisotropic plasma etching on the nickel silicide layer 8, as shown in FIG. 6, the nickel silicide layer 8 of the other part is removed while leaving the nickel silicide layer 8a that becomes a part of the gate electrode.

Subsequently, by performing anisotropic plasma etching using chlorine (Cl ₂ ) gas with the hard mask 9 as a mask, the polysilicon film 5 is used to form polysilicon that becomes a part of the gate electrode as shown in FIG. The remaining part of the polysilicon film 5 is removed leaving the film 5a. Further, the insulating film 3 is subjected to anisotropic etching to form a gate insulating film 3a.

  Next, as shown in FIG. 8, by introducing impurity ions of a predetermined conductivity type into the surface of the semiconductor substrate 1 using the hard mask 9 or the like as a mask, the low-concentration impurity regions 11a that become part of the source / drain regions are formed. 11b are formed. Next, as shown in FIG. 9, an insulating film 13 having a film thickness of about 5 to 10 nm is formed on the semiconductor substrate 1 so as to cover the hard mask 9 and the like by, for example, the CVD method. Next, as shown in FIG. 10, an insulating film 15 is further formed on the insulating film 13 by, eg, CVD.

  Next, as shown in FIG. 11, by performing anisotropic etching on the insulating films 15 and 13, sidewall spacers 13a and sidewall insulating films 15a are formed on both side surfaces of the polysilicon film 5a and the like. Is done. Thus, the gate electrode portion 10 including the polysilicon film 5a, the nickel silicide layer 8a, the sidewall insulating film 15a, and the like is formed. In the gate electrode portion 10, the nickel silicide layer 8a and the polysilicon film 5a become the gate electrode body.

  By introducing impurity ions of a predetermined conductivity type into the surface of the semiconductor substrate 1 using the gate electrode portion 10 as a mask, high-concentration impurity regions 17a and 17b that become part of the source / drain regions are formed. The low concentration impurity regions 11a and 11b and the high concentration impurity regions 17a and 17b constitute a pair of source / drain regions 18a and 18b.

Next, as shown in FIG. 12, a nickel layer 19 is formed on semiconductor substrate 1 so as to cover gate electrode portion 10 by, eg, sputtering. Next, under a nitrogen (N ₂ ) atmosphere, a lamp annealing process is performed at a temperature of about 320 ° C. for a time of about 30 seconds to react silicon in the semiconductor substrate 1 with nickel in the nickel layer 19, Nickel silicide (NiSi) layers 20a and 20b are formed on the surfaces of the source / drain regions 18a and 18b, respectively. Thereafter, lamp annealing is performed under a nitrogen (N ₂ ) atmosphere at a temperature of about 550 ° C. for a time of about 30 seconds.

  Next, by immersing the semiconductor substrate 1 in a mixed solution of phosphoric acid, nitric acid, acetic acid and water, as shown in FIG. 13, the unreacted nickel layer 19 is removed and the surfaces of the nickel silicide layers 20a and 20b are removed. Each is exposed. Thus, the main part of the transistor in the semiconductor device is completed.

In the semiconductor device manufacturing method described above, a nickel silicide layer is formed by a salicide process, and an anisotropic gas using a gas containing ammonia (NH ₃ ) and carbon monoxide (CO) is used for the nickel silicide layer. By performing plasma etching, patterning for forming the gate electrode portion is performed.

  In this etching, by using carbon monoxide gas, a carbonyl compound is generated as a reaction product having a relatively high vapor pressure, and is deposited on the exposed processing surface in the nickel silicide layer. The deposited carbonyl compound reduces the etching rate of the nickel silicide layer, and the ammonia compound is used to remove the carbonyl compound appropriately. As a result, the nickel silicide layer can be patterned accurately and efficiently without decreasing the etching rate.

  Thus, the nickel silicide layer can be patterned by plasma etching, which can be conventionally processed only by a physical sputtering method.

In the above-described patterning of the nickel silicide layer, the anisotropic plasma etching using a gas containing ammonia (NH ₃ ) and carbon monoxide (CO) has been described as an example. However, the nickel silicide layer includes the nickel silicide layer. In order to eliminate silicon residues, it is desirable to use chlorine (Cl ₂ ) gas, which is generally used for etching polysilicon.

That is, as shown in FIG. 14, plasma etching (CO / NH ₃ step) using a gas containing ammonia (NH ₃ ) and carbon monoxide (CO) and plasma using chlorine (Cl ₂ ) gas. By alternately performing etching (Cl ₂ system step) (digital etching), the silicon residue can be efficiently removed, and the nickel silicide layer can be patterned with higher accuracy.

As an example of the conditions, in the CO / NH ₃ system step, for example, the flow rate of ammonia (NH ₃ ) is about 75 cm ³ / min, the flow rate of carbon monoxide (CO) is about 25 cm ³ / min, and the pressure is about 0.003. The nickel silicide layer 8 is subjected to anisotropic plasma etching under 6 Pa and source / bias = 1500 W / 300 W.

On the other hand, in the Cl ₂ system step, for example, the flow rate of chlorine (Cl ₂ ) is about 100 cm ³ / min, the pressure is 0.4 Pa, Pμ (microwave power) = 400 W, Prf (RF power) = 60 W, The nickel silicide layer 8 is subjected to ECR (Electron Cyclotron Resonance) etching.

Further, by performing plasma etching using a gas obtained by adding chlorine (Cl ₂ ) to ammonia (NH ₃ ) and carbon monoxide (CO), the silicon residue contained in the nickel silicide layer can be reduced. .

As an example of the conditions, for example, the flow rate of ammonia (NH ₃ ) is about 75 cm ³ / min, the flow rate of carbon monoxide (CO) is about 25 cm ³ / min, and the flow rate of chlorine (Cl ₂ ) By adding a small amount so as to be about several percent and performing anisotropic plasma etching on the nickel silicide layer 8 under a pressure of about 0.6 Pa and a source / bias of 1500 W / 300 W, silicon residues are removed. The nickel silicide layer can be efficiently removed and patterned with higher accuracy.

As described above, in this method of manufacturing a semiconductor device, the nickel silicide layer can be accurately patterned by anisotropic plasma etching using a gas containing ammonia (NH ₃ ) and carbon monoxide (CO). Furthermore, by alternately performing plasma etching using these gases and plasma etching using chlorine gas, it is possible to suppress silicon residues and perform patterning with higher accuracy.

  In the semiconductor device manufacturing method described above, the nickel silicide layer 8a formed in the gate electrode portion 10 and the nickel silicide layers 20a and 20b formed in the source / drain regions 18a and 18b are not in the same process, but separately. Formed in the process.

  In particular, as shown in FIG. 12, in the step of forming the nickel silicide layers 20a and 20b, the nickel silicide layer 8a formed on the gate electrode portion 10 is covered with the hard mask 9, the sidewall insulating film 15a, and the like. Silicidation is carried out. As a result, compared to the case where the nickel silicide layer formed in the gate electrode portion and the nickel silicide layer formed in the source / drain regions are formed in the same process, the nickel silicide layer grows also on the sidewall insulating film. Thus, it is possible to prevent the nickel silicide layer 8a formed in the gate electrode portion 10 and the nickel silicide layers 20a and 20b formed in the source / drain regions 18a and 18b from being electrically short-circuited.

  Further, in the semiconductor device manufacturing method described above, the side spacer 13a and the sidewall insulating film 15a are formed on the side surfaces of the hard mask 9, the nickel silicide layer 8a, and the polysilicon film 5a of the gate electrode portion 10. Thereby, when forming a contact hole, it can suppress that the part of the area | region of the semiconductor substrate located directly under the side spacer 13a and the side wall insulating film 15a is etched. This will be described.

  When the shared contact hole is formed as the contact hole, as shown in FIG. 15, the contact hole 21a exposing the surfaces of the nickel silicide layer 8a of the gate electrode portion 10 and the nickel silicide layer 20b of the source / drain region 18b is formed as an interlayer. It is formed on the insulating film 21.

  At this time, since the side spacers 13a and the sidewall insulating films 15a are formed from the upper end of the hard mask 9 to the surface of the semiconductor substrate 1, the width (W) direction of the side spacers 13a and the sidewall insulating films 15a accompanying the etching is increased. Can be suppressed. As a result, the exposed surface of the semiconductor substrate 1 can be prevented from being etched and etched.

On the other hand, in the case of the semiconductor device according to the comparative example, as shown in FIG. 16, the sidewall insulating film 115a is formed from the upper end of the polysilicon film 105a of the gate electrode portion 110 to the surface of the semiconductor substrate. In addition, along with the etching when forming the shared contact hole in the interlayer insulating film 121,
In some cases, the width (W) direction of the sidewall insulating film 115a recedes, and the exposed surface of the semiconductor substrate 101 is etched and etched.

  Further, when a self-aligned contact hole is formed as a contact hole, as shown in FIG. 17, the surface of the nickel silicide layer 20b located between two gate electrode portions 10 arranged at an interval is exposed. A contact hole is formed in the interlayer insulating film 21 in a self-aligning manner.

  Also in this case, the side spacer 13a and the sidewall insulating film 15a are formed from the upper end of the hard mask 9 to the surface of the semiconductor substrate 1, thereby preventing the surface of the nickel silicide layer 8a from being exposed. Thereby, an electrical short circuit between the exposed nickel silicide layer 20b and the gate electrode portion 10 can be prevented.

  On the other hand, in the case of the semiconductor device according to the comparative example, as shown in FIG. 18, the sidewall insulating film 115a is formed from the upper end of the polysilicon film 105a of the gate electrode portion 110 to the surface of the semiconductor substrate. In addition, the surface of the nickel silicide layer 108a and the polysilicon film 105a is exposed along with the etching when the contact hole is formed in the interlayer insulating film 121. For this reason, the nickel silicide layer 120b and the gate electrode portion 110 are electrically short-circuited, so that the self-aligned contact hole 121b cannot be formed.

  Further, in the semiconductor device manufacturing method described above, the nickel silicide layer 8a formed in the gate electrode portion 10 and the nickel silicide layers 20a and 20b formed in the source / drain regions 18a and 18b are formed in separate steps. Thus, as shown in FIG. 13, the thickness t1 of the nickel silicide layer 8a and the thickness t2 of the nickel silicide layers 20a and 20b can be made different from each other.

  Thereby, for example, the thickness of the nickel silicide layer 8a formed in the gate electrode portion 10 is relatively thick, and the thickness of the nickel silicide layers 20a and 20b formed in the source / drain regions 18a and 18b is relatively increased. By forming the film thinly or by changing the salicide process conditions to change the film quality of the nickel silicide, the resistance of the gate electrode can be reduced and junction leakage can be reduced.

  As the film quality, for example, the composition ratio and density of nickel silicide correspond to this. The composition ratio and density of the nickel silicide layer can be changed by changing the thickness of the nickel layer and performing heat treatment corresponding to the thickness. In order to contain more nickel, it is preferable to increase the thickness of the nickel layer. More specifically, Ni3Si to NiSi2 are assumed as the composition of nickel silicide. Further, the thickness of the nickel layer is assumed to be about 250 nm.

Embodiment 2
Here, a method for manufacturing a semiconductor device using nickel silicide as a gate electrode material will be described. First, as shown in FIG. 19, an insulating film 3 to be a gate insulating film is formed on the semiconductor substrate 1. A nickel layer is formed on the insulating film 3 by sputtering, for example, and a nickel silicide layer 4 is formed by performing a salicide process on the nickel layer. Next, as shown in FIG. 20, a hard mask 9 for patterning the gate electrode is formed on the nickel silicide layer 4.

Next, the nickel silicide layer 4 is subjected to anisotropic plasma etching using a gas containing ammonia (NH ₃ ) and carbon monoxide (CO) using the hard mask 9 as a mask, as shown in FIG. Thus, the nickel silicide layer 4 which becomes a part of the gate electrode is left, and the other part of the nickel silicide layer 4 is removed.

At this time, as described above, in order to suppress silicon residue, plasma etching (CO / NH ₃ step) using a gas containing ammonia (NH ₃ ) and carbon monoxide (CO), chlorine (Cl ₂ ) Plasma etching using a gas (Cl ₂ system step) may be performed alternately. Further, plasma etching using a gas obtained by adding chlorine (Cl ₂ ) to ammonia (NH ₃ ) and carbon monoxide (CO) may be performed. In this way, the nickel silicide layer 4a and the gate insulating film 3a are formed as the gate electrode body.

  Next, as shown in FIG. 22, by using the hard mask 9 or the like as a mask, impurity ions of a predetermined conductivity type are introduced into the surface of the semiconductor substrate 1 to thereby form a low concentration impurity region 11a that becomes a part of the source / drain region. 11b are formed. Next, as shown in FIG. 23, an insulating film 13 having a film thickness of about 5 to 10 nm is formed on the semiconductor substrate 1 so as to cover the hard mask 9 and the like by, for example, the CVD method. Next, as shown in FIG. 24, an insulating film 15 is further formed on the insulating film 13 by, eg, CVD.

  Next, as shown in FIG. 25, by performing anisotropic etching on the insulating films 15 and 13, sidewall spacers 13a and sidewall insulating films 15a are formed on both side surfaces of the polysilicon film 5a and the like. Is done. Thus, the gate electrode portion 10 including the polysilicon film 5a, the nickel silicide layer 4a, the sidewall insulating film 15a, and the like is formed.

  By introducing impurity ions of a predetermined conductivity type into the surface of the semiconductor substrate 1 using the gate electrode portion 10 as a mask, high-concentration impurity regions 17a and 17b that become part of the source / drain regions are formed. The low concentration impurity regions 11a and 11b and the high concentration impurity regions 17a and 17b constitute a pair of source / drain regions 18a and 18b.

Next, as shown in FIG. 26, a nickel layer 19 is formed on semiconductor substrate 1 so as to cover gate electrode 10 by, for example, sputtering. Next, under a nitrogen (N ₂ ) atmosphere, a lamp annealing process is performed at a temperature of about 320 ° C. for a time of about 30 seconds to react silicon in the semiconductor substrate 1 with nickel in the nickel layer 19, Nickel silicide (NiSi) layers 20a and 20b are formed on the surfaces of the source / drain regions 18a and 18b, respectively. Thereafter, lamp annealing is performed under a nitrogen (N ₂ ) atmosphere at a temperature of about 550 ° C. for a time of about 30 seconds.

  Next, by immersing the semiconductor substrate 1 in a mixed solution of phosphoric acid, nitric acid, acetic acid and water, as shown in FIG. 27, the unreacted nickel layer 19 is removed and the surfaces of the nickel silicide layers 20a and 20b are removed. Each is exposed. Thus, the main part of the transistor in the semiconductor device is completed.

  In the semiconductor device manufacturing method described above, the nickel silicide layer itself is formed on the semiconductor substrate 1 and patterned to form the gate electrode portion 10. This eliminates the need for a metal (nickel) silicidation step in the formation of the gate electrode portion, thereby reducing the number of manufacturing steps.

  In the manufacturing method described above, the case where the nickel silicide layer itself is formed on the semiconductor substrate and the gate electrode portion is formed has been described as an example. However, the material constituting the gate electrode portion is not limited to the nickel silicide layer. A nickel layer may be applied.

Also in this case, the nickel layer can be patterned by performing anisotropic plasma etching using a gas containing ammonia (NH ₃ ) and carbon monoxide (CO).

Further, in the case of the gate electrode portion formed of nickel, the gate electrode portion is formed by lamp annealing when the nickel silicide layer is formed on the surface of the source / drain region as compared with the case where the gate electrode portion includes the nickel silicide layer. This nickel silicide (NiSi) layer does not change to NiSi _2, and it is possible to avoid an increase in resistance.

Embodiment 3
Here, a case where the source / drain regions are formed from the nickel silicide layer itself will be described as an example.

First, by performing anisotropic plasma etching using a gas containing ammonia (NH ₃ ) and carbon monoxide (CO) on the nickel silicide layer in the same manner as the steps shown in FIGS. As shown in FIG. 28, a nickel silicide layer 8a or the like that becomes a part of the gate electrode portion is formed.

  Next, an insulating film (not shown) having a film thickness of about 5 to 10 nm is formed on the semiconductor substrate 1 so as to cover the hard mask 9 and the like by, for example, the CVD method. By performing anisotropic etching on the insulating film, sidewall spacers 13a are formed on both side surfaces of the polysilicon film 5a and the like, as shown in FIG.

Next, as shown in FIG. 30, a nickel layer 19 is formed on semiconductor substrate 1 so as to cover gate electrode portion 10 by, eg, sputtering. Next, under a nitrogen (N ₂ ) atmosphere, a lamp annealing process is performed at a temperature of about 320 ° C. for a time of about 30 seconds to react silicon in the semiconductor substrate 1 with nickel in the nickel layer 19, Nickel silicide (NiSi) layers 20a and 20b are formed on the surface of the semiconductor substrate 1, respectively.

Next, lamp annealing is performed under a nitrogen (N ₂ ) atmosphere at a temperature of about 550 ° C. for a time of about 30 seconds. The nickel silicide layers 20a and 20b formed in this way become source / drain regions 18a and 18b. Thereafter, the unreacted nickel layer 19 is removed by immersing the semiconductor substrate 1 in a mixed solution of phosphoric acid, nitric acid, acetic acid and water.

  Next, an insulating film (not shown) is formed on the semiconductor substrate 1 so as to cover the hard mask 9 and the like, for example, by CVD. Next, by performing anisotropic etching on the insulating film, sidewall insulating films 15a are formed on both side surfaces of the polysilicon film 5a and the like as shown in FIG. Thus, the main part of the transistor in the semiconductor device is completed.

  In the manufacturing method described above, the following effects are obtained in addition to the effects described in the first embodiment. That is, since the ion implantation method is not applied to the formation of the source / drain regions, an annealing process accompanying ion implantation including ion implantation becomes unnecessary. As a result, the number of manufacturing steps can be reduced, and the temperature of the process can be reduced.

  In the manufacturing method described above, the case where the nickel silicide layer and the polysilicon film are formed as the gate electrode portion has been described as an example. However, as described in the second embodiment, the nickel silicide layer itself may be formed. Alternatively, a nickel layer may be formed.

Embodiment 4
In the fourth embodiment, a method for manufacturing a semiconductor device having a gate electrode portion made of metal silicide will be described. First, as shown in FIG. 32, an insulating film 3 made of a high-k film such as HfSiON is formed on the main surface of the semiconductor substrate 1 as a gate insulating film. A polysilicon film 5 is formed on insulating film 3 by, for example, a CVD method.

  Next, as shown in FIG. 33, a nickel (Ni) layer 7 is formed on polysilicon film 5 by, eg, sputtering. A resist pattern 30 for patterning the gate electrode is formed on the nickel layer 7.

Next, using the resist pattern 30 as a mask, as described above, anisotropic plasma etching using a gas containing ammonia (NH ₃ ) and carbon monoxide (CO) is performed on the nickel layer 7. By performing anisotropic etching on the polysilicon film 5, a polysilicon film 5a and a nickel layer 7a for forming a gate electrode are formed as shown in FIG. Thereafter, the resist pattern is removed.

Next, lamp annealing is performed at a temperature of about 320 ° C. under a nitrogen (N ₂ ) atmosphere to react silicon in the polysilicon film 5a with nickel in the nickel layer 7a, as shown in FIG. As described above, the entire polysilicon film 5a and the nickel layer 7a are formed into the nickel silicide layer 8. The gate electrode formed from such a nickel silicide layer 8 is referred to as a FUSI (Full Silicide) electrode. Next, as shown in FIG. 36, the portion of the insulating film 3 located in another region is removed, leaving the portion of the insulating film 3 interposed between the nickel silicide layer 8 and the semiconductor substrate 1.

  Next, as shown in FIG. 37, impurity ions of a predetermined conductivity type are introduced into the surface of the semiconductor substrate 1 using the nickel silicide layer 8 as a mask, thereby forming a low concentration impurity region 11a that becomes a part of the source / drain region. 11b are formed.

  Next, as shown in FIG. 38, an insulating film 13 having a film thickness of about 5 to 10 nm is formed on the semiconductor substrate 1 so as to cover the nickel silicide layer 8 by, eg, CVD. Next, as shown in FIG. 39, an insulating film 15 is further formed on the insulating film 13 by, eg, CVD.

  Next, as shown in FIG. 40, by performing anisotropic etching on the insulating films 15 and 13, sidewall spacers 13a and sidewall insulating films 15a are formed on both side surfaces of the nickel silicide layer 8, respectively. The Thus, the gate electrode portion 10 including the nickel silicide layer 8 and the sidewall insulating film 15a is formed.

  Next, impurity ions of a predetermined conductivity type are introduced into the surface of the semiconductor substrate 1 using the gate electrode portion 10 as a mask, thereby forming high-concentration impurity regions 17a and 17b that become part of the source / drain regions. . The low concentration impurity regions 11a and 11b and the high concentration impurity regions 17a and 17b constitute a pair of source / drain regions 18a and 18b.

Next, as shown in FIG. 41, a nickel layer 19 is formed on semiconductor substrate 1 so as to cover gate electrode portion 10 by, eg, sputtering. Next, under a nitrogen (N ₂ ) atmosphere, a lamp annealing process is performed at a temperature of about 320 ° C. for a time of about 30 seconds to react silicon in the semiconductor substrate 1 with nickel in the nickel layer 19, Nickel silicide (NiSi) layers 20a and 20b are formed on the surfaces of the source / drain regions 18a and 18b, respectively. Thereafter, lamp annealing is performed under a nitrogen (N ₂ ) atmosphere at a temperature of about 550 ° C. for a time of about 30 seconds.

  Next, by immersing the semiconductor substrate 1 in a mixed solution of phosphoric acid, nitric acid, acetic acid and water, as shown in FIG. 42, the unreacted nickel layer 19 is removed and the surfaces of the nickel silicide layers 20a and 20b are removed. Each is exposed. Thus, the main part of the transistor in the semiconductor device is completed.

In the semiconductor device manufacturing method described above, anisotropic plasma etching using a gas containing ammonia (NH ₃ ) and carbon monoxide (CO) is performed on the nickel layer for forming the gate electrode. The patterning of the gate electrode portion can be performed with high accuracy.

  In the semiconductor device manufacturing method described above, the nickel layer 7a and the polysilicon film 5a are described as an example of the nickel layer 7a and the polysilicon film 5a in the step shown in FIG. The entire nickel layer 7a and the polysilicon film 5a need not be formed as a nickel silicide layer by heat treatment when the nickel silicide (NiSi) layers 20a and 20b are formed on the surfaces of the source / drain regions 18a and 18b. May be a nickel silicide layer.

  The embodiment disclosed this time is an example, and the present invention is not limited to this. The present invention is defined by the terms of the claims, rather than the scope described above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

It is sectional drawing which shows 1 process of the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention. FIG. 2 is a cross-sectional view showing a step performed after the step shown in FIG. 1 in the same embodiment. FIG. 3 is a cross-sectional view showing a step performed after the step shown in FIG. 2 in the same embodiment. FIG. 4 is a cross-sectional view showing a step performed after the step shown in FIG. 3 in the same embodiment. FIG. 5 is a cross-sectional view showing a step performed after the step shown in FIG. 4 in the same embodiment. FIG. 6 is a cross-sectional view showing a step performed after the step shown in FIG. 5 in the same embodiment. FIG. 7 is a cross-sectional view showing a step performed after the step shown in FIG. 6 in the same embodiment. FIG. 8 is a cross-sectional view showing a step performed after the step shown in FIG. 7 in the same embodiment. FIG. 9 is a cross-sectional view showing a step performed after the step shown in FIG. 8 in the same embodiment. FIG. 10 is a cross-sectional view showing a step performed after the step shown in FIG. 9 in the same embodiment. FIG. 11 is a cross-sectional view showing a step performed after the step shown in FIG. 10 in the same embodiment. FIG. 12 is a cross-sectional view showing a step performed after the step shown in FIG. 11 in the same embodiment. FIG. 13 is a cross-sectional view showing a step performed after the step shown in FIG. 12 in the same embodiment. In the embodiment, a diagram illustrating a gas containing NH ₃ and CO, and the step of digital etching with a Cl ₂ gas. FIG. 4 is a cross-sectional view of a process for forming a shared contact hole in the same embodiment. FIG. 10 is a cross-sectional view of a process of forming a shared contact hole according to a comparative example in the embodiment. FIG. 10 is a cross-sectional view of a step of forming a self-aligned contact hole in the same embodiment. FIG. 10 is a process cross-sectional view when forming a self-aligned contact hole according to a comparative example in the embodiment. It is sectional drawing which shows 1 process of the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention. FIG. 20 is a cross-sectional view showing a step performed after the step shown in FIG. 19 in the same embodiment. FIG. 21 is a cross-sectional view showing a step performed after the step shown in FIG. 20 in the same embodiment. FIG. 22 is a cross-sectional view showing a step performed after the step shown in FIG. 21 in the same embodiment. FIG. 23 is a cross-sectional view showing a step performed after the step shown in FIG. 22 in the same embodiment. FIG. 24 is a cross-sectional view showing a step performed after the step shown in FIG. 23 in the same embodiment. FIG. 25 is a cross-sectional view showing a step performed after the step shown in FIG. 24 in the same embodiment. FIG. 26 is a cross-sectional view showing a step performed after the step shown in FIG. 25 in the same embodiment. FIG. 27 is a cross-sectional view showing a step performed after the step shown in FIG. 26 in the same embodiment. It is sectional drawing which shows 1 process of the manufacturing method of the semiconductor device which concerns on Embodiment 3 of this invention. FIG. 29 is a cross-sectional view showing a step performed after the step shown in FIG. 28 in the same embodiment. FIG. 30 is a cross-sectional view showing a step performed after the step shown in FIG. 29 in the same embodiment. FIG. 31 is a cross-sectional view showing a step performed after the step shown in FIG. 30 in the same embodiment. It is sectional drawing which shows 1 process of the manufacturing method of the semiconductor device which concerns on Embodiment 4 of this invention. FIG. 33 is a cross-sectional view showing a step performed after the step shown in FIG. 32 in the same embodiment. FIG. 34 is a cross-sectional view showing a step performed after the step shown in FIG. 33 in the same embodiment. FIG. 35 is a cross-sectional view showing a step performed after the step shown in FIG. 34 in the same embodiment. FIG. 36 is a cross-sectional view showing a step performed after the step shown in FIG. 35 in the same embodiment. FIG. 37 is a cross-sectional view showing a step performed after the step shown in FIG. 36 in the same embodiment. FIG. 38 is a cross-sectional view showing a step performed after the step shown in FIG. 37 in the same embodiment. FIG. 39 is a cross-sectional view showing a step performed after the step shown in FIG. 38 in the same embodiment. FIG. 40 is a cross-sectional view showing a step performed after the step shown in FIG. 39 in the same embodiment. FIG. 41 is a cross-sectional view showing a step performed after the step shown in FIG. 40 in the same embodiment. FIG. 42 is a cross-sectional view showing a step performed after the step shown in FIG. 41 in the same embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Semiconductor substrate, 3, 13, 15 insulating film, 3a Gate insulating film, 4, 4Wa, 8, 8a, 20a, 20b Nickel silicide layer, 5, 5a Polysilicon film, 7, 19 Nickel layer, 9 Hard mask, 10 Gate electrode part, 11a, 11b Low concentration impurity region, 13a Side spacer, 15a Side wall insulating film, 17a, 17b High concentration impurity region, 18a, 18b Source / drain region, 21 Interlayer insulating film, 21a Shared contact hole, 21b Self Align contact hole.

Claims (10)

Forming a predetermined conductive layer including either a nickel silicide layer or a nickel layer on a main surface of a semiconductor substrate;
Forming a mask member on the conductive layer;
A patterning step of patterning the conductive layer into a predetermined shape by performing predetermined etching on the conductive layer using the mask member as a mask,
The method of manufacturing a semiconductor device, wherein the predetermined etching in the patterning step includes first plasma etching using a gas containing ammonia (NH ₃ ) and carbon monoxide (CO). The predetermined etching includes a second plasma etching using a gas containing chlorine (Cl ₂ ),
The method of manufacturing a semiconductor device according to claim 1, wherein in the patterning step, the first plasma etching and the second plasma etching are alternately performed. In the predetermined etching, chlorine (Cl ₂ ) is further added,
2. The semiconductor according to claim 1, wherein in the first plasma etching of the patterning step, plasma etching is performed using a gas containing the ammonia (NH ₃ ), the carbon monoxide (CO), and the chlorine (Cl ₂ ). Device manufacturing method. The patterning step includes a step of forming a gate electrode portion extending with a predetermined width on a main surface of the semiconductor substrate,
After forming the gate electrode portion,
Forming a nickel layer on the semiconductor substrate so as to cover the gate electrode portion;
By performing a predetermined heat treatment to react silicon in the semiconductor substrate with nickel in the nickel layer, the semiconductor substrate positioned on one side of the gate electrode portion with the gate electrode portion interposed therebetween 4. The semiconductor according to claim 1, further comprising a step of forming a nickel silicide layer on the portion and the portion of the semiconductor substrate located on the other side of the gate electrode portion. Device manufacturing method.   5. The semiconductor device according to claim 4, further comprising a step of forming a sidewall insulating film from a side surface of the mask member to a surface of the semiconductor substrate with the mask member left before forming the nickel silicide layer. Manufacturing method. After forming the gate electrode portion,
Forming an insulating film on the semiconductor substrate so as to cover the gate electrode portion;
By performing anisotropic etching on the insulating film, the gate electrode portion and the nickel silicide layer are planarly overlapped to form an opening exposing the surface of the gate electrode portion and the nickel silicide. A method for manufacturing a semiconductor device according to claim 5, comprising a step. The patterning step includes a step of forming two gate electrode portions at a predetermined interval,
After forming the two gate electrode portions,
Forming an insulating film on the semiconductor substrate so as to cover the two gate electrode portions;
By performing anisotropic etching on the insulating film, an opening exposing the surface of the nickel silicide portion located in the region of the semiconductor substrate located between one gate electrode and another gate electrode portion is formed. 6. A method of manufacturing a semiconductor device according to claim 5, further comprising a step of forming in a self-aligning manner. A gate electrode portion formed on the main surface of the semiconductor substrate and including a first nickel silicide layer;
Formed in the region of the semiconductor substrate located on one side of the gate electrode portion and the region of the semiconductor substrate located on the other side of the gate electrode portion across the gate electrode portion A pair of second nickel silicide layers formed,
The semiconductor device in which the first nickel silicide layer and the second nickel silicide layer are different in at least one of film thickness and film quality. The gate electrode portion is
A gate electrode body including the first nickel silicide layer;
A mask member formed on the gate electrode body;
The semiconductor device according to claim 8, further comprising a sidewall insulating film formed on both side surfaces of the gate electrode body and the mask member.   10. The semiconductor device according to claim 8, wherein a source / drain region is constituted only by the pair of second nickel silicide layers. 11.

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