JP2007095886A - Electro-optic device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electro-optical device capable of improving transistor characteristics of a TFT element.
A base insulating film 12 on which a semiconductor layer 1a of a TFT 30 is formed has a two-layer structure of a lower base insulating film 12a and an HTO film 12b formed on the lower base insulating film 12a. By forming the HTO film 12b positioned at the boundary with the semiconductor layer 1a with a composition having a refractive index RI = 1.46 to 1.49, the crystallinity of the semiconductor layer 1a is improved and the transistor characteristics of the TFT 30 are improved. improves.
[Selection] Figure 1

Description

  The present invention relates to an electro-optical device provided with a polycrystalline silicon thin film transistor (TFT) element as a switching element.

  In general, an electro-optical device, for example, a liquid crystal device that performs predetermined display using liquid crystal as an electro-optical material has a configuration in which liquid crystal is sandwiched between a pair of substrates. Among them, in an electro-optical device such as an active matrix driving type liquid crystal device by TFT driving or the like, it corresponds to each intersection of a large number of scanning lines (gate lines) and data lines (source lines) arranged vertically and horizontally. The pixel electrode and the switching element are provided on a substrate (active matrix substrate).

  A TFT element is widely used as the switching element. The TFT element is turned on by an ON signal supplied to the gate line, and an image signal supplied through the source line is written to the pixel electrode (current electrode (ITO)). . Thereby, a voltage based on the image signal is applied to the liquid crystal layer between the pixel electrode and the counter electrode to change the arrangement of the liquid crystal molecules. In this way, the transmittance of the pixel is changed, and light passing through the pixel electrode and the liquid crystal layer is changed according to the image signal to perform image display.

In this electro-optical device, it is necessary to improve the characteristics of the TFT element in order to improve the image quality. Therefore, for example, Patent Document 1 discloses a high-temperature oxide film layer (HTO film layer) having a thickness of 50 nm or more as a base insulating film of a TFT element in which a semiconductor layer is formed of a polycrystalline silicon film (polysilicon film). The technology provided is disclosed. According to such a technique, dangling bonds generated at the interface between the TEOS film and the polysilicon film are reduced by the HTO film layer, and further, due to segregation of carbon or the like from the TEOS film to the polysilicon film. Since the occurrence of a short circuit or the like can be prevented, the off characteristics of the TFT element can be improved.
JP 2005-86004 A

  By the way, in this type of electro-optical device, it is necessary to improve the transistor characteristics of the TFT element at a higher level in order to further improve the image quality.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide an electro-optical device capable of improving the transistor characteristics of a TFT element.

  The present invention provides a transistor provided as a switching element in a pixel provided corresponding to the intersection of a plurality of scanning lines and a plurality of data lines, and the transistor element is formed on polycrystalline silicon formed on a base insulating film An electro-optical device comprising a semiconductor layer comprising: a gate insulating film; and a gate electrode, wherein the base insulating film has a refractive index of 1.46 to 1 at a boundary with the semiconductor layer. .49 silicon oxide film.

  According to such a configuration, the crystallinity of the polycrystalline silicon is improved by the influence of the silicon oxide film having a refractive index of 1.46 to 1.49. Off characteristics are improved.

  According to the present invention, a pixel provided corresponding to the intersection of a plurality of scanning lines and a plurality of data lines is provided with a transistor element as a switching element, and the transistor element is formed on a base insulating film. An electro-optical device comprising a semiconductor layer made of crystalline silicon, a gate insulating film, and a gate electrode made of polycrystalline silicon, wherein the gate insulating film is refracted at a boundary with the gate electrode. A silicon oxide film having a rate of 1.46 to 1.49 is provided.

  According to such a configuration, the crystallinity of the polycrystalline silicon constituting the transistor element is improved by the influence of the silicon oxide film having a refractive index of 1.46 to 1.49. In this case, the off characteristics are improved.

  According to the present invention, a pixel provided corresponding to the intersection of a plurality of scanning lines and a plurality of data lines is provided with a transistor element as a switching element, and the transistor element is formed on a base insulating film. An electro-optical device comprising a semiconductor layer made of crystalline silicon, a gate insulating film, and a gate electrode made of polycrystalline silicon, wherein the base insulating film is refracted at a boundary with the semiconductor layer. A silicon oxide film having a refractive index of 1.46 to 1.49 is provided, and the gate insulating film has a silicon oxide film having a refractive index of 1.46 to 1.49 at a boundary with the gate electrode. And

  According to such a configuration, the crystallinity of polycrystalline silicon constituting the transistor element is improved by the influence of the silicon oxide film having a refractive index of 1.46 to 1.49. Will improve.

  Further, the thickness of the silicon oxide film as the base insulating film is in the range of 30 to 70 nm.

  According to such a configuration, the silicon oxide film functions as a contamination prevention film, and the crack resistance of the semiconductor layer is ensured.

  In addition, the thickness of the silicon oxide film of the gate insulating film is formed in the range of 40 to 60 nm.

  According to such a structure, according to such a structure, the function as a gate insulating film is ensured.

  The silicon oxide film is a high temperature silicon oxide film.

  According to such a configuration, the crystallinity of the polycrystalline silicon constituting the transistor element is preferably improved by the influence of the silicon oxide film.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. The drawings relate to one embodiment of the present invention, and FIG. 1 is a cross-sectional view showing a pixel structure of an electro-optical device according to an embodiment of the present invention. This embodiment is applied to a liquid crystal device such as a TFT substrate. FIG. 2 is a plan view of the liquid crystal device, which is the electro-optical device according to the present embodiment, viewed from the counter substrate side together with the components formed thereon. FIG. 3 is a cross-sectional view showing the liquid crystal device cut along the line HH ′ in FIG. FIG. 4 is an equivalent circuit diagram of various elements and wirings in a plurality of pixels constituting the pixel region of the liquid crystal device. FIG. 5 is a VG-ID characteristic diagram of the TFT element when the HTO film of FIG. 1 is set to each refractive index. FIG. 6A is a model diagram showing an HTO film having a refractive index of 1.465, FIG. 6B is a model diagram showing a state after annealing of the HTO film of FIG. 6A, and FIG. FIG. 4D is a model diagram showing a state in which amorphous silicon is laminated on the HTO film, and FIG. 4D is a model diagram showing a state in which amorphous silicon is laminated after annealing the HTO film having a refractive index of 1.445. FIG. 7 is a characteristic diagram showing the relationship between the N ₂ O flow rate and the refractive index when the HTO film is formed by the CVD method, and FIG. 8 is the SiH ₄ flow rate and the refractive index when the HTO film is formed by the CVD method. It is a characteristic view which shows the relationship. 9 is a cross-sectional view showing a pixel structure of an electro-optical device according to a modification of the present invention, and FIG. 10 is a VG-ID characteristic diagram of a TFT element when the HTO film of FIG. 9 is set to each refractive index. FIG. 11 is a cross-sectional view illustrating a pixel structure of an electro-optical device according to a modified example of the invention. In each of the above drawings, the scale is different for each layer and each member so that each layer and each member can be recognized in the drawing.

First, an overall configuration of a liquid crystal device which is an electro-optical device according to the present embodiment will be described with reference to FIGS.
As shown in FIGS. 2 and 3, the liquid crystal device is configured by enclosing a liquid crystal 50 between a TFT substrate 10 which is an element substrate and a counter substrate 20. On the TFT substrate 10, pixel electrodes (ITO) 9a constituting pixels are arranged in a matrix. A counter electrode (ITO) 21 is provided on the entire surface of the counter substrate 20.

  Further, the counter substrate 20 is provided with a light shielding film 53 as a frame for partitioning the display area 10a. As described above, a transparent conductive film such as ITO is formed on the entire surface of the counter substrate 20 as the counter electrode 21, and a polyimide-based alignment film 22 is formed on the entire surface of the counter electrode 21. The alignment film 22 is rubbed in a predetermined direction so as to give a predetermined pretilt angle to the liquid crystal molecules.

  In a region outside the light shielding film 53, a sealing material 52 that encloses liquid crystal is formed between the TFT substrate 10 and the counter substrate 20. The sealing material 52 is disposed so as to substantially match the contour shape of the counter substrate 20, and fixes the TFT substrate 10 and the counter substrate 20 to each other. The sealing material 52 is missing in a part of one side of the TFT substrate 10, and a liquid crystal injection port 108 for injecting the liquid crystal 50 is formed. Liquid crystal is injected from the liquid crystal injection port 108 into the gap between the element substrate 10 and the counter substrate 20 bonded together. After the liquid crystal injection, the liquid crystal injection port 108 is sealed with a sealing material 109.

  Conductive portions 106 are formed at the four corner portions of the sealing material 52. The conductive portion 106 includes an adhesive material and a conductive material amount. The conductive portion 106 contacts the upper and lower conductive terminals 107 of the TFT substrate 10 at the lower end, and contacts the common electrode of the counter substrate 20 at the upper end. Can be electrically connected to each other.

  In an area outside the sealing material 52, an image signal is supplied to the data line 6a (see FIG. 4) at a predetermined timing to connect the data line driving circuit 101 that drives the data line 6a and an external circuit. The external connection terminal 102 is provided along one side of the TFT substrate 10. A scanning line driving circuit 104 that drives a TFT 30 (see FIG. 4) as a switching element by supplying a scanning signal to the scanning line 11a (see FIG. 4) at a predetermined timing along two sides adjacent to the one side. Is provided. The scanning line driving circuit 104 is formed on the TFT substrate 10 at a position facing the light shielding film 53 inside the sealing material 52. Further, on the TFT substrate 10, wiring 105 for connecting the data line driving circuit 101, the scanning line driving circuit 104, and the external connection terminal 102 is provided to face the three sides of the light shielding film 53.

  As shown in FIG. 4, in the pixel region, a plurality of scanning lines 11a and a plurality of data lines 6a are wired so as to cross each other, and a pixel electrode is formed in a region partitioned by the scanning lines 11a and the data lines 6a. 9a are arranged in a matrix. A TFT 30 is provided corresponding to each intersection of the scanning line 11 a and the data line 6 a, and the pixel electrode 9 a is connected to the TFT 30.

  In this embodiment, the TFT 30 is a polycrystalline polysilicon TFT, and the TFT 30 is turned on by an ON signal of the scanning line 11a, whereby an image signal supplied to the data line 6a is supplied to the pixel electrode 9a. A voltage between the pixel electrode 9 a and the counter electrode 21 provided on the counter substrate 20 is applied to the liquid crystal 50.

  In the present embodiment, a storage capacitor 70 is provided in parallel with the pixel electrode 9a, and the storage capacitor 70 causes the voltage of the pixel electrode 9a to be longer by, for example, three digits than the time when the source voltage is applied. Holding is possible. The storage capacitor 70 improves the voltage holding characteristic and enables image display with a high contrast ratio.

  FIG. 1 is a schematic cross-sectional view of a liquid crystal device focusing on one pixel.

  A plurality of pixel electrodes 9a are provided in a matrix on the TFT substrate 10, and data lines 6a and scanning lines 11a are provided along the vertical and horizontal boundaries of the pixel electrodes 9a. As will be described later, the data line 6a has a laminated structure including an aluminum film, and the scanning line 11a is made of, for example, a conductive polysilicon film. The scanning line 11a is electrically connected to the gate electrode 3a facing the channel region 1a 'in the semiconductor layer 1a. That is, the pixel switching TFT 30 is configured by disposing the gate electrode 3a and the channel region 1a 'connected to the scanning line 11a so as to face each other at the intersection of the scanning line 11a and the data line 6a. Here, in FIG. 1, a TFT 30 is, for example, an n-channel TFT in which a V group element dopant is slightly doped by ion implantation or the like.

  On the TFT substrate 10, in addition to the TFT 30 and the pixel electrode 9a, various configurations including these are provided in a laminated structure. As shown in FIG. 1, this stacked structure includes, in order from the bottom, a first layer including the scanning line 11a, a second layer including the TFT 30 including the gate electrode 3a, a third layer including the storage capacitor 70, and the data line 6a. And the like, the fifth layer including the shield layer 400 and the like, and the sixth layer including the pixel electrode 9a and the alignment film 16 and the like. Further, the base insulating film 12 is provided between the first layer and the second layer, the first interlayer insulating film 41 is provided between the second layer and the third layer, and the second interlayer insulating film 42 is provided between the third layer and the fourth layer. A third interlayer insulating film 43 is provided between the fourth layer and the fifth layer, and a fourth interlayer insulating film 44 is provided between the fifth layer and the sixth layer, so that the above-described elements are short-circuited. Is preventing. Further, these various insulating films 12, 41, 42, 43 and 44 are also provided with, for example, a contact hole for electrically connecting the high concentration source region 1d in the semiconductor layer 1a of the TFT 30 and the data line 6a. It has been.

Hereinafter, each of these elements will be described in order from the bottom.
The first layer includes, for example, a simple metal or alloy containing at least one of high melting point metals such as Ti (titanium), Cr (chromium), W (tungsten), Ta (tantalum), and Mo (molybdenum). A scanning line 11a made of metal silicide, polysilicide, a laminate of these, or conductive polysilicon is provided. The scanning line 11a has a function of simultaneously controlling ON / OFF of the TFTs 30 existing in the same row. The scanning line 11a is formed so as to substantially fill a region where the pixel electrode 9a is not formed, and also has a function of blocking light entering the TFT 30 from below. Thereby, generation of light leakage current in the semiconductor layer 1a of the TFT 30 is suppressed, and high-quality image display without flicker or the like is possible.

  In the second layer, the TFT 30 including the gate electrode 3a is provided. As shown in FIG. 1, the TFT 30 has an LDD (Lightly Doped Drain) structure, and includes the gate electrode 3a described above, for example, a polysilicon film, and a channel formed by an electric field from the gate electrode 3a. The channel region 1a ′ of the semiconductor layer 1a to be formed, the insulating film 2 including a gate insulating film that insulates the gate electrode 3a from the semiconductor layer 1a, the low concentration source region 1b and the low concentration drain region 1c in the semiconductor layer 1a, and the high concentration. A source region 1d and a high concentration drain region 1e are provided.

  In the second layer, a relay electrode 719 is formed as the same film as the gate electrode 3a described above. The relay electrode 719 is formed in an island shape so as to be positioned approximately at the center of one side of each pixel electrode 9a when seen in a plan view. Since the relay electrode 719 and the gate electrode 3a are formed as the same film, when the latter is made of a conductive polysilicon film or the like, the former is also made of a conductive polysilicon film or the like.

  The TFT 30 described above preferably has an LDD structure as shown in FIG. 1, but may have an offset structure in which no impurity is implanted into the low concentration source region 1b and the low concentration drain region 1c. A self-aligned TFT that implants impurities at a high concentration as a mask and forms a high concentration source region and a high concentration drain region in a self-aligning manner may be used. In the present embodiment, only one gate electrode of the pixel switching TFT 30 is disposed between the high-concentration source region 1d and the high-concentration drain region 1e. However, two or more gates are interposed between these gate electrodes. An electrode may be arranged. If the TFT is configured with dual gates or triple gates or more in this way, leakage current at the junction between the channel and the source and drain regions can be prevented, and the off-time current can be reduced.

  A base insulating film 12 is provided on the scanning line 11 a described above and below the TFT 30. In addition to the function of insulating the scanning line 11a and the TFT 30, the base insulating film 12 is formed on the entire surface of the TFT substrate 10 so that pixel switching due to roughness during polishing of the surface of the TFT substrate 10 or dirt remaining after cleaning is performed. The TFT 30 has a function of preventing characteristic changes. In the present embodiment, the base insulating film 12 is composed of a two-layer film as will be described later.

  In the base insulating film 12, grooves (contact holes) 12cv having the same width as the channel length of the semiconductor layer 1a extending along the data line 6a described later are dug on both sides of the semiconductor layer 1a in plan view. Corresponding to the groove 12cv, the gate electrode 3a stacked above includes a portion formed in a concave shape on the lower side. Further, since the gate electrode 3a is formed so as to fill the entire groove 12cv, a side wall portion 3b formed integrally with the gate electrode 3a is extended. Yes. As a result, the semiconductor layer 1a of the TFT 30 is covered from the side as viewed in a plan view, and at least light from this portion is prevented from entering.

  Further, the side wall 3b is formed so as to fill the groove 12cv and so that the lower end thereof is in contact with the scanning line 11a. Accordingly, the scanning line 11a and the gate electrode 3a in the same row have the same potential. A structure in which another scanning line including the gate electrode 3a is formed so as to be parallel to the scanning line 11a may be employed. In this case, the scanning line 11a and the other scanning line have a redundant wiring structure. Thereby, for example, even when a part of the scanning line 11a has some defect and normal energization is impossible, another scanning line in the same row as the scanning line 11a is not present. As long as it is sound, the operation control of the TFT 30 can still be normally performed through the soundness.

  In the third layer, a storage capacitor 70 is provided. The storage capacitor 70 includes a lower electrode 71 as a pixel potential side capacitor electrode connected to the high concentration drain region 1e of the TFT 30 and the pixel electrode 9a, and a capacitor electrode 300 as a fixed potential side capacitor electrode. It is formed by arrange | positioning through. According to the storage capacitor 70, it is possible to remarkably improve the potential holding characteristic in the pixel electrode 9a. Further, since the storage capacitor 70 is formed so as not to reach the light transmission region substantially corresponding to the formation region of the pixel electrode 9a (in other words, formed so as to be within the light shielding region), The pixel aperture ratio of the entire electro-optical device is kept relatively large, and thus a brighter image can be displayed.

  More specifically, the lower electrode 71 is made of, for example, a conductive polysilicon film and functions as a pixel potential side capacitor electrode. However, the lower electrode 71 may be composed of a single layer film or a multilayer film containing a metal or an alloy. In addition to the function as a pixel potential side capacitor electrode, the lower electrode 71 has a function of relay-connecting the pixel electrode 9a and the high concentration drain region 1e of the TFT 30. This relay connection is made via a relay electrode 719 as will be described later.

  The capacitor electrode 300 functions as a fixed potential side capacitor electrode of the storage capacitor 70. In order to set the capacitor electrode 300 to a fixed potential, the capacitor electrode 300 is electrically connected to a shield layer 400 described later, which is set to a fixed potential.

  The capacitor electrode 300 is formed in an island shape on the TFT substrate 10 so as to correspond to each pixel, and the lower electrode 71 is formed to have substantially the same shape as the capacitor electrode 300. . As a result, the storage capacitor 70 does not have a wasteful spread in a plane, that is, without decreasing the pixel aperture ratio, and can achieve the maximum capacitance value under the circumstances. That is, the storage capacitor 70 has a smaller area and a larger capacitance value.

  As shown in FIG. 1, the dielectric film 75 is, for example, a relatively thin HTO (High Temperature Oxide) film having a film thickness of about 5 to 200 nm, a silicon oxide film such as an LTO (Low Temperature Oxide) film, or a silicon nitride film. Consists of From the viewpoint of increasing the storage capacitor 70, the thinner the dielectric film 75 is, the better as long as the reliability of the film is sufficiently obtained. As shown in FIG. 1, the dielectric film 75 has a two-layer structure including a silicon oxide film 75a as a lower layer and a silicon nitride film 75b as an upper layer. The presence of the silicon nitride film 75b having a relatively large dielectric constant makes it possible to increase the capacitance value of the storage capacitor 70, and the presence of the silicon oxide film 75a reduces the pressure resistance of the storage capacitor 70. I won't let you down. Thus, by making the dielectric film 75 have a two-layer structure, it is possible to enjoy two conflicting effects.

  In addition, the presence of the silicon nitride film 75b makes it possible to prevent water from entering the TFT 30 in advance. As a result, a situation in which the threshold voltage of the TFT 30 rises is not caused, and a relatively long-term apparatus operation is possible. In the present embodiment, the dielectric film 75 has a two-layer structure. However, the dielectric film 75 has a three-layer structure such as a silicon oxide film, a silicon nitride film, and a silicon oxide film, or more. You may comprise so that it may have the laminated structure of these.

  A first interlayer insulating film 41 is formed on the TFT 30 to the gate electrode 3 a and the relay electrode 719 described above and below the storage capacitor 70. In the first interlayer insulating film 41, a contact hole 81 that electrically connects the high-concentration source region 1d of the TFT 30 and a data line 6a described later opens while penetrating the second interlayer insulating film 42 described later. It is holed. The first interlayer insulating film 41 is provided with a contact hole 83 that electrically connects the high-concentration drain region 1 e of the TFT 30 and the lower electrode 71 constituting the storage capacitor 70.

  Further, the first interlayer insulating film 41 is provided with a contact hole 881 for electrically connecting the lower electrode 71 serving as a pixel potential side capacitor electrode constituting the storage capacitor 70 and the relay electrode 719. . In addition, a contact hole 882 that electrically connects the relay electrode 719 and a second relay electrode 6a2 described later is formed in the first interlayer insulating film 41 while penetrating the second interlayer insulating film 42 described later. Has been.

  As shown in FIG. 1, the contact hole 882 is formed in a region other than the storage capacitor 70, and the lower electrode 71 is once detoured to the lower relay electrode 719 and drawn out to the upper layer through the contact hole 882. Therefore, even when the lower electrode 71 is connected to the upper pixel electrode 9 a, it is not necessary to form the lower electrode 71 wider than the dielectric film 75 and the capacitor electrode 300. Therefore, the lower electrode 71, the dielectric film 75, and the capacitor electrode 300 can be simultaneously patterned in one etching process. As a result, the etching rates of the lower electrode 71, the dielectric film 75, and the capacitor electrode 300 can be easily controlled, and the degree of freedom in designing the film thickness and the like can be increased.

  In addition, since the dielectric film 75 is formed in the same shape as the lower electrode 71 and the capacitor electrode 300 and does not have a spread, in the case of performing a hydrogenation process on the semiconductor layer 1 a of the TFT 30, It is also possible to obtain an effect that it is possible to easily reach the semiconductor layer 1a through the opening around the storage capacitor 70.

  A data line 6a is provided in the fourth layer. The data line 6 a is formed in a stripe shape so as to coincide with the extending direction of the semiconductor layer 1 a of the TFT 30. As shown in FIG. 1, the data line 6a includes, in order from the lower layer, a layer made of aluminum (reference numeral 41A in FIG. 1), a layer made of titanium nitride (see reference numeral 41TN in FIG. 1), and a layer made of a silicon nitride film (see FIG. It is formed as a film having a three-layer structure denoted by reference numeral 401 in FIG. The silicon nitride film is patterned to a slightly larger size so as to cover the lower aluminum layer and titanium nitride layer. Of these, the data line 6a contains aluminum, which is a relatively low resistance material, so that the supply of image signals to the TFT 30 and the pixel electrode 9a can be realized without delay. On the other hand, the formation of a silicon nitride film that is relatively excellent in preventing moisture from entering on the data line 6a can improve the moisture resistance of the TFT 30, and can achieve a long life. The silicon nitride film is preferably a plasma silicon nitride film.

  In addition, a shield layer relay layer 6a1 and a second relay electrode 6a2 are formed on the fourth layer as the same film as the data line 6a. These are not formed so as to have a planar shape continuous with the data line 6a when viewed in plan, but are formed so as to be divided by patterning. The shield layer relay layer 6a1 and the second relay electrode 6a2 are in the same process as the data line 6a, and have a three-layer structure of an aluminum layer, a titanium nitride layer, and a plasma nitride film layer in order from the lower layer. It is formed as. The plasma nitride film is patterned to a slightly larger size so as to cover the lower aluminum layer and titanium nitride layer. The titanium nitride layer functions as a barrier metal for preventing etching through of the contact holes 803 and 804 formed for the shield layer relay layer 6a1 and the second relay electrode 6a2. Further, by forming a plasma nitride film that is relatively excellent in the action of blocking moisture ingress on the shield layer relay layer 6a1 and the second relay electrode 6a2, the moisture resistance of the TFT 30 can be improved. Longer service life can be realized. The plasma nitride film is preferably a plasma silicon nitride film.

  A second interlayer insulating film 42 is formed on the storage capacitor 70 and below the data line 6a. In the second interlayer insulating film 42, a contact hole 81 for electrically connecting the high concentration source region 1d of the TFT 30 and the data line 6a is opened, and the shield layer relay layer 6a1 and the storage capacitor 70 are formed. A contact hole 801 is formed to electrically connect the capacitor electrode 300, which is the upper electrode. Further, a contact hole 882 for electrically connecting the second relay electrode 6a2 and the relay electrode 719 is formed in the second interlayer insulating film.

  A shield layer 400 is formed on the fifth layer. The shield layer 400 is formed in a lattice shape in plan view. The shield layer 400 extends from the image display region 10a in which the pixel electrode 9a is disposed to the periphery thereof, and is electrically connected to a constant potential source to have a fixed potential. The constant potential source may be a positive potential source or a negative potential constant source supplied to the data line driving circuit 101 described later, or a constant potential source supplied to the counter electrode 21 of the counter substrate 20.

  Further, a third relay electrode 402 as a relay layer is formed on the fifth layer as the same film as the shield layer 400. The third relay electrode 402 has a function of relaying an electrical connection between the second relay electrode 6a2 and the pixel electrode 9a through a contact hole 89 described later. The shield layer 400 and the third relay electrode 402 are not continuously formed in a planar shape, but are formed so as to be separated by patterning.

  On the other hand, the shield layer 400 and the third relay electrode 402 described above have a two-layer structure in which a lower layer is made of aluminum and an upper layer is made of titanium nitride. In the third relay electrode 402, the lower layer made of aluminum is connected to the second relay electrode 6a2, and the upper layer made of titanium nitride is connected to the pixel electrode 9a made of ITO or the like. Yes. When aluminum and ITO are directly connected, electric corrosion occurs between the two, and preferable electrical connection cannot be realized due to disconnection of aluminum or insulation due to formation of alumina. On the other hand, since titanium nitride and ITO are connected, contact resistance is low and good connectivity is obtained.

  Furthermore, since the shield layer 400 and the third relay electrode 402 include aluminum that is relatively excellent in light reflection performance and include titanium nitride that is relatively excellent in light absorption performance, the shield layer 400 and the third relay electrode 402 can function as a light shielding layer. That is, according to these, it is possible to block the progress of incident light (see FIG. 1) on the semiconductor layer 1a of the TFT 30 on the upper side thereof. Such a light shielding function can be similarly applied to the capacitor electrode 300 and the data line 6a described above. The shield layer 400, the third relay electrode 402, the capacitor electrode 300, and the data line 6 a form an upper light-shielding film that blocks light incident on the TFT 30 from the upper side while forming a part of the laminated structure constructed on the TFT substrate 10. Function.

  A third interlayer insulating film 43 is formed on the data line 6 a and below the shield layer 400. In the third interlayer insulating film 43, a contact hole 803 for electrically connecting the shield layer 400 and the shield layer relay layer 6a1, and a third relay electrode 402 and the second relay electrode 6a2 are electrically connected. Contact holes 804 for connecting to each are opened.

  In the sixth layer, the pixel electrodes 9a are formed in a matrix as described above, and the alignment film 16 is formed on the pixel electrodes 9a. A fourth interlayer insulating film 44 is formed under the pixel electrode 9a. In the fourth interlayer insulating film 44, a contact hole 89 for electrically connecting the pixel electrode 9a and the third relay electrode 402 is opened.

  The surfaces of the third and fourth interlayer insulating films 43 and 44 are planarized by a CMP (Chemical Mechanical Polishing) process or the like. Alignment defects of the liquid crystal layer 50 due to steps due to various wirings, elements, etc. existing below the planarized interlayer insulating films 43 and 44 are reduced. However, instead of or in addition to performing the planarization process on the third and fourth interlayer insulating films 43 and 44 in this way, the TFT substrate 10, the base insulating film 12, the first interlayer insulating film 41, and the second interlayer A planarization process may be performed by digging a groove in at least one of the insulating film 42 and the third interlayer insulating film 43 and embedding a wiring such as the data line 6a or the TFT 30 or the like.

In addition, the storage capacitor 70 has a three-layer structure of a pixel potential side capacitor electrode, a dielectric film, and a fixed potential side capacitor electrode in order from the bottom, but may have a structure opposite to this. . In the liquid crystal device having such a configuration, the base insulating film 12 is, for example, a TEOS film or HDP (High Density Plasma) formed using a TEOS (Tetra-Ethyl-Ortho-Silicate) gas by reduced pressure or atmospheric pressure CVD. A lower base insulating film 12a made of a silicon oxide film or the like formed using SiH ₄ and O ₂ gases by CVD is formed in the lower layer, and an HTO film 12b that is a silicon oxide film is formed thereon 2 It is composed of a layered film.
The lower base insulating film 12a has a high film forming property, can be formed in a good covering state with a relatively thick film thickness, and has a sufficient insulating property.

  On the other hand, the HTO film 12b is formed with a film thickness in the range of 30 to 70 nm, for example. The HTO film 12b is formed at the boundary with the semiconductor layer 1a with a film thickness of 30 nm or more, thereby reducing the influence of the organic gas remaining in the lower base insulating film 12a on the semiconductor layer 1a. Or as a crack prevention film that relieves stress. Further, since the HTO film 12b is formed with a film thickness of 70 nm or less, excessive stress is generated in the HTO film 12b and cracks and the like are prevented from occurring in the semiconductor layer 1a.

  Further, the HTO film 12b preferably has a Si-rich composition than usual. Here, the HTO film having a normal composition means a composition in which the Si component is substantially saturated. Specifically, the HTO film is formed with a composition having a refractive index RI = 1.44 to 1.45. It is an HTO film. On the other hand, as the HTO film 12b of the present embodiment, a Si-rich composition having a higher refractive index (for example, RI = 1.46 to 1.49) than the normal one is preferable. It is used for.

Such an HTO film 12b is formed by using, for example, a CVD apparatus, and its composition (refractive index RI) is controlled by, for example, a flow ratio of SiH ₄ gas, which is a raw material gas, and N ₂ O gas. Is possible. Specifically, as shown in FIGS. 7 and 8, the formation of the high-refractive-index HTO film 12b is realized by increasing the flow rate ratio of SiH ₄ gas as compared with the case of forming a normal HTO film. The Incidentally, FIG. 7, the flow rate of SiH ₄ gas was a fixed value, the refractive index RI of the HTO film formed in the case of changing the flow rate of _{N 2} O gas, FIG. 8, the _{N 2} O gas The refractive index RI of the HTO film formed when the flow rate is fixed and the flow rate of the SiH ₄ gas is changed is shown.

  A TFT element in which a semiconductor layer is formed on a high-refractive index HTO film is more on-characteristic than a TFT element in which a semiconductor layer is formed on a normal HTO film (for example, an HTO film with RI = 1.44). Both (Ion) and off characteristics (Ioff) are improved. Here, the experimental result about the VG-ID characteristic of the TFT element formed on the HTO film | membrane of each refractive index is shown in FIG. This experimental result confirms that the transistor characteristics of the TFT element formed on the HTO film with RI = 1.46 are dramatically improved over the TFT element formed on the HTO film with RI = 1.445. It was done. Further, it was confirmed that the limit on the high refractive index side of the HTO film 12b for realizing good transistor characteristics of the TFT is about RI = 1.49.

This improvement in transistor characteristics is presumed to be due to the improved crystallinity of the polysilicon film constituting the semiconductor layer 1a due to the influence of the high refractive index HTO film 12b.
More specifically, a large amount of Si—H exists in a high refractive index HTO film formed under a condition where the flow rate ratio of SiH ₄ is higher than that during normal HTO film formation (FIG. 6 (a)). When such an HTO film is annealed, the H ₂ component in the film is eliminated and a large amount of Si ³⁺ exists in the film (see FIG. 6B). That is, a large amount of Si ³⁺ can be present in the HTO film which is originally composed of SiO or SiO ₂ by self-dissociation. Since such an HTO film has a lattice constant close to that of amorphous silicon, when amorphous silicon (a-Si) formed on the HTO film in the manufacturing process of the semiconductor layer 1a is polycrystallized, Si ³⁺ It is presumed that dangling bonds at the interface are terminated (terminated) and the crystallinity is improved (see FIG. 6C). On the other hand, since it is difficult to make a large amount of Si ³⁺ exist in a normal HTO film, it is considered difficult to obtain sufficient crystallinity when polymorphizing amorphous silicon ( (Refer FIG.6 (d)).

  Here, in the present embodiment, the technology for improving the transistor characteristics of the n-channel TFT element by the HTO film having a refractive index of 1.46 to 1.49 can be applied to the p-channel TFT element. Is possible. FIG. 9 is a schematic cross-sectional view showing a modification in which the present invention is applied to a liquid crystal device using a p-channel TFT 30 as a switching element. As shown in FIG. 9, the insulating film 2 constituting the gate insulating film of the TFT 30 has a normal HTO film 2a formed in the lower layer by thermal oxidation or the like of the semiconductor layer 1a and a refractive index formed in the upper layer of 1 And a high-refractive-index HTO film 2b of .46 to 1.49. Here, in order to ensure the function of the insulating film 2 as the gate insulating film of the TFT 30, it is desirable that the thickness of the HTO film 2b is formed in the range of 40 nm to 60 nm.

  As described above, the TFT 30 in which the high-refractive-index HTO film 2b is formed at the boundary with the gate electrode 3a has improved off characteristics as compared with, for example, a TFT in which the gate insulating film is formed of a single layer of a normal HTO film. Here, a normal (for example, RI = 1.44) p-channel TFT element in which a gate insulating film is formed as a single layer, a normal HTO film, and a high refractive index (for example, RI = 1.465). FIG. 10 shows the experimental results of the VG-ID characteristics of the p-channel TFT element in which the gate insulating film is formed in two layers with the HTO film. As a result of this experiment, a TFT element in which a gate electrode is formed of two layers of a normal HTO film and a high refractive index HTO film is more effective than a TFT element in which a gate insulating film is formed of a normal HTO film single layer. It was confirmed that the characteristics (off characteristics) were drastically improved.

  Furthermore, in the present embodiment, for example, as shown in FIG. 11, an HTO film 12b having a refractive index of 1.46 to 1.49 is formed at the boundary with the semiconductor layer 1a, and at the boundary with the gate electrode 3a. By forming the HTO film 2b having a refractive index of 1.46 to 1.49, the transistor characteristics of the TFT 30 can be improved.

  The present invention can also be applied to a microlens substrate, a counter substrate with a microlens for a liquid crystal display device, a liquid crystal display device, and a projection type liquid crystal display device using the same. Furthermore, the present invention can be used for transmissive, reflective, and transflective electro-optical devices.

  The electro-optical device may be a display device that forms elements on a semiconductor substrate, for example, LCOS (Liquid Crystal On Silicon). In LCOS, a single crystal silicon substrate is used as an element substrate, and a transistor is formed on a single crystal silicon substrate as a switching element used for a pixel or a peripheral circuit. In addition, a reflective pixel electrode is used for the pixel, and each element of the pixel is formed below the pixel electrode.

    The electro-optical device of the present invention is a mobile phone, a portable information device called PDA (Personal Digital Assistants), a portable personal computer, a personal computer, a workstation, a digital still camera, an in-vehicle monitor, a digital video camera, and a liquid crystal television. It can be widely used in electronic devices such as a viewfinder type, monitor direct view type video tape recorder, car navigation device, pager, electronic notebook, calculator, word processor, workstation, videophone, and POS terminal.

Sectional view showing pixel structure of electro-optical device A plan view of a liquid crystal device, which is an electro-optical device, viewed from the counter substrate side together with the components formed thereon Sectional drawing which cuts and shows a liquid crystal device in the position of the HH 'line of FIG. Equivalent circuit diagram of various elements, wiring, etc. in a plurality of pixels constituting the pixel area of the liquid crystal device VG-ID characteristic diagram of TFT element when HTO film of FIG. 1 is set to each refractive index (A) is a model diagram showing an HTO film having a refractive index of 1.465, (b) is a model diagram showing a state after annealing of the HTO film of (a), and (c) is amorphous to the HTO film of (b). Model diagram showing a state in which silicon is laminated, (d) is a model diagram showing a state in which amorphous silicon is laminated after annealing an HTO film having a refractive index of 1.445. Characteristic diagram showing the relationship between N ₂ O flow rate and refractive index when forming an HTO film by CVD Characteristic diagram showing the relationship between the flow rate of SiH ₄ and the refractive index when forming an HTO film by the CVD method Sectional drawing which shows the pixel structure of the electro-optical apparatus which concerns on the modification of this invention VG-ID characteristic diagram of TFT element when HTO film of FIG. 9 is set to each refractive index Sectional drawing which shows the pixel structure of the electro-optical apparatus which concerns on the modification of this invention

Explanation of symbols

    DESCRIPTION OF SYMBOLS 1a ... Semiconductor layer, 2 ... Insulating film, 2b ... HTO film (silicon oxide film), 3a ... Gate electrode, 6a ... Data line, 11a ... Scanning line, 12 ... Base insulating film, 12b ... HTO film (silicon oxide film) 30 ... TFT (switching element)

Claims (6)

A pixel provided corresponding to the intersection of a plurality of scanning lines and a plurality of data lines has a transistor element as a switching element, and the transistor element is a semiconductor layer made of polycrystalline silicon formed on a base insulating film An electro-optical device comprising a gate insulating film and a gate electrode,
The electro-optical device, wherein the base insulating film has a silicon oxide film having a refractive index of 1.46 to 1.49 at a boundary with the semiconductor layer. A pixel provided corresponding to the intersection of a plurality of scanning lines and a plurality of data lines has a transistor element as a switching element, and the transistor element is a semiconductor layer made of polycrystalline silicon formed on a base insulating film An electro-optic device comprising a gate insulating film and a gate electrode made of polycrystalline silicon,
The electro-optical device, wherein the gate insulating film has a silicon oxide film having a refractive index of 1.46 to 1.49 at a boundary with the gate electrode. A pixel provided corresponding to the intersection of a plurality of scanning lines and a plurality of data lines has a transistor element as a switching element, and the transistor element is a semiconductor layer made of polycrystalline silicon formed on a base insulating film An electro-optic device comprising a gate insulating film and a gate electrode made of polycrystalline silicon,
The base insulating film has a silicon oxide film having a refractive index of 1.46 to 1.49 at the boundary with the semiconductor layer,
The electro-optical device, wherein the gate insulating film has a silicon oxide film having a refractive index of 1.46 to 1.49 at a boundary with the gate electrode.   4. The electro-optical device according to claim 1, wherein a thickness of the silicon oxide film as the base insulating film is formed in a range of 30 to 70 nm.   4. The electro-optical device according to claim 2, wherein the thickness of the silicon oxide film of the gate insulating film is in the range of 40 to 60 nm.   The electro-optical device according to claim 1, wherein the silicon oxide film is a high-temperature silicon oxide film.

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