JP2007081385A - Source drain electrode, transistor substrate and method for manufacturing the same, and display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a source drain electrode in which a barrier metal layer of a lower part can be eliminated, a production process can be simplified without increasing the number of processes, an Al based alloy film can be connected to a semiconductor layer of a thin film transistor directly and surely, and an electrical resistivity between transparent pixel electrodes can be lowered even in the case of applying a low thermal process temperature to an Al alloy film. <P>SOLUTION: A thin film transistor substrate is provided with a semiconductor layer 33 of a thin film transistor, a source drain electrode 34, and a transparent pixel electrode 5, wherein the source drain electrode 34 is formed with an Al alloy film containing Ni of 0.1 to 6 atom% as an alloy component, and the Al alloy film is directly connected to the semiconductor layer 33 of the thin film transistor. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  TECHNICAL FIELD The present invention relates to a source-drain electrode for a thin film transistor used for a liquid crystal display, a semiconductor, an optical component, etc., a transistor substrate and a manufacturing method thereof, and a display device, and in particular, a novel source-drain electrode containing an Al alloy thin film as a constituent element It is about.

  Liquid crystal display devices used in various fields ranging from small mobile phones to large televisions exceeding 30 inches can be divided into simple matrix liquid crystal display devices and active matrix liquid crystal display devices depending on the pixel driving method. . Among them, an active matrix liquid crystal display device having a thin film transistor (hereinafter referred to as TFT) as a switching element is widely used because it can realize high-precision image quality and can cope with high-speed images. .

  With reference to FIG. 1, the configuration and operation principle of a typical liquid crystal panel applied to an active matrix liquid crystal display device will be described. Here, an example of a TFT substrate using hydrogen amorphous silicon as an active semiconductor layer (hereinafter sometimes referred to as an amorphous silicon TFT substrate) will be described as a representative example, but the present invention is not limited thereto, and polysilicon is used. It may be a TFT substrate.

As shown in FIG. 1, a liquid crystal panel 100 is disposed between a TFT substrate 1, a counter substrate 2 disposed opposite to the TFT substrate 1, and between the TFT substrate 1 and the counter substrate 2, and serves as a light modulation layer. And a functioning liquid crystal layer 3. The TFT substrate 1 has a TFT 4 disposed on an insulating glass substrate 1a, a transparent pixel electrode 5, and a wiring portion 6 including a scanning line and a signal line. The transparent pixel electrode 5 is formed of an indium tin oxide (ITO) film containing about 10% by mass of tin oxide (SnO) in indium oxide (In ₂ O ₃ ). The TFT substrate 1 is driven by a driver circuit 13 and a control circuit 14 connected via a TAB tape 12.

  The counter substrate 2 has a common electrode 7 formed on the entire surface of the insulating glass substrate 1 b on the TFT substrate 1 side, a color filter 8 disposed at a position facing the transparent pixel electrode 5, and the TFT substrate 1. A light shielding film 9 disposed at a position facing the TFT 4 and the wiring portion 6. The counter substrate 2 further includes an alignment film 11 for aligning liquid crystal molecules (not shown) included in the liquid crystal layer 3 in a predetermined direction.

  Polarizing plates 10a and 10b are disposed outside the TFT substrate 1 and the counter substrate 2 (on the side opposite to the liquid crystal layer 3 side), respectively.

  In the liquid crystal panel 100, the alignment direction of liquid crystal molecules in the liquid crystal layer 3 is controlled by an electric field formed between the counter electrode 2 and the transparent pixel electrode 5, and light passing through the liquid crystal layer 3 is modulated. As a result, the amount of light transmitted through the counter substrate 2 is controlled to display an image.

  Next, the configuration and operation principle of a conventional amorphous silicon TFT substrate suitably used for a liquid crystal panel will be described in detail with reference to FIG. FIG. 2 is an enlarged view of a main part A in FIG.

  As shown in FIG. 2, a scanning line (gate thin film wiring) 25 is formed on a glass substrate (not shown), and a part of the scanning line 25 functions as a gate electrode 26 for controlling on / off of the TFT. To do. A gate insulating film (silicon nitride film) 27 is formed so as to cover the gate electrode 26. A signal line (source-drain wiring) 34 is formed so as to intersect the scanning line 25 via the gate insulating film 27, and a part of the signal line 34 functions as a source electrode 28 of the TFT. On the gate insulating film 27, an amorphous silicon channel film (active semiconductor film) 33, a signal line (source-drain wiring) 34, and an interlayer insulating silicon nitride film (protective film) 30 are sequentially formed. This type is generally called a bottom gate type.

The amorphous silicon channel film 33 is composed of an intrinsic layer that is not doped with P (phosphorus) (also referred to as i layer or non-doped layer) and a doped layer that is doped with P (n layer). In the pixel region on the gate insulating film 27, for example, the transparent pixel electrode 5 formed of an ITO film containing SnO in In ₂ O ₃ is disposed. The drain electrode 29 of the TFT is in direct contact with and electrically connected to the transparent pixel electrode 5.

  When the gate voltage is supplied to the gate electrode 26 via the scanning line 25, the TFT 4 is turned on, and the drive voltage supplied in advance to the signal line 34 is transmitted from the source electrode 28 via the drain electrode 29 to the transparent pixel electrode. 5 is supplied. When a driving voltage of a predetermined level is supplied to the transparent pixel electrode 5, as described with reference to FIG. 1, a potential difference is generated between the transparent pixel electrode 5 and the counter electrode 2. As a result, the liquid crystal contained in the liquid crystal layer 3. The molecules are aligned and light modulation is performed.

  In the TFT substrate 1, a signal line (pixel electrode signal line) electrically connected to the transparent pixel electrode 5, a source-drain wiring 34 electrically connected to the source electrode 28 -drain electrode 29, and a gate electrode 26 The scanning lines 25 that are electrically connected have low specific resistance and are easy to process. For example, all of them are pure Al or Al alloys such as Al-Nd (hereinafter collectively referred to as Al-based alloys). 2), and below and below the barrier metal layers 51, 52, 53, 54 made of a refractory metal such as Mo, Cr, Ti, W, etc., as shown in FIG. Is formed.

  First, the reason why the Al-based alloy thin film is connected to the transparent pixel electrode 5 through the barrier metal layers 51 and 52 is that when the Al-based alloy thin film is directly connected to the transparent pixel electrode, the contact resistance increases, and the display quality of the screen is improved. This is because of a decrease. That is, Al constituting the wiring for the transparent pixel electrode is very easily oxidized, and oxygen is generated at the interface between the Al-based alloy thin film and the transparent pixel electrode due to oxygen generated during the film forming process of the liquid crystal panel or oxygen added during film forming. This is because an oxide insulating layer is formed. Moreover, although ITO which comprises a transparent pixel electrode is an electroconductive metal oxide, an electrical ohmic connection cannot be performed with the Al oxide layer produced | generated as mentioned above.

  However, in order to form the barrier metal layer, in addition to the film-forming sputtering apparatus necessary for forming the gate electrode, source electrode, and drain electrode, an extra film-forming chamber for forming the barrier metal must be provided. I must. As the cost of the liquid crystal panel is reduced along with the mass production, the increase in the manufacturing cost and the decrease in the productivity due to the formation of the barrier metal layer cannot be neglected.

  Therefore, electrode materials and manufacturing methods that can omit the formation of the barrier metal layer and can directly connect the Al-based alloy thin film to the transparent pixel electrode have been proposed.

  For example, Patent Document 1 discloses a technique using an indium zinc oxide (IZO) film containing about 10% by mass of zinc oxide in indium oxide as a material for a transparent pixel electrode. However, according to this technique, since the most popular ITO film must be changed to an IZO film, the material cost increases.

  Patent Document 2 discloses a method of modifying the surface of the drain electrode by performing plasma treatment or ion implantation on the drain electrode. However, according to this method, since a process for surface treatment is added, productivity is lowered.

  Patent Document 3 discloses a pure Al or Al first layer and a pure Al or Al containing an impurity such as N, O, Si, and C as a gate electrode, a source electrode, and a drain electrode. The method used is disclosed. According to this method, there is an advantage that the thin films constituting the gate electrode, the source electrode, and the drain electrode can be continuously formed using the same film formation chamber, but the step of forming the second layer containing the impurity described above. Will increase. In addition, in the process of introducing the impurity into the source-drain wiring, the deposit of the source-drain wiring is flakes from the wall surface of the chamber due to the difference in thermal expansion coefficient between the film in which the impurity is mixed and the film in which the impurity is not mixed. As a result, the phenomenon of peeling off frequently occurs. In order to prevent this phenomenon, it is necessary to frequently stop the film forming process and perform maintenance, and the productivity is significantly reduced.

In view of such circumstances, the applicant of the present application can omit the barrier metal layer, simplify it without increasing the number of steps, and connect the Al-based alloy film directly and reliably to the transparent pixel electrode. A method is disclosed (Patent Document 4). In Patent Document 4, an Al-based alloy containing 0.1 to 6 atomic% of at least one selected from the group consisting of Au, Ag, Zn, Cu, Ni, Sr, Ge, Sm, and Bi is used as an alloy component. The above problems are solved by causing at least a part of these alloy components to exist as precipitates or concentrated layers at the interface between the Al-based alloy film and the transparent pixel electrode.
Japanese Patent Laid-Open No. 11-337976 JP-A-11-283934 JP-A-11-284195 JP 2004-214606 A

  Thus, according to Patent Document 4, the Al-based alloy film can be directly connected to the transparent pixel electrode.

  On the other hand, a technique that can directly connect a source-drain wiring made of an Al-based alloy to an amorphous silicon thin film has not yet been disclosed.

  As described above, until now, as the source-drain wiring, wiring in which the barrier metal layers 54 and 53 are laminated on and under the Al-based alloy has been used. Laminated wiring with a three-layer structure in which a 50 nm Mo layer (lower barrier metal layer), a pure Al or Al—Nd alloy thin film having a thickness of about 150 nm, and a Mo layer (upper barrier metal layer) having a thickness of about 50 nm are sequentially formed. Is mentioned. The main reason why the lower barrier metal layer is formed in this way is to prevent interdiffusion between silicon and aluminum at the interface between the Al alloy thin film and the amorphous silicon thin film, while the upper barrier metal layer is formed. The main reason for this is to prevent the formation of hillocks (cove-like projections) on the surface of the Al alloy thin film. A detailed mechanism will be described later.

  However, in order to form the upper and lower barrier metal layers, a film forming apparatus equipped with an extra film forming chamber for forming the barrier metal (typically, a plurality of film forming chambers are connected to the transfer chamber). Cluster tool), which increases manufacturing costs and decreases productivity.

  In addition, in order to taper a multilayer wiring having a three-layer structure by a wet etching method, it is necessary to prepare etchants (etching solutions) for a barrier metal and an Al-based alloy, respectively. Cost increases, such as the need for an etching bath. In addition, for example, it has been attempted to process laminated wiring using the same etchant by forming pure Mo as an upper barrier metal layer and forming an Mo alloy as a lower barrier metal layer, but high-precision processing is performed. It is difficult to do.

  Accordingly, it is desired to provide a source-drain electrode that can omit the lower barrier metal layer and further the upper barrier metal layer and can directly connect the Al-based alloy thin film for source-drain wiring to the amorphous silicon thin film.

  Furthermore, recently, the process temperature for manufacturing a display device tends to be lowered more and more from the viewpoint of improvement in yield and productivity. For example, source / drain electrode materials for amorphous silicon TFTs are required to have low electrical resistivity and heat resistance, and the required specifications have been about 8 μΩ · cm or less in terms of electrical resistivity so far, The temperature was about 350 ° C. This heat-resistant temperature is determined by the maximum temperature applied to the source and drain electrodes in the manufacturing process, and this maximum temperature is the formation temperature of the insulating film formed as a protective film on the electrodes. Recently, it has become possible to obtain a desired insulating film even at a low temperature by improving the film forming technique. In particular, the protective film on the source and drain electrodes can be formed at about 200 ° C.

  Therefore, a source-drain electrode material that has a heat resistance temperature of 200 ° C. and a sufficiently low electric resistivity is required.

  In the above description, the liquid crystal display device has been taken up as a representative. However, the above-described problem is not limited to the liquid crystal display device, and is common to amorphous silicon TFT substrates.

  The present invention has been made paying attention to the above-mentioned circumstances, and the object thereof is to make it possible to omit the lower barrier metal layer, simplify it without increasing the number of steps, and make the Al-based alloy film amorphous. It can be directly and securely connected to the silicon channel film, and low electrical resistivity can be achieved even when a low thermal process temperature of, for example, about 100 ° C. to 300 ° C. is applied to the Al alloy film. It is an object of the present invention to provide a source-drain electrode that can be used. Specifically, even when heat treatment at a low temperature of about 200 ° C. × 20 minutes is performed, the electrical resistivity of the Al alloy film can be reliably achieved at 8 Ω · cm or less, and it is suitable for lowering the processing temperature. Another object is to provide such a source-drain electrode.

  Another object of the present invention is to make it possible to omit not only the lower barrier metal layer but also the upper barrier metal layer, so that the Al-based alloy film can be applied not only to the amorphous silicon channel film but also to the transparent pixel electrode. Is to provide a technology that can be directly and reliably connected.

  A source-drain electrode according to the present invention that has solved the above-mentioned problems is composed of an Al alloy thin film containing 0.1 to 6 atomic% of Ni as an alloy component, and the Al alloy thin film is a semiconductor of the thin film transistor. The point is that it is directly connected to the layer.

  In a preferred embodiment, the Al alloy further contains at least one element selected from the group consisting of Ti, V, Zr, Nb, Mo, Hf, Ta, and W as an alloy component in a range of 0.1 to 1 .. Contains 0 atomic%.

  In a preferred embodiment, the Al alloy further includes Mg, Cr, Mn, Ru, Rh, Pd, Ir, Pt, La, Gd, Tb, Dy, Nd, Y, Co, Fe, Ce, as alloy components. And 0.1 to 2.0 atomic% of at least one element selected from the group consisting of Pr.

  In a preferred embodiment, a compound containing Ni is included at an interface between the thin film of the Al alloy and the semiconductor layer of the thin film transistor.

  In a preferred embodiment, the Ni-containing compound is an intermetallic compound of Al and Ni contained in the Al alloy, a silicide or silicon of Ni contained in the Al alloy and Si contained in a semiconductor layer of the thin film transistor. And at least one compound selected from the group consisting of an intermetallic compound of Al and Ni contained in the Al alloy and Si contained in the semiconductor layer of the thin film transistor.

  In a preferred embodiment, a Ni concentrated layer is present at the interface between the thin film of the Al alloy and the semiconductor layer of the thin film transistor, and the average Ni concentration in the Ni concentrated layer is 2 of the average Ni concentration in the Al alloy. It is more than double.

  In a preferred embodiment, the Al alloy thin film has an electrical resistivity of 8 μΩ · cm or less.

  In a preferred embodiment, the Al alloy thin film is further directly connected to the transparent pixel electrode.

  In a preferred embodiment, AlOx (0 <x ≦ 0.8) is provided at the interface between the Al alloy thin film and the transparent pixel electrode.

  In a preferred embodiment, a Ni concentrated layer is present at the interface between the Al alloy thin film and the transparent pixel electrode, and the average Ni concentration in the Ni concentrated layer is twice the average Ni concentration in the Al alloy. That's it.

  In a preferred embodiment, the transparent pixel electrode is made of indium tin oxide (ITO) or indium zinc oxide (IZO).

  The thin film transistor substrate of the present invention includes any one of the source-drain electrodes described above.

  A display device of the present invention includes the above-described thin film transistor substrate.

A method of manufacturing a thin film transistor substrate according to the present invention is a method of manufacturing the above thin film transistor substrate, the step (a) of preparing a substrate on which a semiconductor layer of the thin film transistor is formed, and the Al on the semiconductor layer of the thin film transistor. A step (b) of forming an alloy thin film and a step (c) of depositing a silicon nitride film on the Al alloy thin film, wherein the step (c) is performed at a temperature of 100 ° C. or higher and 300 ° C. or lower. Heating.
In a preferred embodiment, the step (b) includes a sputtering method.

  Since the source-drain electrode of the present invention is configured as described above, the Al-based alloy thin film can be directly connected to the semiconductor layer of the thin film transistor. Preferably, the Al-based alloy thin film is further connected to the transparent pixel electrode. Can be connected directly. Therefore, according to the present invention, it is possible to provide an inexpensive and high-performance display device that is excellent in productivity.

  Furthermore, according to the present invention, a sufficiently low electrical resistivity can be ensured even when a relatively low heat treatment temperature of about 200 ° C. is applied. The heat treatment temperature here refers to, for example, the highest processing temperature in the TFT array manufacturing process, and in the general display device manufacturing process, the substrate heating temperature during CVD film formation for various film formation The temperature of the heat treatment furnace when the protective film is thermally cured corresponds to this.

  The present inventor has intensively studied to provide a novel technique capable of directly and reliably connecting an Al-based alloy thin film for a source-drain electrode to a semiconductor layer of a thin film transistor. As a result, when an Al-based alloy containing 0.1 to 6.0 atomic percent of Ni (hereinafter sometimes referred to as an Al-Ni alloy) is used as the source-drain electrode, the Al-Ni alloy and the thin film transistor are used. The present invention was completed by finding that the intended purpose can be achieved because interdiffusion of Al and silicon at the interface with the semiconductor layer can be prevented. According to the present invention, not only the above-described lower barrier metal layer can be omitted, but also the upper barrier metal layer can be omitted, so that the thin film of the Al—Ni alloy can be directly connected to the semiconductor layer of the thin film transistor. The transparent pixel electrode can also be directly connected.

  In this specification, the “source-drain electrode” includes both the source-drain electrode itself and the source-drain wiring. That is, the source-drain electrode of the present invention is formed by integrally forming the source-drain electrode and the source-drain wiring, and the source-drain wiring is in contact with the source-drain electrode.

  Before describing the configuration of the present invention in detail, the background to the present invention will be described based on the technique of Patent Document 4 described above.

  The inventor has conducted research to improve the characteristics and productivity of wiring materials used in liquid crystal display devices.

  First, the present inventor has focused on transparent pixel electrode wiring, and has developed an alloy thin film containing a trace amount of noble metal such as Au or Ag as an alloy component as an Al-based alloy that can be directly connected to the transparent pixel electrode (described above). Patent Document 4). If the Al-based alloy described in Patent Document 4 is used, a conductive precipitate is formed at the interface between the Al-based alloy thin film and the transparent pixel electrode, and most of the contact current flows through the precipitate. As in the prior art, the formation of an Al oxide insulating layer at the interface can be prevented.

  Next, the inventor pays attention to the source-drain wiring, and provides an Al-based alloy that can be directly connected to the semiconductor layer of the thin film transistor without interposing a barrier metal layer such as Mo on the TFT substrate as in the past. In order to do that, we have been researching further. In order to achieve the above object, unlike the case of Patent Document 4 described above, interdiffusion between silicon and Al (detailed mechanism) at the interface between the Al-based alloy thin film for source-drain wiring and the semiconductor layer of the thin film transistor. Is described later). Based on this point of view, the present inventor has studied many experiments, and as a result, among many alloy elements that can be added to Al, Ni can effectively prevent the above-described mutual diffusion between silicon and Al. The present invention has been found.

  Here, the interdiffusion between silicon and Al at the interface between the Al-based alloy thin film and the semiconductor layer of the thin film transistor (hereinafter sometimes simply referred to as an interface) will be described.

  Conventionally, the reason why the lower barrier metal layer such as Mo is formed under the Al-based alloy thin film connected to the semiconductor layer of the thin film transistor is that the silicon is Al-based mainly by the heat treatment in the TFT film formation process at the interface. This is because it diffuses into the alloy thin film and the electric resistance of the Al-based alloy thin film increases. That is, when silicon enters the inside of the Al-based alloy thin film, silicon precipitates are formed, which are solid-phase grown to form insulating silicon islands, which increases the electrical resistance of the source-drain electrodes. .

  At the interface, the diffusion of Al to the semiconductor layer of the thin film transistor also occurs simultaneously with the diffusion of silicon described above. Al diffused into the semiconductor layer of the thin film transistor compensates for the P carriers doped in the semiconductor layer, and the contact resistance at the interface increases.

  Al diffused in the semiconductor layer of the thin film transistor further diffuses into the silicon depletion layer (the region where the charge becomes zero) to form a defect level, and thus an abnormality in the current flowing through the semiconductor layer is observed. . As a result, in particular, the leakage current (off current) that flows when the TFT switching is turned off increases, and switching becomes impossible. Moreover, the power consumption at the time of OFF will become large.

  Therefore, the present invention and the above-mentioned Patent Document 4 are different in characteristics required for alloy elements that can be added to Al. That is, in Patent Document 4, as a wiring material that can be directly connected to the transparent pixel electrode, an element that can be added to the Al alloy from the viewpoint of preventing oxidation of Al at the interface between the Al-based alloy thin film and the transparent pixel electrode. In contrast, in the present invention, as a source-drain wiring material that can be directly connected to the semiconductor layer of the thin film transistor, Al is prevented from diffusing silicon at the interface between the Al-based alloy thin film and the semiconductor layer. The elements that can be added to the alloy are specified, and both have different characteristics required for the wiring material.

  Next, the Al—Ni alloy used in the present invention will be described.

  As described above, in the present invention, an Al alloy containing 0.1 to 6 atomic% of Ni is used as the source-drain electrode. Thereby, at a relatively low heat treatment temperature, a Ni-containing precipitate or a Ni-enriched layer that prevents diffusion of silicon or Al at the interface can be formed at the contact interface between the Al—Ni alloy and the semiconductor layer of the thin film transistor. The off-state current can be reduced (see the examples described later).

  Here, the “Ni-containing precipitate” refers to an intermetallic compound of Al and Ni contained in the Al—Ni alloy, a silicide of Ni contained in the Al—Ni alloy and Si contained in the semiconductor layer of the thin film transistor. Alternatively, it means a silicon compound and at least one compound selected from the group consisting of an intermetallic compound of Al, Ni contained in the Al—Ni alloy, and Si contained in the semiconductor layer of the thin film transistor.

  The “Ni concentrated layer” is present at the interface between the Al—Ni alloy thin film and the semiconductor layer of the thin film transistor, and the average Ni concentration in the Ni concentrated layer is the same as that in the Al—Ni alloy. The average Ni concentration is 2 times or more (preferably 2.5 times or more). The preferred thickness of the Ni concentrated layer is 0.5 nm or more, more preferably 1.0 nm or more and 10 nm or less, more preferably 5 nm or less.

  As shown in the examples described later, when Ni is less than 0.1 atomic%, diffusion of silicon and Al at the interface between the Al—Ni alloy and the amorphous silicon thin film cannot be effectively prevented. However, if the Ni content exceeds 6 atomic%, the electrical resistance of the Al—Ni alloy thin film becomes high, the response speed of the pixel becomes slow, the power consumption increases, the quality of the display decreases, and it becomes practical. It cannot be used. The above range was determined in consideration of these advantages and disadvantages. The Ni content is preferably 0.3 atomic percent or more and 5 atomic percent or less, and more preferably 0.5 atomic percent or more.

  The Al—Ni alloy used in the present invention is further selected as an alloy component from the group consisting of Ti, V, Zr, Nb, Mo, Hf, Ta, and W (hereinafter sometimes referred to as group α). It is preferable to contain 0.1 to 1.0 atomic% of at least one element. Thus, by using an Al—Ni alloy containing an element belonging to group α (hereinafter sometimes referred to as “Al—Ni—α alloy”), the above-described interdiffusion prevention effect between silicon and aluminum is further exhibited. In addition, it is possible to effectively prevent hillocks (cove-like projections) from being formed on the surface of the Al-based alloy thin film. When the content of the element belonging to the group α is less than 0.1 atomic%, the above action cannot be exhibited effectively. On the other hand, when the content of the element belonging to the group α exceeds 1.0 atomic%, the above effect is improved, but the electrical resistivity with respect to the film material is increased. Considering these two aspects, the content of the element belonging to the group α is preferably 0.2 atomic% or more and 0.8 atomic% or less. These elements may be added alone or in combination of two or more. When two or more elements are added, the total content of each element only needs to satisfy the above range.

  Alternatively, the Al—Ni alloy used in the present invention further includes Mg, Cr, Mn, Ru, Rh, Pd, Ir, Pt, La, Gd, Tb, Dy, Nd, Y, Co, and Fe as alloy components. It is preferable to contain 0.1 to 2.0 atomic% of at least one element selected from the group consisting of, Ce, and Pr (hereinafter sometimes referred to as group β). Thus, by using an Al—Ni alloy containing an element belonging to group β (hereinafter sometimes referred to as an Al—Ni—β alloy), the above-described action of preventing mutual diffusion between silicon and aluminum is further exhibited. In addition, it is possible to effectively prevent hillocks (cove-like projections) from being formed on the surface of the Al-based alloy thin film. When the content of the element belonging to the group β is less than 0.1 atomic%, the above action is not effectively exhibited. However, when the content of the element belonging to the group β exceeds 2.0 atomic%, the above effect is improved, but the electrical resistivity with respect to the film material is increased. Considering these two aspects, the content of elements belonging to group β is preferably 0.3 atomic% or more and 1.8 atomic% or less. These elements may be added alone or in combination of two or more. When two or more elements are added, the total content of each element only needs to satisfy the above range.

  In the present invention, an Al—Ni—α-β alloy obtained by adding both the group α element and the group β element to the Al—Ni alloy can also be used.

  Here, the reason why hillocks are formed will be described.

  Hillock is a heat treatment (generally about 300 ° C. to 400 ° C.) applied when forming a silicon nitride film (protective film) after forming a pure Al or Al—Nd alloy thin film in the TFT substrate manufacturing process. It is thought that it is formed by. That is, the substrate on which the Al-based alloy thin film is formed is then formed with a silicon nitride film (protective film) by a CVD method or the like. At this time, the glass substrate and the glass substrate are heated by high temperature heat applied to the Al-based alloy thin film. It is presumed that a difference in thermal expansion occurs during this period and hillocks are formed.

  As described above, the elements belonging to the groups α and β are all selected from the viewpoints of heat resistance and the effect of reducing the electrical resistivity. And slightly different. Hereinafter, this will be described in detail with reference to FIG.

  FIG. 12 is a diagram schematically illustrating the relationship between the temperature and stress (stress) of the Al thin film. In FIG. 12, “A” is pure Al, “B” is an Al—β alloy to which an element belonging to group β is added, “C” is an Al—α alloy to which an element belonging to group α is added, Each is shown.

  As shown in FIG. 12, in the Al-β alloy film “B” to which an element belonging to the group β is added, the compressive stress increases as the temperature rises. Although the grain growth suppression effect is exhibited at the initial stage of the temperature rise, the grain growth starts at a relatively low temperature, and the stress is relieved rapidly in a narrow temperature range. At this time, it is considered that the solid solution element contained in the alloy precipitates as an intermetallic compound in a short time, and the grain growth of Al proceeds accordingly, and the electrical resistivity decreases. That is, a sufficient reduction in electrical resistivity is achieved at a relatively low heating temperature. On the other hand, when further heating is performed in a state where stress is completely relieved, crystal grains are pushed out by the compressive stress generated inside the thin film, and hillocks and the like are likely to occur. The heat-resistant temperature of the alloy is considered to be around the temperature at which this stress is relieved.

  On the other hand, the Al-α alloy film to which an element belonging to the group α is added also increases the compressive stress as the temperature rises similarly to the Al-β alloy film, and Al grain growth starts in the same temperature range as described above. . However, as shown in FIG. 12, the element belonging to group α diffuses from the solid solution state and precipitates as an intermetallic compound relatively slowly, and the intermetallic compound gradually precipitates in a wide temperature range. With this, stress is gradually relieved. Therefore, until the stress is sufficiently relaxed and most of the solid solution elements precipitate as intermetallic compounds, and at the same time, the grain growth of Al proceeds and the electrical conductivity of the film base material is sufficiently reduced. Heating and time are required, and heat resistance increases accordingly. That is, the element belonging to the group α is considered to have a higher effect of improving the heat resistance by the delay of the precipitation of the intermetallic compound as compared with the element belonging to the group β. Sufficient heat resistance improvement effect can be obtained.

  As described above, the elements belonging to the group α and the group β have different heat resistance mechanisms, and therefore the addition amount (upper limit) is also different.

  As for the contact resistivity, the element belonging to the group α can reduce the contact resistivity to the reference value level even if the addition amount is smaller than that of the element belonging to the group β. Such an effect was similarly observed even when the treatment was performed at a relatively low heating temperature.

  Moreover, the element belonging to the group α has a feature that the amount of addition cannot be increased much compared with the element belonging to the group β, but voids (holes) are hardly generated in the electrode film. That is, when an element in which an intermetallic compound precipitates at a stretch in a narrow temperature range at the time of heating, such as an element belonging to group β, the stronger the tensile stress in the film when the temperature drops to room temperature after heating as the grain growth progresses. May cause voids. However, in an alloy system in which intermetallic compounds gradually precipitate with time, such as elements belonging to group β, precipitation and grain growth are interrupted when heated to the same temperature range as group β. Does not proceed sufficiently, and the tensile stress remaining in the film when the temperature is subsequently lowered to room temperature is reduced. Based on the viewpoint of preventing generation of voids due to tensile stress, it is preferable to select an element belonging to group α.

  These Al—Ni alloy thin films are preferably formed by vapor deposition or sputtering, and more preferably by sputtering.

  The aforementioned Al—Ni alloy thin film for source-drain wiring is preferably directly connected to the transparent pixel electrode, and such a TFT substrate is also included in the scope of the present invention.

Here, it is preferable to have AlOx (0 <x ≦ 0.8) at the interface between the Al—Ni alloy thin film and the transparent pixel electrode. By forming such a conductive oxide at the interface, the contact resistivity at the interface can be reduced to about 8 × 10 ⁻⁵ Ω · cm ² or less.

  The thickness of the AlOx is preferably in the range of 1 to 10 nm, more preferably in the range of 2 to 8 nm, and most preferably about 5 nm.

Incidentally, in the conventional method, pure Al, Al—Nd alloy or the like is in direct contact with the transparent conductive film, so that the contact resistance is high and non-ohmic contact is obtained. The reason is that the aluminum oxide layer formed at the contact interface becomes a high-resistance film containing almost the same amount of oxygen as the stoichiometric composition of Al oxide (Al ₂ O ₃ ), and the aluminum oxide layer is also thick. It seems to be because.

  Specifically, such a conductive oxide film (AlOx) is formed using, for example, the following method. First, the substrate temperature is preferably set in a range of 100 to 200 ° C., and a film having a thickness of 5 to 20 nm (preferably about 10 nm) is formed using a non-oxidizing gas such as argon. During this period, that is, at the initial stage of forming the ITO film constituting the transparent pixel electrode, the film is formed in an oxygen-free atmosphere so as not to oxidize the surface of the Al—Ni alloy thin film as much as possible. Note that when film formation is performed in an oxygen-free atmosphere, the oxygen content in the ITO film formed by the sputtering method decreases, and the conductivity of the ITO film itself decreases. However, at this time, if the substrate is appropriately heated, the crystallinity of the ITO is increased, and the decrease in the conductivity as the ITO film can be compensated.

Next, while maintaining the temperature of the substrate, the atmospheric gas is changed from a non-oxidizing gas to an oxygen-containing gas in which oxygen is mixed in the non-oxidizing gas, and has a thickness of about 20 to 200 nm (preferably around 40 nm). ). At this time, the amount of oxygen added to the atmospheric gas is not particularly limited. As a typical condition, for example, oxygen is controlled to 10 to 50 μTorr (preferably about 20 μTorr) with respect to about 1 to 5 mTorr (preferably about 3 mTorr). It is preferable to do. It has been confirmed by experiments that the electrical resistivity of the formed ITO film is the lowest when such conditions are adopted and is about 1 × 10 ⁻⁴ Ω · cm ² or less. The same effect can be obtained by adding water vapor instead of adding oxygen. Thus, by forming the ITO film by sputtering in two stages (or multiple stages) by changing the oxygen content of the atmospheric gas, while suppressing the oxidation of the Al alloy film at the initial stage of ITO film formation, The film itself can ensure a sufficiently high conductivity.

Furthermore, a Ni concentrated layer exists at the interface between the Al—Ni alloy thin film and the transparent pixel electrode, and the average Ni concentration in the Ni concentrated layer is at least twice the average Ni concentration in the Al—Ni alloy ( More preferably, it is 2.5 times or more. Thereby, the contact resistivity of the interface can be further reduced to about 8 × 10 ⁻⁵ Ω · cm ² or less. The thickness of the Ni concentrated layer is preferably 0.5 nm or more and 10 nm or less, and more preferably 1.0 nm or more and 5 nm or less.

  When a liquid crystal display device was prototyped using the Al-Ni alloy thin film described above, as shown in the examples described later, the same level as in the case of using a conventional Al alloy thin film with a barrier metal layer such as Mo interposed therebetween. It was confirmed that the above TFT characteristics can be realized. Therefore, according to the present invention, the manufacturing process can be simplified by omitting the barrier metal layer, and the manufacturing cost can be reduced. Moreover, according to the present invention, a sufficiently low electrical resistivity can be achieved at a relatively low thermal process temperature of about 200 ° C., so that the range of selection of display device constituent materials and processing conditions can be further expanded. It becomes possible.

  Hereinafter, preferred embodiments of a TFT substrate according to the present invention will be described with reference to the drawings. In the following, a liquid crystal display device having an amorphous silicon TFT substrate will be described as a representative example. However, the present invention is not limited to this, and is implemented with appropriate modifications within a range that can meet the purpose described above and below. Any of these may be included in the technical scope of the present invention. Experiments have been made that the Al—Ni alloy thin film used in the present invention can be similarly applied to, for example, a reflective electrode such as a reflective liquid crystal display device and a TAB (tab) connection electrode used for signal input / output to the outside. It is confirmed by.

(Embodiment 1)
The embodiment of the amorphous silicon TFT substrate will be described in detail with reference to FIG.

  FIG. 3 is a schematic cross-sectional explanatory view for explaining a preferred embodiment of a TFT substrate according to the present invention. In FIG. 3, the same reference numerals as those in FIG.

  As is clear from comparison between FIG. 2 and FIG. 3, in the conventional TFT substrate, as shown in FIG. 2, a barrier metal layer (lower barrier metal layer) 53 such as Mo is formed under the source-drain electrodes. In contrast, in the TFT substrate of the present invention, the lower barrier metal layer 53 can be omitted. According to the present embodiment, the source-drain wiring can be directly connected to the amorphous silicon thin film without interposing a lower barrier metal layer as in the prior art, and this also is equivalent to or more than that of the conventional TFT substrate. Good TFT characteristics can be realized (see Examples 1 and 2 described later).

  Although FIG. 3 shows an embodiment in which the upper barrier metal layer 54 is formed on the source-drain wiring, the upper barrier metal layer 54 can be omitted as shown in the second embodiment to be described later.

  Further, in the TFT substrate shown in FIG. 3, the barrier metal layers 51 and 52 formed on the scanning line 25 and the gate electrode 26, respectively, can be omitted.

  Therefore, according to the present invention, it is possible to omit all the barrier metal layers that are indispensable for the wiring material.

  Next, a manufacturing method of the TFT substrate according to the present invention shown in FIG. 3 will be described with reference to FIG. Here, an Al—Ni alloy containing 2.0 atomic% Ni is used as the source-drain electrode. 4, the same reference numerals as those in FIG. 3 are given.

  First, an Al alloy thin film (Al-2.0 atomic% Nd) having a thickness of about 250 nm and a Mo thin film 52 having a thickness of about 50 nm are sequentially laminated on the glass substrate 1a by sputtering. The film formation temperature for sputtering was room temperature. By patterning the laminated thin film, the gate electrode 26 and the scanning line 25 are formed (FIG. 4A). At this time, in the step shown in FIG. 4B, which will be described later, the periphery of the laminated thin film is etched into a taper of about 30 ° to 60 ° so that the coverage of the gate insulating film 27 is improved. Good.

Next, as shown in FIG. 4B, a silicon nitride film (gate insulating film) 27 having a thickness of about 300 nm is formed by using a method such as plasma CVD. The film formation temperature of the plasma CVD method was about 350 ° C. Subsequently, a non-doped hydrogenated amorphous silicon film (a-Si-H) 55 having a thickness of about 200 nm and a thickness of about 80 nm are formed on the silicon nitride film (gate insulating film) 27 by using, for example, a plasma CVD method. An n ⁺ -type hydrogenated amorphous silicon film (n ⁺ a-Si-H) 56 doped with phosphorus is sequentially stacked. The n ⁺ -type hydrogenated amorphous silicon film is formed, for example, by performing a plasma CVD method in which PH ₃ gas is added at a predetermined partial pressure.

The hydrogenated amorphous silicon film 55 and the n ⁺ type hydrogenated amorphous silicon film 56 thus formed are patterned as shown in FIG.

  Next, as shown in FIG. 4D, an Al-2.0 atomic% Ni alloy film having a thickness of about 300 nm and a Mo film 53 having a thickness of about 50 nm are sequentially stacked using a sputtering method. The film formation temperature for sputtering was room temperature. According to the present embodiment, an off current substantially equal to that obtained when the lower barrier metal layer is interposed can be realized without interposing the lower barrier metal layer of Mo under the amorphous silicon thin film as in the prior art. be able to. In this embodiment, the Mo film 53 is laminated on the Al-2.0 atomic% Ni alloy film, but the Mo film 53 can be omitted as shown in Example 2 described later.

By patterning such a laminated thin film, the source electrode 28 integrated with the signal line and the drain electrode 29 are formed (FIG. 4D). Further, using the source electrode 28 and the drain electrode 29 as a mask, the n ⁺ type hydrogenated amorphous silicon film 56 is removed by dry etching (FIG. 4D).

  Then, as shown in FIG. 4E, a silicon nitride film (protective film) 30 having a thickness of about 300 nm is formed using, for example, a plasma CVD apparatus. The film formation at this time was performed at about 200 ° C. Next, the contact hole 57 is formed by performing dry etching or the like on the silicon nitride film 30.

  Next, after passing through an ashing process using, for example, oxygen plasma, the photoresist layer (not shown) is stripped using, for example, an amine-based stripping solution. Finally, as shown in FIG. 4F, an ITO film (adding 10% by mass of tin oxide to indium oxide) having a thickness of about 50 nm is formed. Next, when the transparent pixel electrode 5 is formed by performing patterning by wet etching, the TFT substrate is completed.

  In the above description, an ITO film is used as the transparent pixel electrode 5, but an IZO film may be used. Further, polysilicon may be used as the active semiconductor layer instead of amorphous silicon.

  Using the TFT substrate thus obtained, for example, the liquid crystal display device shown in FIG. 1 is completed by the method described below.

  First, for example, polyimide is applied to the surface of the TFT substrate 1 manufactured as described above and dried, and then a rubbing process is performed to form an alignment film.

  On the other hand, the counter substrate 2 forms a light shielding film 9 on a glass substrate by patterning, for example, chromium in a matrix. Next, resin-made red, green, and blue color filters 8 are formed in the gaps between the light shielding films 9. A counter electrode is formed by disposing a transparent conductive film such as an ITO film as the common electrode 7 on the light shielding film 9 and the color filter 8. Then, for example, polyimide is applied to the uppermost layer of the counter electrode, and after drying, a rubbing process is performed to form the alignment film 11.

  Next, the TFT substrate 1 and the surface of the counter substrate 2 on which the alignment film 11 is formed are arranged so as to oppose each other, and the TFT substrate 1 is opposed to the TFT substrate 1 by a sealing material 16 made of resin, excluding the liquid crystal sealing port. The 22 substrates are bonded together. At this time, a gap between the two substrates is kept substantially constant by interposing a spacer 15 between the TFT substrate 1 and the counter substrate 2.

  By placing the empty cell thus obtained in a vacuum and gradually returning it to atmospheric pressure with the sealing port immersed in liquid crystal, a liquid crystal material containing liquid crystal molecules is injected into the empty cell to form a liquid crystal layer. Form and seal the sealing port. Finally, polarizing plates 10 are attached to both sides of the empty cell to complete the liquid crystal panel.

  Next, as shown in FIG. 1, a driver circuit 13 for driving the liquid crystal display device is electrically connected to the liquid crystal panel and disposed on the side portion or the back surface portion of the liquid crystal panel. Then, the liquid crystal panel is held by the holding frame 23 including the opening serving as the display surface of the liquid crystal panel, the backlight 22 serving as the surface light source, the light guide plate 20, and the holding frame 23, thereby completing the liquid crystal display device.

(Embodiment 2)
The TFT substrate of Embodiment 2 is the same as that of Embodiment 1 described above in that both the upper barrier metal layer 54 and the lower barrier metal layer 53 are omitted from the TFT substrate shown in FIG. Only the TFT substrate is omitted. Other configurations are the same.

  In the TFT substrate of this embodiment, in Embodiment 1, only an Al-based alloy thin film (Al-2, 0 atomic% Nd) having a thickness of about 300 nm was formed on the glass substrate 1a, and Mo was not formed. Except for the above, it can be manufactured by the same method as in the first embodiment. According to this embodiment, the Al—Ni alloy thin film is directly connected to the amorphous silicon thin film and also directly connected to the transparent pixel electrode. As described above, according to the present embodiment, not only the barrier metal layer on the wiring connected to the transparent pixel electrode can be omitted, but also excellent TFT characteristics equivalent to or higher than those of the conventional TFT substrate can be realized (described later). See Examples 3 to 4).

Example 1
In Example 1 and Example 2 to be described later, various experiments were conducted for the purpose of confirming that excellent TFT characteristics can be obtained even if the lower barrier metal layer is omitted by using the TFT substrate of Embodiment 1 described above. went. In all of these examples, an Al-2.0 atomic% Ni alloy is used as the source-drain electrode, and will be abbreviated as an Al-Ni alloy thin film hereinafter.

  In this example and the examples described later, the amount of Ni is determined by GD-OES (glow discharge emission spectroscopy), and the thicknesses of the Ni concentrated layer and the Al oxide film are determined by cross-sectional TEM observation. The content and the oxygen content in the Al oxide film were examined by analyzing the composition of the cross-sectional TEM observation sample by EDX.

(Observation near the interface between amorphous silicon thin film and Al-Ni alloy thin film)
First, according to the present invention, a Ni-concentrated layer having excellent conductivity is formed near the interface between an amorphous silicon thin film and an Al—Ni alloy thin film for source-drain electrodes. Examined.

  First, the situation in the vicinity of the interface immediately after forming an Al—Ni alloy on an amorphous silicon thin film at room temperature was examined. FIG. 5A is a cross-sectional TEM photograph of the interface, and FIG. 5B is a HAADF-STEM (high angle dark field scanning electron microscope) image at the same observation position as the TEM photograph. The TEM photograph shows the composition of the interface, and the HAADF-STEM shows the Ni distribution state.

  As shown in FIG. 5A, it can be seen that the Al—Ni alloy thin film has columnar crystal grain boundaries. As a result of analyzing the interface by EDX (energy dispersive X-ray spectroscopy), interdiffusion between Si and Al was not observed.

  In FIG. 5B, the portion that glows white (the arrow portion in the figure) is Ni. That is, immediately after depositing the Al—Ni alloy on the amorphous silicon thin film, enrichment of Ni was already observed on the Al—Ni alloy thin film side of the interface.

  Next, the situation in the vicinity of the interface between the amorphous silicon thin film and the Al—Ni alloy thin film when all the TFT manufacturing steps were completed was similarly examined. FIG. 6A is a cross-sectional TEM photograph of the interface, and FIG. 6B is a photograph showing a HAADF-STEM image at the same observation position as the TEM photograph.

  As described above, when the TFT substrate of this embodiment is manufactured, various film forming steps are performed even after the Al—Ni alloy is formed on the amorphous silicon thin film. The step of forming is a step of forming a silicon nitride film (protective film), and heat treatment is performed at 200 ° C. for 20 minutes including preheating.

  As shown in FIG. 6A, according to the present embodiment, it was found that Ni maintained columnar crystal grain boundaries at the interface even after such a film forming step. Furthermore, the interface between the amorphous silicon thin film and the Al—Ni alloy thin film was kept flat as in FIG. 5A described above, and no interdiffusion between silicon and Al was observed even by analysis by EDX.

  Moreover, as shown to FIG. 6B, it turns out that the precipitate and intermetallic compound which contain Ni are formed in the said interface.

  Furthermore, the Ni concentration distribution in the vicinity of the interface between the amorphous silicon thin film and the Al—Ni alloy thin film when all the TFT manufacturing processes were completed was examined using GD-OES (glow discharge emission spectroscopy). In GD-OES, the concentration of the element is measured by measuring the intrinsic light emission of the sputtered element using the sputtering phenomenon caused by Ar glow discharge. Here, the sputter region was 3 mmφ, and the average Ni concentration in the surface space at 3 mmφ was examined. The result is shown in FIG.

  For comparison, the Ni concentration distribution near the interface immediately after forming an Al—Ni alloy on an amorphous silicon thin film at room temperature was examined in the same manner as described above. The result is shown in FIG.

As is clear from the comparison between FIG. 7A and FIG. 7B, the Ni concentration near the interface was almost constant immediately after the Al—Ni alloy thin film was formed. After completing all the film forming steps, formation of a Ni concentrated layer was observed in the vicinity of the interface. This result is consistent with the result of the HAADF-STEM image shown in FIG. 6B described above, and the Ni concentrated layer is probably precipitated in the form of an intermetallic compound of Al ₃ Ni. Specifically, such a Ni concentrated layer is formed within a range of about 50 nm or less on the interface side of the Al—Ni alloy thin film, and the maximum value of Ni amount is about 4.0 atomic%.

(TFT characteristics)
Next, the switching characteristics of the drain current-gate voltage of the TFT on the TFT substrate in this embodiment were examined. This also makes it possible to evaluate the diffusion of Al into the amorphous silicon thin film. Here, the amount of change in leakage current (drain current value when a negative voltage is applied to the gate voltage, that is, off-current) that flows when TFT switching is turned off, and the threshold value that flows when TFT switching is turned on (gate voltage) Value) was measured as follows.

Using a TFT having a gate length (L) of 3 μm, a gate width (W) of 30 μm, and a W / L ratio of 10, a drain current and a gate voltage were measured. The drain voltage at the time of measurement was 10V. The off-current was defined as the current when a gate voltage (−5 V) was applied, and the threshold was defined as the gate voltage when the drain current was 10 ⁻⁸ A.

The off-state current is evaluated by off-state current (3 × 10 ⁻¹² A) when a conventional source-drain wiring (laminated wiring in which a Mo barrier metal layer is formed on and below the Al—Nd alloy, respectively) is used. ) As a reference value, a value within one digit increase range (3 × 10 ⁻¹¹ A) with respect to the reference value was determined to be good, and a value exceeding the above range was determined to be defective.

As a result, the off-current of the TFT is 5 × 10 ⁻¹² A, and the conventional source-drain wiring (laminated wiring in which a barrier metal layer of Mo is formed on and below the Al—Nd alloy, respectively) is used. It was almost the same as the off-state current (3 × 10 ⁻¹² A). Further, the threshold value of the TFT was 0.45 V, which was the same as the value (0.45 V) when using the above-described conventional laminated wiring.

  From the above results, it is confirmed that the TFT substrate of this embodiment can achieve the same TFT characteristics as the TFT substrate formed using the conventional source-drain wiring even if the lower barrier metal layer is omitted. It was done.

(Comparative example)
For comparison, a TFT substrate was fabricated in the same manner as in Embodiment 1 except that pure Al was used instead of the Al-2.0 atomic% Ni alloy as the source-drain wiring in Embodiment 1 described above. . Next, in the same manner as in Example 1 described above, the vicinity of the interface between the amorphous silicon thin film and the pure Al thin film for source-drain electrodes was observed with a TEM.

  First, the situation in the vicinity of the interface immediately after depositing pure Al at room temperature on an amorphous silicon thin film was examined. FIG. 8A is a TEM photograph showing a cross section of the interface, and FIG. 8B is a TEM photograph showing a cross section of the interface when the magnification is increased. FIG. 8B also shows the results of EDX analysis.

  As shown in FIGS. 8A and 8B, the pure Al thin film has irregular crystal grain boundaries. When the interface was analyzed by EDX, the presence of about 10 atomic% Al was confirmed over the amorphous silicon side of the interface near 10 nm. That is, according to this comparative example, Al diffusion was already observed at the interface immediately after the pure Al alloy was formed on the amorphous silicon thin film.

  Next, the situation in the vicinity of the interface between the amorphous silicon thin film and the pure Al thin film when all the TFT manufacturing processes were completed was similarly examined. FIG. 9A is a TEM photograph showing a cross section of the interface, and FIG. 9B is a mapping image (Si map and Al map) when the same observation position as the TEM photograph is analyzed by EDX.

  As shown in FIG. 9A, according to this comparative example, after all the film forming steps, Al diffusion further proceeds, and Al and Si are interdiffused near the interface. I understand.

  Specifically, as is apparent from the Si map and the Al map in FIG. 9B, Al diffuses over the vicinity of 100 nm on the amorphous silicon side of the interface, and Si diffuses over about 250 nm on the pure Al side of the interface. Was confirmed.

Further, the TFT characteristics of the comparative example were examined in the same manner as in Example 1 described above. As a result, the off-current of the TFT was 1 × 10 ⁻⁸ A, which was significantly higher than the off-current (3 × 10 ⁻¹² A) when using the conventional multilayer wiring. Similarly, the threshold value of the TFT is 2.5 V, which is significantly higher than the value (0.45 V) when the conventional laminated wiring is used.

  From the above results, it was found that when pure Al was used as the source-drain wiring, the TFT switching characteristics did not function at all when the lower barrier metal layer was omitted and the TFT was fabricated. Therefore, it was confirmed that the formation of the barrier metal layer is indispensable when a TFT is manufactured using pure Al.

(Example 2)
In this example, various Al—Ni alloys in which the amount of Ni added to the Al alloy was changed within the range shown in Table 1 were used, and TFT characteristics (off current and threshold value) were the same as in Example 1 described above. The amount of each change) was measured. Furthermore, an Al-2.0 atomic% Ni-La alloy or an Al-2.0 atomic% Ni- in which La or Nd is added as a third component in the range shown in Table 1 with respect to Al-2.0 atomic% Ni. TFT characteristics were similarly investigated using Nd alloy or Al-0.1 atomic% Ni-La alloy in which La was added in the range shown in Table 1 with respect to Al-0.1 atomic% Ni. .

  For comparison, TFT characteristics when pure Al, Mo, and Al-1 atomic% Si were used instead of the Al—Ni alloy were similarly measured.

The off-state current is evaluated by off-state current (3 × 10 ⁻¹² A) when a conventional source-drain wiring (laminated wiring in which a Mo barrier metal layer is formed on and below the Al—Nd alloy, respectively) is used. ) As a reference value, a value within one digit increase range (3 × 10 ⁻¹¹ A) with respect to the reference value was determined to be good, and a value exceeding the above range was determined to be defective.

  In addition, in the evaluation of the threshold value, a value included in a range of ± 0.2 V with respect to the threshold value of Mo was regarded as good, and a value exceeding the above range was regarded as defective.

  For TFT characteristics, the off-state current and the threshold value evaluated in this way are comprehensively judged, and “○” indicates that all the characteristics are good, and any of the characteristics is bad or any of the characteristics is bad. Was evaluated as “×”.

(Heat-resistant)
Furthermore, the heat resistance of the pure Al and various Al alloys used in this example was evaluated as follows.

First, a sample of the pure Al film or Al alloy film having a thickness of about 200 nm was prepared on a glass substrate by sputtering. A 10 μm wide line and space pattern was formed on these samples. Next, these samples were subjected to heat treatment at 200 ° C. × 1 hour or 300 ° C. × 1 hour under a vacuum of 1 × 10 ⁻³ Torr or less, respectively, and the change of the thin film surface was observed with an optical microscope (400 × magnification). Observed at. The occurrence of hillocks exceeding 1 × 10 ⁹ / m ² was designated as “x”, and the others were designated as “◯”.

  These results are summarized in Table 1.

  From Table 1, it is understood that good TFT characteristics can be obtained by adding 0.1 atomic% or more of Ni to the Al alloy.

  In addition, when Al is added within a range of 0.1 atomic% to 2.0 atomic% or Nd within a range of 0.1 atomic% to 1.0 atomic% with respect to Al-2.0 atomic% Ni, it is favorable. In addition to obtaining excellent TFT characteristics, the heat resistance was also improved. A similar tendency was observed when La was added to Al-0.1 atomic% Ni.

  On the other hand, when pure Al, Mo, and Al-1 atomic% Si were used, the TFT characteristics and the heat resistance were significantly lowered.

(Example 3)
In Example 3 and Example 4 to be described later, it is confirmed that excellent TFT characteristics can be obtained even if both the lower barrier metal layer and the upper barrier metal layer are omitted by using the TFT substrate of Embodiment 2 described above. For the purpose, the following experiment was conducted.

(TFT characteristics)
First, using the TFT, the TFT characteristics were examined in the same manner as in Example 1 described above. As a result, the off-current of the TFT was 4 × 10 ⁻¹² A, which was almost the same as the off-current (3 × 10 ⁻¹² A) when using the conventional source-drain wiring. Further, the threshold value of the TFT was 0.45 V, which was the same as the value (0.45 V) when using the above-described conventional laminated wiring.

  Next, the direct contact resistance (contact resistance) when the Al-2.0 atomic% Ni alloy thin film was directly connected to the transparent pixel electrode was measured by the following method.

1) Transparent pixel electrode: Indium tin oxide (ITO) obtained by adding 10% by mass of tin oxide to indium oxide was used.
2) Thin film formation conditions: atmospheric gas = argon, pressure = 3 mTorr, thickness = 200 nm,
3) Heating conditions: 200 ° C. × 20 minutes 4) Measuring method of contact resistivity:
A Kelvin pattern (contact hole size: 10 μm square) shown in FIG. 10 is prepared and measured at four terminals [current is passed through the ITO-Al alloy, and the voltage drop between the ITO (or IZO) -Al alloy is measured at another terminal. Method] was performed. That is, by passing the current I between I _{1 and} I ₂ in FIG. 10 and monitoring the voltage V between V _{1 and} V ₂ , the direct contact resistivity R of the contact portion C is set to [R = (V ₂ −V ₁ ) / I ₂ ]. Contact resistivity is Cr thin film and ITO
Contact resistance (2 × 10 ⁻⁴ Ω · cm ² or less) as a reference value, a value within the range of the reference value is good (◯), and a value exceeding the reference value is defective (×) .

As a result, the contact resistivity was 8 × 10 ⁻⁵ Ω · cm ² or less, and it was found that the TFT had good TFT characteristics.

(Observation near the interface between ITO film (transparent pixel electrode) and Al-Ni alloy thin film)
Next, the interface between the ITO film and the Al—Ni alloy thin film was observed with a cross-sectional TEM, and the composition analysis was performed with EDX. The result is shown in FIG.

  From FIG. 11, it is understood that a conductive layer of about 5 nm of Al oxide (AlOx) is formed at the interface. Further, a Ni concentrated layer (Ni content is about 8 atomic%) having a thickness of about 1 nm was formed at the interface between the AlOx conductive layer and the bulk Al—Ni alloy thin film. This is because Al diffuses in the direction of the oxide film as the oxidation of Al progresses, Ni diffuses in the bulk direction, and Ni tends to remain as a residue when dry etching a contact hole. Conceivable. When the Ni concentrated layer is formed by these influences, the diffusion of Al ions from the Al alloy bulk is suppressed, and the effect of suppressing the oxidation of Al is expected.

Example 4
In this example, various Al—Ni alloys in which the amount of Ni added to the Al alloy was changed within the range shown in Table 2 were used, and the TFT characteristics (off current and threshold value) were the same as in Example 3 described above. The amount of each change) was measured. Further, an Al-2.0 atomic% Ni-La alloy or an Al-2.0 atomic% Ni- in which La or Nd is added as a third component in the range shown in Table 2 with respect to Al-2.0 atomic% Ni. TFT characteristics were similarly examined using an Al-0.1 atomic% Ni-La alloy in which La was added in the range shown in Table 2 with respect to Nd alloy or Al-0.1 atomic% Ni. .

  For comparison, TFT characteristics when pure Al, Mo, and Al-1 atomic% Si were used instead of the Al—Ni alloy were similarly measured. The evaluation criteria for the off-current are the same as those in Example 2 described above. These results are summarized in Table 2.

  From Table 2, it is understood that good TFT characteristics can be obtained by adding 0.1 atomic% or more of Ni to the Al alloy.

  Further, when Al is added within a range of 0.1 atomic% to 2.0 atomic% or Nd within a range of 0.1 atomic% to 1.0 atomic% with respect to Al-2.0 atomic% Ni, Also, good TFT characteristics were obtained. A similar tendency was observed when La was added to Al-0.1 atomic% Ni.

  On the other hand, when pure Al, Mo, and Al-1 atomic% Si were used, the TFT characteristics were remarkably deteriorated.

FIG. 1 is a schematic enlarged cross-sectional view illustrating a configuration of a typical liquid crystal panel to which an amorphous silicon TFT substrate is applied. FIG. 2 is a schematic cross-sectional explanatory view showing a configuration of a conventional typical amorphous silicon TFT substrate. FIG. 3 is a schematic cross-sectional explanatory view showing the configuration of the TFT substrate according to the first embodiment of the present invention. FIG. 4 is a process diagram showing manufacturing steps of the TFT substrate shown in FIG. FIG. 5A is a cross-sectional TEM photograph of an interface between an Al—Ni alloy thin film and an amorphous silicon thin film immediately after forming an Al—Ni alloy on the amorphous silicon thin film at room temperature in the first embodiment of the present invention. . FIG. 5B is a HAADF-STEM image of the interface between the Al—Ni alloy thin film and the amorphous silicon thin film in the TFT substrate according to the first embodiment of the present invention. FIG. 6A is a cross-sectional TEM photograph of an interface between an Al—Ni alloy thin film and an amorphous silicon thin film in the TFT substrate according to the first embodiment of the present invention. FIG. 6B is a HAADF-STEM image of the interface between the Al—Ni alloy thin film and the amorphous silicon thin film in the TFT substrate according to the first embodiment of the present invention. FIG. 7A shows elements in the vicinity of the interface between the Al—Ni alloy thin film and the amorphous silicon thin film immediately after forming the Al—Ni alloy on the amorphous silicon thin film at room temperature in the first embodiment of the present invention. FIG. 7B is a diagram showing the concentration distribution in the depth direction. FIG. 7B shows the element concentration in the vicinity of the interface between the Al—Ni alloy thin film and the amorphous silicon thin film in the TFT substrate according to the first embodiment of the present invention. It is a figure which shows depth direction distribution. FIG. 8A is a cross-sectional TEM photograph of an interface between an Al—Ni alloy thin film and an amorphous silicon thin film immediately after forming an Al—Ni alloy on the amorphous silicon thin film at room temperature in the second embodiment of the present invention. . FIG. 8B is a HAADF-STEM image of the interface between the Al—Ni alloy thin film and the amorphous silicon thin film in the TFT substrate according to the second embodiment of the present invention. FIG. 9A is a cross-sectional TEM photograph of an interface between an amorphous silicon thin film and a pure Al thin film in the TFT substrate according to the second embodiment of the present invention. FIG. 9B is a mapping image (Si map and Al map) when the same observation position as the TEM photograph shown in FIG. 9A is analyzed by EDX. FIG. 10 is a diagram showing a Kelvin pattern used for measuring the contact resistivity between the Al alloy thin film and the transparent pixel electrode. FIG. 11 is a cross-sectional TEM photograph showing a contact interface between a transparent pixel electrode and an Al—Ni alloy in Example 4. FIG. 12 is a diagram schematically illustrating the relationship between the temperature and stress (stress) of the Al thin film.

Explanation of symbols

1 TFT substrate 2 Counter electrode 3 Liquid crystal layer 4 Thin film transistor (TFT)
DESCRIPTION OF SYMBOLS 5 Transparent pixel electrode 6 Wiring part 7 Common electrode 8 Color filter 9 Light-shielding film 10a, 10b Polarizing plate 11 Orientation film 12 TAB tape 13 Driver circuit 14 Control circuit 15 Spacer 16 Sealing material 17 Protective film 18 Diffusion plate 19 Prism sheet 20 Light guide plate 21 Reflector 22 Backlight 23 Holding Frame 24 Printed Circuit Board 25 Scan Line 26 Gate Electrode 27 Gate Insulating Film (Silicon Nitride Film)
28 Source electrode 29 Drain electrode 30 Protective film (silicon nitride film)
31 Photoresist 32 Contact hole 33 Amorphous silicon channel film (active semiconductor film)
34 Signal line (source-drain wiring)
51, 52, 53, 54 Barrier metal layer 55 Non-doped hydrogenated amorphous silicon film (a-Si-H)
56 n ⁺ type hydrogenated amorphous silicon film (n ⁺ a-Si-H)
100 LCD panel

Claims (15)

It consists of an Al alloy thin film containing 0.1 to 6 atomic% of Ni as an alloy component,
The source-drain electrode, wherein the Al alloy thin film is directly connected to the semiconductor layer of the thin film transistor.   The Al alloy further contains 0.1 to 1.0 atomic% of at least one element selected from the group consisting of Ti, V, Zr, Nb, Mo, Hf, Ta, and W as an alloy component. The source-drain electrode according to claim 1.   The Al alloy further includes Mg, Cr, Mn, Ru, Rh, Pd, Ir, Pt, La, Gd, Tb, Dy, Nd, Y, Co, Fe, Ce, and Pr as alloy components. The source-drain electrode according to claim 1 or 2, which contains at least one element selected from 0.1 to 2.0 atomic%.   The source-drain electrode according to any one of claims 1 to 3, comprising a compound containing Ni at an interface between the thin film of the Al alloy and the semiconductor layer of the thin film transistor.   The compound containing Ni is an intermetallic compound of Al and Ni contained in the Al alloy, a silicide or silicon compound of Ni contained in the Al alloy and Si contained in a semiconductor layer of the thin film transistor, and the Al The source-drain electrode according to claim 4, which is at least one compound selected from the group consisting of an intermetallic compound of Al and Ni contained in an alloy and Si contained in a semiconductor layer of the thin film transistor.   An Ni-concentrated layer is present at the interface between the thin film of the Al alloy and the semiconductor layer of the thin film transistor, and the average Ni concentration in the Ni-concentrated layer is at least twice the average Ni concentration in the Al alloy. Item 6. The source-drain electrode according to any one of Items 1 to 5.   The source-drain electrode according to claim 1, wherein the Al alloy thin film has an electrical resistivity of 8 μΩ · cm or less.   The source-drain electrode according to claim 1, wherein the Al alloy thin film is further directly connected to the transparent pixel electrode.   9. The source-drain electrode according to claim 8, comprising AlOx (0 <x ≦ 0.8) at an interface between the Al alloy thin film and the transparent pixel electrode.   An Ni-enriched layer is present at the interface between the Al alloy thin film and the transparent pixel electrode, and the average Ni concentration in the Ni-enriched layer is at least twice the average Ni concentration in the Al alloy. The source-drain electrode according to 8 or 9.   The source-drain electrode according to claim 1, wherein the transparent pixel electrode is made of indium tin oxide (ITO) or indium zinc oxide (IZO).   A thin film transistor substrate comprising the source-drain electrode according to claim 1.   A display device comprising the thin film transistor substrate according to claim 12. A method of manufacturing the thin film transistor substrate according to claim 12,
A step (a) of preparing a substrate on which a semiconductor layer of a thin film transistor is formed;
Forming a thin film of the Al alloy on the semiconductor layer of the thin film transistor;
And (c) depositing a silicon nitride film on the Al alloy thin film,
The said process (c) is a manufacturing method of a thin-film transistor substrate including the process heated at the temperature of 100 to 300 degreeC.   The method of manufacturing a thin film transistor substrate according to claim 14, wherein the step (b) includes a sputtering method.