JP2007027609A - Light emitting diode array and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a light-emitting diode array high in yield and excellent in mass productivity, and to provide its manufacturing method. <P>SOLUTION: A main face 41a of a substrate made of a GaAs single crystal with a plurality of semiconductor layers laminated thereon is inclined at 1-20° on the (01T) face 72 side or on the (0TT) face 73 side from the (100) face 71. Consequently, it is possible to obtain a face with almost no occurrence of fogging when forming a plurality of the semiconductor layers on the main face 41a of the GaAs substrate 41 by an MOCVD method. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a light-emitting diode array and a manufacturing method thereof, and more particularly to a light-emitting diode array suitable as a light source for an image forming apparatus such as an electrophotographic printer or a copying machine, and a manufacturing method thereof.

  Conventionally, as a light source of an electrophotographic image forming apparatus, a laser method and a light emitting diode array method are mainly used. In particular, the light emitting diode array method does not require a long optical path length unlike the laser method, and is easy to reduce the size of the apparatus and the printing size, so that it is often used as a light source of an image forming apparatus. It is becoming. Recently, a cheaper light emitting diode array has been demanded due to a reduction in the price of image forming apparatuses.

  As such a conventional light emitting diode array, for example, a p-type GaAs layer, a p-type AlGaAs layer, and an n-type AlGaAs are formed on a (100) surface of a semi-insulating GaAs substrate by MOCVD (Metal-Organic Chemical Vapor Deposition) method. A layer and an n-type GaAs layer are sequentially formed, and a plurality of light emitting diodes are divided and formed by mesa etching grooves (see, for example, Patent Document 1).

On the other hand, as a method for growing a GaAs single crystal having a low transition density, a vertical bridgeman (VB) method, a vertical temperature gradient (VGF) method, a liquid encapsulate pulling (LEC) is used. The method is known conventionally (for example, refer patent document 2).
JP 2001-44504 A (paragraph [0032]) JP2003-226594A (paragraph [0002])

  However, when a GaAs substrate is produced by the VB method or VGF method, it is difficult to produce a large GaAs substrate although the density of transition defects is low. On the other hand, when a GaAs substrate is manufactured by the LEC method, a substrate having a semi-insulating property and suitable for upsizing can be manufactured. However, since the dislocation defect density is high, when a crystal layer is formed thereon, There is a problem that cloudiness and pits are generated and the yield of the light emitting diode array is deteriorated.

  Accordingly, an object of the present invention is to provide a light emitting diode array having a high yield and excellent mass productivity and a method for manufacturing the same.

  In one embodiment of the present invention, in order to achieve the above object, a plurality of epitaxial layers are stacked on a main surface of a substrate made of GaAs single crystal, and the plurality of epitaxial layers are divided by mesa etching grooves in a predetermined direction. In a light emitting diode array formed by forming a plurality of light emitting diode portions arranged, the main surface of the substrate is inclined by 1 to 20 degrees from a (100) plane.

  According to the light emitting diode array, when a plurality of epitaxial layers are stacked on a substrate by an epitaxial growth method such as MOVPE (metal organic chemical vapor deposition) method or MOCVD method, cloudiness and pits are not generated, and crystallinity is good. An epitaxial layer can be obtained.

  As the substrate, an insulating substrate can be used, but a semi-insulating substrate, an n-type substrate, or a p-type substrate can be used as long as it can be electrically insulated from the epitaxial layer.

  The arrangement direction of the light emitting diodes is preferably a forward mesa direction. Wiring does not break at the mesa step.

  The direction tilted from the (100) plane of the main surface of the substrate can be the arrangement direction of the light emitting diodes or a direction orthogonal to the direction. The shape of the groove formed by mesa etching is stable, and the light emitting diode portion can be formed with high yield. If the direction in which the main surface is inclined deviates from the arrangement direction of the light emitting diode portions or the direction orthogonal to the direction, the shape of the light emitting diode portions formed by mesa etching becomes unstable, and the variation in light output increases.

  The direction inclined from the (100) plane of the main surface of the substrate can be the (01T) plane direction or the (0TT) plane direction.

  In one embodiment of the present invention, in order to achieve the above object, a substrate made of a GaAs single crystal and having a principal surface inclined by 1 to 20 ° with respect to the (100) plane is manufactured by the LEC method. A method of manufacturing a light-emitting diode array, comprising: stacking a plurality of epitaxial layers; and dividing the plurality of epitaxial layers by mesa etching grooves to form a plurality of light-emitting diode portions arranged in a predetermined direction. To do.

  According to the method for manufacturing a light emitting diode array, when a plurality of epitaxial layers are stacked on a substrate by an epitaxial growth method such as the MOVPE method, fogging and pits are not generated, and an epitaxial layer with good crystallinity can be obtained. . In addition, a large substrate can be obtained by manufacturing a substrate by the LEC method. Note that another manufacturing method such as a VB method or a VGF method may be used as long as a large substrate can be manufactured.

  The lamination of the plurality of epitaxial layers is preferably performed by the MOVPE method. Since the structure such as MQW (Multiple Quantum Well), DBR (Distributed Bragg Reflector), etc. can be adopted by the MOVPE method, a high output light emitting diode part can be manufactured.

  According to the present invention, a main surface of a substrate made of GaAs single crystal is tilted by 1 to 20 ° from a (100) plane, and thus a light emitting diode array having a high yield and excellent mass productivity and a method for manufacturing the same are provided. Can do.

  1 is a plan view of a light-emitting diode array according to an embodiment of the present invention, FIG. 2 is a cross-sectional view taken along line AA ′ of FIG. 1, and FIG. 3 is a cross-sectional view taken along line BB ′ of FIG. .

  This light emitting diode array has a plurality of light emitting diode portions 51 arranged in a line on a chip as shown in FIG. 1, and a p-type on a semi-insulating GaAs substrate 41 as shown in FIG. The GaAs layer 42, the p-type AlGaAs cladding layer 43, the AlGaAs active layer 44, the n-type AlGaAs cladding layer 45, and the n-type GaAs layer 46 are sequentially stacked.

(Light-emitting diode part)
The plurality of light emitting diode portions 51 are divided into m (for example, 32) blocks, and each block includes n (for example, four) light emitting diode portions 51. The plurality of light emitting diode portions 51 are connected to a common anode bonding pad 57 via a common anode electrode 55 for each block. Further, the plurality of light emitting diode portions 51 are connected to the cathode bonding pad 59 via n (for example, four) common cathode wirings 58.

  The plurality of light emitting diode portions 51 are separated and formed by mesa etching grooves 52A and 52B, and are electrically separated for each anode by a group groove 53B reaching the GaAs substrate 41. The mesa etching groove 52A has a forward mesa shape that reaches the p-type GaAs layer 42 along the arrangement direction of the light emitting diode portions 51 that coincides with the forward mesa direction. The mesa etching groove 52B has a reverse mesa shape that is orthogonal to the mesa etching groove 52A and reaches the p-type GaAs layer.

(Cathode electrode)
The cathode electrode 54 is made of AuGe / Ni / Au, the lower surface side is in ohmic contact with and electrically connected to the n-type GaAs layer 46, and the upper surface side is electrically connected to the cathode bonding pad 59 by the Au wiring 61. Connected.

  Further, the cathode electrode 54 and the cathode bonding pad 59 are electrically connected by a through hole 56, a common cathode wiring 58 and an Au wiring 61.

(Anode electrode)
The anode electrode 55 is made of AuZn / Ni / Au, the lower surface side is in ohmic contact with and electrically connected to the p-type GaAs layer 42, and the upper surface side is electrically connected to the anode bonding pad 57 by the Au wiring 61. Connected.

FIG. 4 is a circuit diagram of the photodiode array. The plurality of light emitting diode portions 51 are divided into m (32 in the figure) blocks B ₁ , B ₂ ,..., B ₃₁ , B ₃₂ , and one block has n (see FIG. In this case, the light emitting diode unit 51 includes four light emitting diode units 51. Each light emitting diode portion 51 is connected to m anodes A _{1 to} A ₃₂ common to each block, and is connected to n cathodes C _{1 to} C ₄ .

(Method for manufacturing light-emitting diode array)
Next, an example of a method for manufacturing a light-emitting diode array will be described with reference to FIGS.

(1) Preparation of Substrate FIG. 5 shows the crystal orientation of a semi-insulating GaAs substrate by the LEC method. A semi-insulating GaAs substrate 41 made of a GaAs single crystal is produced by the LEC method. The main surface 41a of the substrate 41 is in the direction shown in FIG. In the figure, G is a perpendicular to the (100) plane, and H is a perpendicular to the main surface 41 a of the semi-insulating GaAs substrate 41. The crystal plane orientation of the main surface 41a is tilted by 2 ° from the (100) plane 71, and the tilted direction is the (01T) plane 72 direction.

  The crystal plane orientation may be the (0TT) plane 73 direction in which the substrate main surface 41a is inclined with respect to the (100) plane 71. Moreover, the angle which inclines should just be the range of 1-20 degrees.

(2) Growth of Each Layer Next, as shown in FIG. 6A (a), a plurality of layers are formed on the main surface 41a of the semi-insulating GaAs substrate 41 by metal organic vapor phase epitaxy (MOVPE). Epitaxial layers, that is, p-type GaAs layer 42 (carrier concentration: 4 × 10 ¹⁹ cm ⁻³ , thickness: 1 μm), p-type AlGaAs cladding layer 43 (carrier concentration: 1 × 10 ¹⁸ cm ⁻³ , thickness: 1 μm), p-type AlGaAs active layer 44 (carrier concentration: 1 × 10 ¹⁸ cm ⁻³ , thickness: 1 μm), n-type AlGaAs cladding layer (carrier concentration: 2 × 10 ¹⁸ cm ⁻³ , thickness: 3 μm), Then, an n-type GaAs layer 46 (carrier concentration: 1 × 10 ¹⁸ cm ⁻³ , thickness: 0.5 μm) is sequentially grown.

(3) Formation of Light-Emitting Diode Portion Next, as shown in FIG. 6A (b), the portion of the n-type GaAs layer 46 corresponding to the light-emitting diode portion 51 is removed by wet etching.

(4) Separation of Light Emitting Diode Portion Next, as shown in FIG. 6A (c), wet etching is performed so that the two mesa etching grooves 52A along the column direction of the light emitting diode portion 51 reach the p-type AlGaAs cladding layer 43. To form. Further, an etching groove 52B for individually separating each light emitting diode portion 51 is formed by wet etching so as to reach the p-type AlGaAs cladding layer 43.

Next, as shown in FIGS. 6A (d), 3 and 4, the anodes A _{1 to} A ₃₂ between the blocks B 1, B 2,. Grooves 53A and 53B are formed.

(5) Formation of electrode Next, as shown in FIG. 6B (e), a first layer made of SiO _{2 having a} thickness of 0.5 μm is formed by chemical vapor deposition (CVD) so as to cover the entire top surface of the crystal surface. The insulating film 62 is formed.

  Next, as shown in FIG. 6B (f), a portion corresponding to the cathode electrode 54 of the first insulating film 62 is removed with hydrofluoric acid to form a hole, and AuGe / Ni / Au is deposited in the hole. Then, a cathode electrode 54a having a thickness of 0.5 μm is formed.

  Next, as shown in FIG. 6B (g), a portion corresponding to the anode electrode 55 of the first insulating film 62 is removed with hydrofluoric acid to form a hole, and AuZn / Ni / Au is deposited in the hole. Then, an anode electrode 55a having a thickness of 0.5 μm is formed. Next, the cathode electrode 54a and the anode electrode 55a are alloyed simultaneously.

(6) Formation of Common Cathode Wiring Next, as shown in FIG. 6B (h), after Ti / Au is deposited on the first insulating film 62, the common cathode wiring 58 having a thickness of 0.5 μm is formed by pattern etching. Form.

(7) Formation of the wiring and the bonding pad Next, as shown in FIG. 6C (i), a second insulating film 63 made of SiO ₂ having a thickness of 1μm by CVD to cover the entire top surface of the crystal surface To do.

Next, as shown in FIGS. 6C (j) and 6 (k), portions of the first insulating film 62 and the second insulating film 63 on the cathode electrode 54a are removed with hydrofluoric acid to form holes.
Further, portions of the first insulating film 62 and the second insulating film 63 on the anode electrode 55a are removed with hydrofluoric acid to form holes. Further, a portion corresponding to the through hole 56 of the second insulating film 63 is removed with hydrofluoric acid to form a hole, resist pattern formation, Ti / Au vapor deposition, and lift-off are performed, the Au wiring 61 having a thickness of 1 μm, the anode A bonding pad 57 and a cathode bonding pad 59 are formed.

(Mesa etching groove direction)
FIG. 7 is a schematic diagram for explaining the directions of the mesa etching grooves 52A and 52B. When the crystal layer formed on the GaAs substrate is mesa-etched, there are a forward mesa (V groove) direction and a reverse mesa direction as shown in FIG. Since the mesa etching groove 52A is a forward mesa direction along the arrangement direction of the light emitting diode portions 51, the Au wiring 61 connecting the cathode electrode 54 and the cathode bonding pad 59, and the anode electrode 55 and the anode bonding pad 57 are connected. The Au wiring 61 to be cut is not broken at the stepped portion.

(Operation of LED array)
A signal corresponding to image data is sent to the anodes A _{1 to} A ₃₂ with _{one of the} common cathodes C _{1 to} C ₄ turned on and the remaining common cathodes turned off. By sequentially performing this operation from the common cathodes C _{1 to} C ₄ , the light emission information of all dots can be sent.

(Effect of embodiment)
According to the light-emitting diode array according to the present embodiment, the following effects can be obtained.
(A) Since the arrangement direction of the light emitting diode portions 51 is made coincident with the forward mesa direction, the wiring is not cut at the mesa step portion.
(B) Since the GaAs substrate 41 is produced by the LEC method, an inexpensive and large-sized GaAs substrate can be produced.
(C) Since the light emitting diode unit 51 can be turned on by dynamic driving, the driving IC and the number of bonding can be reduced as compared with the static driving method.
(D) Since the epitaxial layer is grown by the MOVPE method, a structure such as MQW or DBR can be adopted, and the high-power light-emitting diode unit 51 can be obtained.

[Other embodiments]
The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the invention.

  For example, in the above embodiment, the case of an AlGaAs light emitting diode has been described. However, the present invention can also be applied to an AlGaAsP light emitting diode.

It is a top view of the light emitting diode array which concerns on embodiment of this invention. FIG. 2 is a cross-sectional view taken along line A-A ′ of FIG. 1. FIG. 2 is a sectional view taken along line B-B ′ of FIG. 1. It is a wiring diagram of the light emitting diode array shown in FIG. It is a figure which shows the crystal orientation of the semi-insulating GaAs substrate by LEC method. (A)-(d) is a manufacturing-process figure of a light emitting diode array. (E)-(h) is a manufacturing-process figure of a light emitting diode array. (I)-(k) is a manufacturing-process figure of a light emitting diode array. It is a schematic diagram for demonstrating a forward mesa direction and a reverse mesa direction.

Explanation of symbols

41 Semi-insulating GaAs substrate 41a Main surface 42 p-type GaAs layer 43 p-type AlGaAs cladding layer 44 p-type AlGaAs active layer 45 n-type AlGaAs cladding layer 46 n-type GaAs layer 46 layer 51 Light-emitting diode portion 52A Etching groove 52A Mesa etching groove 52B Mesa etching groove 53A, 53B Group groove 54, 54a, 54b Cathode electrode 55, 55a, 55b Anode electrode 56 Through hole 57 Anode bonding pad 58 Common cathode wiring 59 Cathode bonding pad 61 Au wiring 62 First insulating film 63 Second Insulating film 71 (100) surface 72 (01T) surface 73 (0TT) surface

Claims (6)

Light emission formed by laminating a plurality of epitaxial layers on a main surface of a substrate made of GaAs single crystal and dividing the plurality of epitaxial layers by mesa etching grooves to form a plurality of light emitting diode portions arranged in a predetermined direction. In the diode array:
The light emitting diode array, wherein the main surface of the substrate is inclined by 1 to 20 degrees from a (100) plane.   The light emitting diode array according to claim 1, wherein the predetermined direction is a forward mesa direction.   2. The light-emitting diode array according to claim 1, wherein a direction inclined from the (100) plane of the main surface of the substrate is the predetermined direction or a direction perpendicular to the predetermined direction.   2. The light-emitting diode array according to claim 1, wherein a direction inclined from the (100) plane of the main surface of the substrate is a (01T) plane direction or a (0TT) plane direction. A substrate made of GaAs single crystal and having a principal surface inclined by 1 to 20 ° from the (100) plane is manufactured by the LEC method,
Laminating a plurality of epitaxial layers on the main surface of the substrate;
A method for manufacturing a light-emitting diode array, wherein the plurality of epitaxial layers are divided by mesa etching grooves to form a plurality of light-emitting diode portions arranged in a predetermined direction.   6. The method of manufacturing a light emitting diode according to claim 5, wherein the stacking of the plurality of epitaxial layers is performed by an MOVPE method.

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