JP2007013025A - Field effect transistor and manufacturing method thereof - Google Patents

Abstract

A field effect transistor capable of preventing a short channel effect and improving mobility and reducing junction leakage current is provided.
A field effect transistor according to the present invention includes undoped layers 5 and 6 provided on a semiconductor substrate 1, and sources 14 and 20 and drains 15 and 21 provided on the undoped layers 5 and 6, respectively. Gate insulating films 7 and 8 provided on the undoped layers 5 and 6, gate electrodes 9 and 10 provided on the gate insulating films 7 and 8, and side surfaces of the gate electrodes 9 and 10, respectively. Side wall insulating films 19 and 13 provided respectively.
[Selection] Figure 1

Description

  The present invention relates to a MIS field effect transistor having a reduced impurity concentration in a channel region and a reduced source / drain junction capacitance and junction leakage current, and a method for manufacturing the same.

  Conventionally, high performance of integrated circuits has been realized by miniaturization of field effect transistors. In particular, by shortening the gate length, the element area is reduced, and the current driving force and the operating speed are improved. The biggest problem that occurs when shortening the gate length is the short channel effect, and in order to prevent this, it is essential to reduce the junction depth of the source / drain regions.

  FIG. 12 is a sectional view showing the structure of a conventional MOS field effect transistor. As shown in FIG. 12, in a conventional field effect transistor using Si, a well 202, a source region 203, a drain region 204, and an LDD (Lightly Doped Drain) region are formed in a semiconductor substrate 201 using an ion implantation method. 205 and 206 are formed. A gate electrode 208 made of polysilicon is formed on the semiconductor substrate 201 with a gate oxide film 207 interposed therebetween, and a gate electrode 209 made of silicide is formed on the gate electrode 208. A silicide source electrode 212 and a silicide drain electrode 213 are formed on the source region 203 and the drain region 204. Further, gate sidewall insulating films 210 and 211 are formed on the side surface of the gate electrode 208.

  When a MOS field effect transistor as shown in FIG. 12 is manufactured, the source region 203 and the drain region 204 are formed as shallow as possible in order to prevent the short channel effect, and a well structure called a pocket structure (or halo structure) is formed. A technique is used in which ions of the same type as impurities are implanted into the lower portion of the LDD region. With this technique, the impurity concentration in the channel portion can be increased, so that the short channel effect can be suppressed even if the gate length is shortened. Further, when the depth of the source / drain region is reduced, the resistance increases, and the switching speed and drive current are reduced. To prevent this, the impurity concentration of the source / drain region may be increased.

  FIG. 13 is a sectional view showing the structure of a conventional MOS field effect transistor obtained by improving the MOS field effect transistor shown in FIG. In the structure shown in FIG. 13, a source 214 and a drain 215 are formed by an epitaxial growth method. The source 214 and the drain 215 are formed by performing an ion implantation method after selectively forming a semiconductor layer made of Si or the like on the semiconductor substrate 201. Impurities are also implanted into the semiconductor substrate 201 by ion implantation when forming the source 214 and the drain 215, so that the source region 203 and the drain region 204 are formed in the semiconductor substrate 201. The transistor shown in FIG. 13 is one of the proposed improved methods because the junction depth of the source / drain regions is shallow and the impurity concentration is limited by the ion implantation method.

FIG. 14 is a cross-sectional view showing the structure of a conventional MOS field effect transistor obtained by improving the MOS field effect transistor shown in FIG. 13 (refer to Patent Document 1 for a detailed configuration). The source 214 and the drain 215 shown in FIG. 14 are formed by selective epitaxial growth with impurity doping. After the source 214 and the drain 215 are formed by epitaxial growth, an impurity is diffused in the semiconductor substrate 201 by annealing, so that the shallow source region 203 and the drain region 204 are formed. The transistor shown in FIG. 14 is also one of the proposed improved methods because there is a limit to increasing the impurity concentration by reducing the junction depth of the source / drain regions by ion implantation. In the transistor shown in FIG. 14, the junction of the source / drain regions can be formed shallower than the transistor shown in FIG.
Japanese Patent Laid-Open No. 1-186680

  However, the conventional configuration has a problem in that the carrier mobility deteriorates due to impurity scattering because the impurity concentration on the channel surface is high. In addition, a well with a high impurity concentration and a source / drain region with a high impurity concentration generate a large junction capacitance, resulting in a problem that the operation speed is reduced and the junction leakage current is increased.

Further, when a material having a dielectric constant higher than that of SiO ₂ (generally referred to as a High-K material) is used for the gate insulating film, carrier scattering at the interface between the semiconductor and the gate insulating film is increased, and the carrier mobility is increased. There was a problem of deterioration.

  The present invention solves the above-described conventional problems, and provides a MIS field effect transistor and a method for manufacturing the same that prevent short channel effects, improve mobility, and reduce junction leakage current. With the goal.

  According to one embodiment of the present invention, a field effect transistor includes a first conductivity type semiconductor layer, an undoped semiconductor layer provided on the first conductivity type semiconductor layer, and the undoped semiconductor layer spaced apart from each other. And the source and drain formed of the second conductivity type semiconductor layer and the region of the undoped semiconductor layer positioned between the source and the drain, the source and the drain are separated from each other. A first insulating film provided on the first insulating film; a gate electrode provided on the first insulating film; and an insulating film interposed between the gate electrode and the source and drain.

  In the field-effect transistor of one embodiment of the present invention, the source / drain is arranged on the undoped layer, and therefore, the source / drain hardly spreads to a portion deeper than the portion serving as the channel region in the undoped layer. As a result, the source / drain junction can be shallow. Therefore, since the wraparound of the carrier to the substrate can be suppressed, the short channel effect can be made difficult to occur.

  In addition, since an undoped semiconductor layer having a low impurity concentration serves as a channel region, mobility is not easily lowered due to impurity confusion. Therefore, high mobility can be obtained and driving current can be improved.

  Further, since the source / drain is arranged on the undoped layer, the junction capacitance can be reduced even if the impurity concentration of the source / drain is increased. Therefore, the gate capacitance and the source / drain capacitance can be reduced, and the cutoff frequency can be improved. Thereby, high-speed operation becomes possible. Also, junction leakage current can be reduced.

The undoped semiconductor layer preferably contains an impurity of 10 ¹⁰ cm ⁻³ or more and 10 ¹⁷ cm ⁻³ or less.

The first insulating film includes ZrO ₂ , ZrSiO, ZrSiON, HfO ₂ , HfSiO, HfSiON, SiN, TiO ₂ , La ₂ O ₃ , SiON, Al ₂ O ₃ , SrTiO ₃ , BaSrTiO ₃ , Nd ₂ O ₃ and It is preferable to include any one of Ta ₂ O ₅ or a laminated structure thereof.

  The second conductivity type semiconductor layer may be formed by a crystal growth method.

At least one of the first conductivity type semiconductor layer, the undoped semiconductor layer, and the second conductivity type semiconductor layer is Si _1-xy Ge _{x Cy} (0 ≦ x ≦ 1, 0 ≦ y ≦ 1). ).

  According to one embodiment of the present invention, there is provided a method for manufacturing a field effect transistor, the step of crystal-growing an undoped semiconductor layer on a first conductivity type semiconductor layer, and the formation of a first insulating film on the undoped semiconductor layer. A step of forming a gate electrode on a part of the first insulating film, a step of forming a second insulating film on a side wall of the gate electrode, the second insulating film, A step of removing an exposed portion of the first insulating film using a gate electrode as a mask, and a second electrode spaced apart from each other on the undoped semiconductor layer with the gate electrode and the second insulating layer interposed therebetween, And crystal growth of a source and a drain made of a conductive semiconductor layer.

  According to the manufacturing method of one embodiment of the present invention, since the source / drain is formed on the undoped layer, the source / drain hardly spreads to a portion deeper than the portion serving as the channel region in the undoped layer. As a result, the source / drain junction can be shallow. Therefore, since the wraparound of the carrier to the substrate can be suppressed, the short channel effect can be made difficult to occur.

  In addition, since an undoped semiconductor layer having a low impurity concentration can be used as a channel region, mobility is hardly lowered due to impurity confusion. Therefore, high mobility can be obtained and driving current can be improved.

  Further, since the source / drain is formed on the undoped layer, the junction capacitance can be reduced even if the impurity concentration of the source / drain is increased. Therefore, the gate capacitance and the source / drain capacitance can be reduced, and the cutoff frequency can be improved. Thereby, high-speed operation becomes possible. In addition, the junction leakage current can be reduced.

  A step of crystal growing an undoped semiconductor layer on the first conductivity type semiconductor layer; a step of crystal growing a second conductivity type semiconductor layer on the undoped semiconductor layer; and the second conductivity type semiconductor layer. Forming a first insulating film on the substrate, and forming a groove penetrating the first insulating film and the second conductive type semiconductor layer to separate the second conductive type semiconductor layer into two Thus, a step of forming a source and a drain made of the second conductivity type semiconductor layer, a step of forming a gate insulating film covering the surface of the groove, and a gate electrode are formed on the gate insulating film. You may provide the process and the process of removing the said 1st insulating film.

  In the field effect transistor of the present invention, the short channel effect can be prevented, the mobility can be improved, the junction leakage current can be reduced, and the junction capacitance between the source, gate and drain terminals and the substrate can be reduced.

  Embodiments of the present invention will be described below with reference to the drawings.

(First embodiment)
FIG. 1 is a cross-sectional view showing the structure of a field effect transistor according to the first embodiment of the present invention. As shown in FIG. 1, a p-type field effect transistor 40 and an n-type field effect transistor 41 are formed on the semiconductor substrate 1 of this embodiment in a state where they are separated from each other by an element isolation region 2. . An n well 3 is formed in a region of the semiconductor substrate 1 where the p-type field effect transistor 40 is formed, and a p well 4 is formed in a region where the n-type field effect transistor 41 is formed. .

On the n-well 3 and the p-well 4, undoped layers 5 and 6 made of, for example, a Si semiconductor are provided, respectively. In this specification, the undoped layers 5 and 6 mean layers formed by performing epitaxial growth without doping impurities. However, the undoped layers 5 and 6 may contain impurities at a low concentration of 10 ¹⁰ cm ⁻³ or more and 10 ¹⁷ cm ⁻³ or less.

  On the undoped layers 5 and 6, gate insulating films 7 and 8 made of, for example, oxide films, and gate electrodes 9 and 10 made of, for example, polysilicon are formed. Furthermore, a source region 20 and a drain region 21 made of, for example, a p-conductivity type Si semiconductor are formed on portions of the undoped layer 5 located on both sides of the gate electrode 9. Similarly, a source region 14 and a drain region 15 made of, for example, an n-conductivity type Si semiconductor are formed on portions of the undoped layer 6 located on both sides of the gate electrode 10.

  Sidewall insulating films 13 and 19 made of, for example, a SiN film are formed on the side surfaces of the gate electrodes 9 and 10. A source electrode 22 and a drain electrode 23 made of silicide are formed on the source region 20 and the drain region 21. Similarly, a source electrode 16 and a drain electrode 17 made of silicide are formed on the source 14 and the drain 15.

  According to such a configuration, the undoped layers 5 and 6 become channel regions. Since the impurity concentration in the channel region is low, mobility is not easily lowered due to impurity scattering. Therefore, high mobility can be obtained and driving current can be improved.

  In addition, since the sources 20 and 14 and the drains 21 and 15 are provided on the undoped layers 5 and 6, respectively, the sources 20 and 14 and the drain 21 are deeper than the portion that becomes the channel region in the undoped layers 5 and 6. 15 is difficult to spread. Therefore, since the depths of the sources 20 and 14 and the drains 21 and 15 can be reduced, the short channel effect can hardly occur.

  Further, since the sources 20 and 14 and the drains 21 and 15 are formed on the undoped layers 5 and 6, the impurity concentration of the n-well 3, the p-well 4, the sources 20 and 14 and the drains 21 and 15 is increased. Also, the junction capacity can be reduced. Therefore, the gate capacitance and the source / drain capacitance can be reduced, and the cutoff frequency can be improved. Thereby, high-speed operation becomes possible. Also, junction leakage current can be reduced.

In the present embodiment, the semiconductor substrate 1, an undoped layer 5,6, and a semiconductor layer made of Si semiconductor as a source 20,14 and drain _{21,15, Si 1-xy Ge x} C y (0 ≦ x A semiconductor material having a composition of ≦ 1, 0 ≦ y ≦ 1) may be used. For example, when a strained SiGe semiconductor, a strained Si semiconductor, a Ge semiconductor, or a strained Ge semiconductor is used for the channel layer, higher mobility than that of the Si semiconductor can be obtained.

  The materials of the sources 20 and 14 and the drains 21 and 15 can be selected in accordance with the material of the channel. For example, a Si semiconductor is used for the sources 20 and 14 and the drains 21 and 15 and a SiGe semiconductor is used for the channel. When a material having a wider band gap than the channel is selected for the source, the diffusion of carriers from the source to the channel is accelerated by the difference of the valence band generated at the heterointerface, and the speed can be increased. In addition, when a material having a wider band gap than the channel is used for the drain, off-leakage current can be reduced. FIG. 2 is a cross-sectional view illustrating a structure of a semiconductor device according to a modification of the first embodiment. As shown in FIG. 2, in this modification, an n-well 31 made of Si semiconductor, an undoped strained SiGe semiconductor layer 32 that becomes a channel, and a source region 33 and a drain region 34 made of Si semiconductor are formed.

  In order to improve various characteristics, the channel may be composed of a multilayer semiconductor. FIG. 3 is a cross-sectional view illustrating the structure of a semiconductor device according to a modification of the first embodiment. As shown in FIG. 3, in this modification, an undoped Si layer 35 is provided on the undoped strained SiGe semiconductor layer 32, and a buried channel is formed at the heterointerface. In this structure, formation of a buried channel can prevent deterioration in mobility at the gate insulating film interface.

  The gate electrodes 9 and 10 are not limited to polysilicon, but may be metal, silicide, SiGe, or poly-SiGe. By appropriately using these materials, the threshold voltage value can be controlled without increasing the channel concentration.

As the gate insulating films 7 and 8, an insulator such as a High-K material may be used instead of the SiO ₂ film. Specifically, ZrO ₂ , ZrSiO, ZrSiON, HfO ₂ , HfSiO, HfSiON, SiN, TiO ₂ , La ₂ O ₃ , SiON, Al ₂ O ₃ , SrTiO ₃ , BaSrTiO ₃ , Nd ₂ O ₃ and Ta ₂ O _{By using} any one of ₅ or a laminated structure thereof as the gate insulating films 7 and 8, it is possible to reduce the gate leakage current and increase the current driving force due to the increase in unit capacity.

Further, as control of the threshold voltage and prevention of the short channel effect, the concentration of the n-well 3 and the p-well 4 can be set to 1 × 10 ¹⁸ cm ⁻³ or more, for example. Usually, when the well concentration is increased, problems such as junction capacitance and leakage current are likely to occur. However, in this embodiment, the undoped layer 5 is interposed between the wells 3 and 4 and the gate insulating film 7. Such problems are unlikely to occur.

(Second Embodiment)
FIG. 4 is a sectional view showing the structure of a field effect transistor according to the second embodiment of the present invention. In FIG. 4, not only the undoped Si layer 32 a but also the well electrode 36 is provided on the well region 31. Since the configuration other than this is the same as the configuration shown in FIG. 2, detailed description thereof is omitted. By applying a bias to the well electrode 36, a desired threshold voltage can be obtained even if the channel is not doped with impurities. In addition, the short channel effect can be prevented.

(Third embodiment)
In the present embodiment, a method for manufacturing the field effect transistor described in the first embodiment will be described. FIG. 5A to FIG. 9B are cross-sectional views illustrating a method for manufacturing a field effect transistor according to the third embodiment of the present invention. 5A to 9B, the same members as those shown in FIG. 1 are denoted by the same reference numerals.

  In the manufacturing method of the present embodiment, first, after the element isolation region 2 is formed in a part of the semiconductor substrate 1 made of silicon in the step shown in FIG. 5A, the ion is extracted in the step shown in FIG. By performing the implantation, an n well 3 containing an n-type impurity and a p well 4 containing a p-type impurity are formed in a region surrounded by the element isolation region 2 in the semiconductor substrate 1.

  Next, in the step shown in FIG. 5C, undoped layers 5 and 6 made of, for example, a SiGe semiconductor are epitaxially grown on the n well 3 and the p well 4, and in the step shown in FIG. Insulating films 7 a and 8 a to be gate insulating films are formed on 5 and 6.

  Next, in the step shown in FIG. 6B, gate electrodes 9 and 10 made of, for example, polysilicon are formed on the insulating films 7a and 8a. Thereafter, in the step shown in FIG. 6C, an insulating film 11 made of, for example, SiN is formed on the entire insulating films 7a and 8a. Thereafter, a region 40a for forming the p-type transistor (region where the n-well 3 is formed) 40a is covered with a resist 12, and a region for forming the n-type transistor (region where the p-well 4 is formed) 41a is exposed.

  Next, by performing anisotropic etching in the step shown in FIG. 7A, the sidewall insulating film 13 is formed while leaving only the portion of the insulating film 11 located on the sidewall of the gate electrode 10. Thereafter, the exposed portion of the insulating film 8a is removed, and the gate insulating film 8 is removed.

  Next, the resist 12 is removed in the step shown in FIG. Thereafter, a source 14 and a drain 15 made of n conductivity type Si doped with P, for example, are selectively formed on the undoped layer 6 by epitaxial growth. At this time, since the region 40a for forming the p-type transistor is covered with the insulating film 11, crystal growth proceeds only in the region 41a for forming the n-type transistor.

  Next, in the step shown in FIG. 8A, the region 41a where the n-type transistor is to be formed is coated with the resist 25, and the region 40a where the p-type transistor is to be formed is exposed. In this state, by performing anisotropic etching, only the portion of the insulating film 11 located on the side wall of the gate electrode 9 is left, and the side wall insulating film 19 is formed. Thereafter, the exposed portion of the insulating film 7a is removed, and the gate insulating film 7 is formed.

  Next, the resist 25 is removed in the step shown in FIG. Thereafter, the entire upper surface of the substrate is covered with an insulating film 27. Thereafter, the region 41a for forming the n-channel transistor in the insulating film 27 is covered with the resist 26, and the region 40a for forming the p-channel transistor in the insulating film 27 is exposed.

  Next, the insulating film 27 located in the region 40a where the p-channel transistor is formed is removed by performing etching in the step shown in FIG. Thereafter, the resist 26 is removed. Thereafter, a source region 20 and a drain region 21 made of, for example, p-conductivity type Si doped with B are selectively formed on the undoped layer 5 by an epitaxial growth method. At this time, since the region 41a for forming the right n-type transistor is covered with the insulating film 27, crystal growth proceeds only in the region 40a for forming the left p-type transistor.

  Next, in the step shown in FIG. 9B, after the insulating film 27 is removed, source electrodes 16 and 22, drain electrodes 17 and 23, and gate electrodes 18 and 24 made of silicide are formed. Through the above steps, n-type and p-type transistors can be manufactured.

  Note that in this embodiment mode, the n well and the p well are formed using the ion implantation method, but may be formed using an epitaxial growth method.

(Fourth embodiment)
10 (a) to 11 (b) are cross-sectional views illustrating a method for manufacturing a field effect transistor according to the fourth embodiment of the present invention.

In the manufacturing method of the present embodiment, first, in the step shown in FIG. 10A, an n well 101 made of, for example, Si, an undoped layer 102 made of SiGe, and a p ⁺ Si layer 103 are formed on the semiconductor substrate 100 in this order. Epitaxial growth. Thereafter, a first insulating film 104 is formed on the p ⁺ Si layer 103.

Next, a resist 107 having an opening is formed on the first insulating film 104 in the step shown in FIG. Thereafter, using the resist 107 as a mask, the first insulating film 104 and the p ⁺ Si layer 103 are etched to form a groove 112 that penetrates the first insulating film 104 and the p ⁺ Si layer 103. By this etching, the p ⁺ Si layer 103 is divided into a source 105 and a drain 106 with a groove 112 therebetween.

  Next, in the step shown in FIG. 10C, the second insulating film 108 a is applied to the entire surface of the first insulating film 104 and the groove 112. 11A, after depositing a metal film (not shown) filling the trench 112 from above the second insulation film 108a, the trench 112 of the second insulation film 108a and the metal film is formed. Only the part located inside is left and the other part is removed. Thus, a gate insulating film 108 covering the surface of the trench 112 and a gate electrode 109 filling the trench 112 from above the gate insulating film 108 are formed.

  After that, in the step shown in FIG. 11B, the first insulating film 104 is removed, and the source electrode 110 and the drain electrode 111 are formed on both sides of the gate electrode 109. Through the above steps, the MIS field effect transistor of this embodiment is formed.

  In this embodiment, the n-well 101 is formed using the epitaxial growth method, but may be formed using an ion implantation method.

  The field effect transistor according to the present invention is useful as a transistor for an integrated circuit with a fine design rule in that it can prevent a short channel effect and can improve mobility and reduce junction leakage current. . Further, it is useful as a transistor for a CMOS circuit or a transistor for single use.

It is sectional drawing which shows the structure of the field effect transistor in the 1st Embodiment of this invention. In 1st Embodiment, it is sectional drawing which shows the structure of the semiconductor device of a modification. In 1st Embodiment, it is sectional drawing which shows the structure of the semiconductor device of a modification. In 2nd Embodiment, it is sectional drawing which shows the structure of the semiconductor device of a modification. (A)-(c) is sectional drawing which shows the manufacturing method of the field effect transistor in the 3rd Embodiment of this invention. (A)-(c) is sectional drawing which shows the manufacturing method of the field effect transistor in the 3rd Embodiment of this invention. (A), (b) is sectional drawing which shows the manufacturing method of the field effect transistor in the 3rd Embodiment of this invention. (A), (b) is sectional drawing which shows the manufacturing method of the field effect transistor in the 3rd Embodiment of this invention. (A), (b) is sectional drawing which shows the manufacturing method of the field effect transistor in the 3rd Embodiment of this invention. (A)-(c) is sectional drawing which shows the manufacturing method of the field effect transistor which concerns on the 4th Embodiment of this invention. (A), (b) is sectional drawing which shows the manufacturing method of the field effect transistor which concerns on the 4th Embodiment of this invention. It is sectional drawing which shows the structure of the most common MOS type field effect transistor in the past. FIG. 13 is a cross-sectional view showing a structure of a conventional MOS field effect transistor obtained by improving the MOS field effect transistor shown in FIG. It is sectional drawing which shows the structure of the conventional MOS type field effect transistor which improved the MOS type field effect transistor shown in FIG.

Explanation of symbols

1 Semiconductor substrate
2 Device isolation region
3 n-well
4 p-well
5, 6 Undoped layer
7, 8 Gate insulation film
7a, 8a Insulating film
9, 10 Gate electrode
11 Insulating film
12 resist
13, 19 Side wall insulating film
14 Source
15 Drain
16, 22 Source electrode
17, 23 Drain electrode
18, 24 Gate electrode
20, 14 source
21, 15 Drain
25, 26 resist
27 Insulating film
31 n-well
32 Undoped strained SiGe layer
32a Undoped Si layer
33 Source region
34 Drain region
35 Undoped Si layer
36 well electrode 100 semiconductor substrate 101 n well 102 undoped layer 103 p ⁺ Si layer 104 first insulating film 105 source 106 drain 107 resist 108 gate insulating film 108a second insulating film 109 gate electrode 110 source electrode 111 drain electrode 112 groove

Claims (7)

A first conductivity type semiconductor layer;
An undoped semiconductor layer provided on the semiconductor layer of the first conductivity type;
A source and a drain made of a semiconductor layer of a second conductivity type provided on the undoped semiconductor layer and spaced apart from each other;
A first insulating film provided on the region of the undoped semiconductor layer located between the source and the drain and spaced apart from the source and the drain;
A gate electrode provided on the first insulating film;
A field effect transistor comprising: the gate electrode; and a second insulating film interposed between the source and the drain. The field effect transistor according to claim 1, wherein the undoped semiconductor layer includes an impurity of 10 ¹⁰ cm ⁻³ or more and 10 ¹⁷ cm ⁻³ or less. The first insulating film includes ZrO ₂ , ZrSiO, ZrSiON, HfO ₂ , HfSiO, HfSiON, SiN, TiO ₂ , La ₂ O ₃ , SiON, Al ₂ O ₃ , SrTiO ₃ , BaSrTiO ₃ , Nd ₂ O ₃ and The field effect transistor according to claim 1, comprising any one of Ta ₂ O ₅ or a stacked structure thereof.   The field effect transistor according to claim 1, wherein the second conductivity type semiconductor layer is formed by a crystal growth method. At least one of the first conductivity type semiconductor layer, the undoped semiconductor layer, and the second conductivity type semiconductor layer is Si _1-xy Ge _{x Cy} (0 ≦ x ≦ 1, 0 ≦ y ≦ 1). The field effect transistor according to claim 1, comprising: Crystal growth of an undoped semiconductor layer on the semiconductor layer of the first conductivity type;
Forming a first insulating film on the undoped semiconductor layer;
Forming a gate electrode on a portion of the first insulating film;
Forming a second insulating film on the sidewall of the gate electrode;
Removing the exposed portion of the first insulating film using the second insulating film and the gate electrode as a mask;
And a step of crystal-growing a source and a drain made of a semiconductor layer of a second conductivity type, which are separated from each other with the gate electrode and the second insulating layer interposed therebetween on the undoped semiconductor layer. Method. Crystal growth of an undoped semiconductor layer on the semiconductor layer of the first conductivity type;
Crystal growth of a second conductivity type semiconductor layer on the undoped semiconductor layer;
Forming a first insulating film on the semiconductor layer of the second conductivity type;
A groove penetrating the first insulating film and the second conductivity type semiconductor layer is formed to separate the second conductivity type semiconductor layer into two, thereby comprising the second conductivity type semiconductor layer. Forming a source and a drain;
Forming a gate insulating film covering the surface of the trench;
Forming a gate electrode on the gate insulating film;
And a step of removing the first insulating film.

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