JP2007006700A - Power converter - Google Patents

Abstract

【Task】
An object of the present invention is to provide a pulse width modulation method and apparatus, a power conversion method, and a power converter that can make the current pulse width on the DC side greater than a width that allows current detection and that do not cause mutual interference of switching. is there.
[Solution]
The present invention includes a step of calculating a second command signal so that any two of the command signal differences in the three first command signals are equal to or greater than a predetermined value, and a pulse based on the second command signal And a step of width modulation.
[Selection] Figure 1

Description

  The present invention relates to a novel pulse width modulation method and apparatus for controlling a power converter, a power conversion method, and a power converter.

  In a power converter that converts direct current into alternating current by pulse width modulation, there is a method described in Non-Patent Document 1 as a method of detecting an alternating current from a direct current. As pulse width modulation methods suitable for this current detection method, there are methods described in Patent Document 1 and Patent Document 2. Details of the PWM control unit and the current detection unit are described in Patent Document 3, for example.

JP 2001-327173 A JP 2002-119062 JP JP 2002-95263 A Derivation of motor line-current waveforms from the DC-link current of an inverter ”IEE PROCEEDING, Vol.136, Pt.B, JULY 1989, pp.196-204

  In Non-Patent Document 1, when the AC voltage is low, the current pulse width on the DC side is small, so that it is difficult to stably detect the current on the DC side. On the other hand, in Patent Document 1, in the first half of one cycle of the pulse width modulation carrier wave, correction is made so that the current pulse width on the DC side is sufficient to stably detect the current, and in the latter half, the AC side voltage is corrected. Is corrected to a desired voltage. For this reason, in the latter half, the pulse width necessary for current detection is not ensured, and it is necessary to calculate the modulated wave with a period that is half the period of the carrier wave, and a high-performance microcomputer is required for the calculation. . Also in Patent Document 1, the current pulse width necessary for detecting the current may not be ensured.

  Further, in the methods described in Patent Document 1 and Patent Document 2, there is a case where switching of a certain phase and switching of another phase are performed in a short time, and normal switching cannot be performed due to mutual interference occurring at this time. Cannot be prevented.

  As described above, when detecting the output current of the power converter from the DC current Idc in the conventional power converter using pulse width modulation for converting DC to AC, if the voltage command signal between the phases is small, the DC current The pulse width of Idc becomes narrow and detection is difficult.

  An object of the present invention is to provide a pulse width modulation method and apparatus, a power conversion method, and a power converter that can make the current pulse width on the DC side equal to or greater than a width that allows current detection and that do not cause mutual interference of switching. There is to do.

  In the present invention, the second command signal is set such that the difference between any two or three of the command signals in each of the three first command signals is equal to or greater than a predetermined value. The pulse width modulation method includes a step of calculating and a step of performing pulse width modulation based on the second command signal.

  More specifically, the present invention relates to a pulse width modulation method in which three second command signals calculated based on three first command signals are subjected to pulse width modulation. And the three error integrated values, which are the integrated values of the differences between the three first command signals and the three second command signals, are all equal to or less than a predetermined value. A step of calculating the second command signal based on the first command signal, and a step of performing pulse width modulation on the second command signal, and three first command signals and the three first commands. Adding three error integrated values, which are integrated values of differences from the three second command signals corrected based on the signals, to the three first command signals, respectively, and calculating three third command signals; The difference between the two third command signal Characterized by a step of calculating the second command signal so that the above predetermined value.

  The present invention provides, as a power conversion method, a voltage command signal correction step for calculating a second AC voltage command signal based on a first AC voltage command signal, a pulse width modulation based on the second AC voltage command signal, and a gate signal. A PWM control step for outputting, and a step of switching a DC voltage to an AC voltage based on the gate signal, wherein the pulse width modulation comprises the pulse width modulation method described above, and an external And a motor control step for outputting the first AC voltage command signal based on a speed command signal given from the motor.

  The present invention provides a correction means for calculating a difference between any two of the command signals in the three command signals to be equal to or greater than a predetermined value, and a pulse width modulation means for performing pulse width modulation on the calculated output. The pulse width modulation device is characterized by comprising:

  Further, the present invention provides a pulse width modulation device having pulse width modulation means for pulse width modulating three second command signals calculated on the basis of three first command signals. The second command so that the difference between the command signals is greater than or equal to a predetermined value and the integrated value of the differences between the three first command signals and the three second command signals is less than or equal to a predetermined value. A correction means for calculating a signal; and three error integrated values which are integrated values of differences between the three first command signals and the three second command signals corrected based on the three first command signals. Is added to each of the three first command signals to calculate three third command signals, and the second command signal so that any two third command signal differences are not less than a predetermined value. Correction means for correcting To.

  The present invention provides a voltage command correction unit that calculates a second AC voltage command signal based on the first AC voltage command signal, and a PWM control unit that performs pulse width modulation based on the second AC voltage command signal and outputs a gate signal And a switching device for switching a DC voltage to an AC voltage based on the gate signal, and converting the DC voltage into an AC voltage, the pulse width modulation is performed by the pulse width modulation device described above It is characterized by that.

  That is, according to the present invention, the difference between any two modulation waves among the differences between the three input signals can be made to be equal to or greater than the minimum value. The interval at which two pulses change can be made longer than the time corresponding to the minimum value. In addition, by applying this pulse width modulation method to the power converter, the DC current pulse width is also longer than the time corresponding to the above minimum value, so that the DC current can be detected, and the DC side current pulse width Can be made larger than the width that allows current detection. Moreover, since the interval at which the pulses change is secured, the mutual interference of switching can be suppressed.

  In addition, the three signals and their respective error integration values are added and corrected so that the difference between any two command signals in the addition result is equal to or greater than the minimum value, and pulse width modulation is performed based on the correction result. A pulse width modulation method of updating the error integrated value from the difference between the addition results of the adding means is preferable.

  In addition, since the pulse width of the direct current is always ensured, even if the correction result is updated every half cycle of the carrier wave or an integral multiple thereof, current detection will not be hindered, so the calculation cycle may be increased. And the amount of calculation per unit time of the pulse width modulation method can be reduced. The command signal is a voltage command signal, and an error caused by the correction is preferably added to the voltage command signal.

  According to the present invention, there is provided a pulse width modulation method, an apparatus thereof, a power conversion method, and a power converter, in which a current pulse width of a direct current is always ensured to be equal to or greater than a width capable of current detection and no mutual interference of switching occurs. be able to.

Example 1
FIG. 1 is a configuration diagram showing an example of a power converter using the pulse width modulation method of the present invention. In FIG. 1, a rectifier circuit 2, a smoothing capacitor 3, a current detector 5, a current detector 7, a motor controller 8 for outputting the first AC voltage command signal based on a speed command given from outside, the first AC A voltage command correction unit 9 that corrects to a second AC voltage command signal based on the voltage command signal, a PWM control unit 6 that performs pulse width modulation based on the second AC voltage command signal and outputs a gate signal, and based on the gate signal A power converter 10 that converts a DC voltage into an AC voltage, a AC power source 1, and a motor 4 that have switching elements Qu, Qv, Qw, Qx, Qy, and Qz that switch DC voltage to AC voltage. It is a thing.

  The voltage supplied from the AC power source 1 is rectified by the rectifier circuit 2, further smoothed by the smoothing capacitor 3, and converted into a DC voltage. By switching the converted DC voltage through the switching elements Qu, Qv, Qw, Qx, Qy, and Qz, the U-phase, V-phase, and W-phase voltages connected to the motor 4 are controlled.

  The current detector 5 detects the DC current Idc flowing through the smoothing capacitor 3 from the switching elements Qx, Qy, and Qz, and the current detection unit 7 detects the detected DC current Idc and the gate signals Gu, Gv output from the PWM control unit 6. , Gw, Gx, Gy, and Gz, a U-phase motor current Iu, a V-phase motor current Iv, and a W-phase motor current Iw flowing to the motor 4 are detected. Based on the detected motor currents Iu, Iv, and Iw and the speed command Fr * given from the outside, the motor control unit 8 outputs the first U-phase AC voltage command signal Eu, the first V-phase AC voltage command signal Ev, and The first W-phase AC voltage command signal Ew is output.

  The voltage command correction unit 9 corrects the first AC voltage command signals Eu, Ev, and Ew, thereby correcting the second U-phase AC voltage command signal Eu ′, the second V-phase AC voltage command signal Ev ′, and The second W-phase AC voltage command signal Ew ′ is output, and the PWM controller 6 performs pulse width modulation based on the second AC voltage command signals Eu ′, Ev ′, and Ew ′, and the switching elements Qu, Qv, Gate signals Gu, Gv, Gw, Gx, Gy, and Gz that command switching of Qw, Qx, Qy, and Qz, respectively, are output.

  In this embodiment, a DC voltage is generated from the AC power source 1 from the rectifier circuit 2 and the smoothing capacitor 3. However, when this is replaced with a DC power source, the rectifier circuit 2 and the smoothing capacitor 3 are unnecessary.

  The voltage command correction unit 9 makes the difference between any two AC voltage command signals out of the second AC voltage command signals Eu ′, Ev ′, and Ew ′ equal to or greater than a predetermined value, and The error accumulated values dEu, dEv, and dEw obtained by integrating the respective differences between the 1 AC voltage command signals Eu, Ev, and Ew and the second AC voltage command signals Eu ′, Ev ′, and Ew ′ are The second AC voltage command signals Eu ′, Ev ′, and Ew ′ are calculated so as not to exceed a certain value.

  Specifically, the voltage command correction unit 9 accumulates the differences between the first AC voltage command signals Eu, Ev, and Ew and the second AC voltage command signals Eu ′, Ev ′, and Ew ′. Error accumulating values dEu, dEv, and dEw are obtained, and based on values obtained by adding error accumulating values dEu, dEv, and dEw and first AC voltage command signals Eu, Ev, and Ew, respectively, a second AC voltage command signal Processing is performed so that the difference between any two AC voltage command signals of Eu ′, Ev ′, and Ew ′ is equal to or greater than a predetermined value.

  The voltage command correction unit 9 will be described in more detail with reference to FIGS. FIG. 2 is a diagram illustrating the timing at which the voltage command correction unit 9 updates the second AC voltage command signals Eu ′, Ev ′, and Ew ′ that are outputs. In FIG. 2, 201 is a carrier wave used for pulse width modulation of the PWM control unit 6, and 202 to 208 are timings at which the voltage command correction unit 9 updates the output. The voltage command correction unit 9 performs processing to be described later for each half cycle of the carrier wave 201, and outputs second AC voltage command signals Eu ′, Ev ′, and Ew ′. The process shown in FIGS. 3 and 4 is the main process, and the process shown in FIG. 5 is a subroutine.

  FIG. 3 is a diagram illustrating a flow of main processing of the voltage command correction unit. The voltage command correction unit 9 first executes the process 300. In the process 300, the addition result of the U-phase AC voltage command signal Eu and the U-phase error integrated value dEu is added to the third U-phase AC voltage command signal Eu0, and the V-phase AC voltage command signal Ev and the V-phase error integrated value dEv are added. The result is assigned to the third V-phase AC voltage command signal Ev0, the addition result of the U-phase AC voltage command signal Eu and the U-phase error integrated value dEu is assigned to the third W-phase AC voltage command signal Ev0, and The process 301 is executed.

  In the process 301, the third U-phase AC voltage command signal Eu0 and the third V-phase AC voltage command signal Ev0 are compared. If Eu0 is equal to or greater than Ev0, the process 302 is executed, and Eu0 is less than Ev0. If so, the process 401 of FIG. 4 is executed next.

  In process 302, the third V-phase AC voltage command signal Ev0 is compared with the third W-phase AC voltage command signal Ew0. If Ev0 is equal to or greater than Ew0, process 303 is executed, and Ev0 is less than Ew0. In the case, processing 306 is executed.

  In the process 303, the third U-phase AC voltage command signal Eu0 is set to the first maximum voltage Ea, the third V-phase AC voltage command signal Ev0 is set to the first intermediate voltage Eb, and the third W-phase AC voltage command is set. The process 304 is executed by substituting the signal Ew0 for the first minimum voltage Ec. Details of the correction process of the process 304 will be described later.

  After the process 304, the process 305 is executed, the second maximum voltage Ea ′ is set to the second U-phase AC voltage command signal Eu ′, and the second intermediate voltage Eb ′ is set to the second V-phase AC voltage command signal Ev. Then, the second minimum voltage Ec ′ is substituted into the second W-phase AC voltage command signal Ew ′, and then the process 313 is executed.

  In the process 313, the U-phase error integrated value dEu is obtained by subtracting the second U-phase AC voltage command signal Eu ′ from the third U-phase AC voltage command signal Eu0, and the third V-phase AC voltage command signal Ev0. Is obtained by subtracting the second V-phase AC voltage command signal Ev ′ from the V-phase error integrated value dEv, and the second W-phase AC voltage command signal Ew ′ is subtracted from the third W-phase AC voltage command signal Ew0. The W-phase error integrated value dEw is updated with the obtained values, and the processing of the voltage command correction unit 9 is terminated.

  When the process 306 is executed after the process 302, the process 306 compares the third U-phase AC voltage command signal Eu0 with the third W-phase AC voltage command signal Ew0, and Eu0 is equal to or greater than Ew0. Next, process 307 is executed, and if Eu0 is less than Ew0, process 310 is executed.

  When the process 307 is executed after the process 306, in the process 307, the third U-phase AC voltage command signal Eu0 is set to the first maximum voltage Ea, and the third W-phase AC voltage command signal Ew0 is set to the first intermediate voltage. The third V-phase AC voltage command signal Ev0 is substituted for the first minimum voltage Ec for the voltage Eb, and the processing 308 is executed. Details of the correction processing of processing 308 will be described later.

  After the process 308, the process 309 is executed, the second maximum voltage Ea ′ is set to the second U-phase AC voltage command signal Eu ′, and the second intermediate voltage Eb ′ is set to the second W-phase AC voltage command signal Ew. Then, the second minimum voltage Ec ′ is substituted for the second V-phase AC voltage command signal Ev ′, the process 313 is executed, and the process of the voltage command correction unit 9 is terminated.

  When the process 310 is executed after the process 306, in the process 310, the third W-phase AC voltage command signal Ew0 is set to the first maximum voltage Ea, and the third U-phase AC voltage command signal Eu0 is set to the first intermediate voltage. The third V-phase AC voltage command signal Ev0 is substituted for the first minimum voltage Ec for the voltage Eb, and the processing 311 is executed. Details of the correction processing of processing 311 will be described later.

  After the process 311, the process 312 is executed, and the second maximum voltage Ea ′ is used as the second W-phase AC voltage command signal Ew ′, and the second intermediate voltage Eb ′ is used as the second U-phase AC voltage command signal Eu. Then, the second minimum voltage Ec ′ is substituted for the second V-phase AC voltage command signal Ev ′, the process 313 is executed, and the process of the voltage command correction unit 9 is terminated.

FIG. 4 is a diagram showing another part of the flow for performing the main processing of the voltage command correction unit 9 of FIG. If Eu0 is less than Ev0 in process 301 in FIG. 4, process 401 is executed. In process 401, the third U-phase AC voltage command signal Ew0 is compared with the third W-phase AC voltage command signal Ew0. If Eu0 is equal to or higher than Ew0, then process 402 is executed, and Eu0 is less than Ew0. If so, the process 405 is executed.

  In process 402, the third V-phase AC voltage command signal Ev0 is set to the first maximum voltage Ea, the third U-phase AC voltage command signal Eu0 is set to the first intermediate voltage Eb, and the third W-phase AC voltage command is set. The process E403 is executed by substituting the signal Ew0 for the first minimum voltage Ec.

  After the process 403, the process 404 is executed, the second maximum voltage Ea ′ is set to the second V-phase AC voltage command signal Ev ′, and the second intermediate voltage Eb ′ is set to the second U-phase AC voltage command signal Eu. Then, the second minimum voltage Ec ′ is substituted for the second W-phase AC voltage command signal Ew ′, the process 313 is executed, and the process of the voltage command correction unit 9 is terminated.

  In process 405, the third U-phase AC voltage command signal Eu0 is compared with the third W-phase AC voltage command signal Ew0. If Eu0 is equal to or greater than Ew0, process 406 is executed and Eu0 is less than Ew0. If so, then process 409 is executed.

  In process 406, the third V-phase AC voltage command signal Ev0 is set to the first maximum voltage Ea, the third W-phase AC voltage command signal Ew0 is set to the first intermediate voltage Eb, and the third U-phase AC voltage command is set. The signal Eu0 is substituted for the first minimum voltage Ec, and the process 407 is executed.

  After the process 407, the process 408 is executed, the second maximum voltage Ea ′ is set to the second V-phase AC voltage command signal Ev ′, and the second intermediate voltage Eb ′ is set to the second W-phase AC voltage command signal Ew. Then, the second minimum voltage Ec ′ is substituted for the second U-phase AC voltage command signal Eu ′, the process 313 is executed, and the process of the voltage command correction unit 9 is terminated.

  In process 409, the third W-phase AC voltage command signal Ew0 is set to the first maximum voltage Ea, the third V-phase AC voltage command signal Ev0 is set to the first intermediate voltage Eb, and the third U-phase AC voltage command is set. The process 410 is executed by substituting the signal Eu0 for the first minimum voltage Ec.

  After the process 410, the process 411 is executed, and the second maximum voltage Ea ′ is used as the second W-phase AC voltage command signal Ew ′, and the second intermediate voltage Eb ′ is used as the second V-phase AC voltage command signal Ev. Then, the second minimum voltage Ec ′ is substituted for the second U-phase AC voltage command signal Eu ′, the process 313 is executed, and the process of the voltage command correction unit 9 is terminated.

With the above processing, among the third AC voltage command signals Eu0, Ev0, and Ew0, the maximum value is set to the first maximum voltage Ea, the middle value is set to the first intermediate voltage Eb, and the minimum value is set to the first value. Substituting into the minimum voltage Ec of 1 respectively, correction processing is executed. The second maximum voltage Ea ′, the second intermediate voltage Eb ′, and the second minimum voltage Ec ′, which are the execution results of the correction process, are determined according to the magnitude relationship of the third AC voltage command signals Eu0, Ev0, and Ew0. Substitute for the second AC voltage command signals Eu ′, Ev ′, and Ew ′. Further, the first AC voltage command signals Eu, Ev, and Ew and the second AC voltage command signal Eu ′,
Errors from Ev 'and Ew' are managed by error accumulated values dEu, dEv, and dEw, and processed by third AC voltage command signals Eu0, Ev0, and Ew0 obtained by adding error accumulated values dEu, dEv, and dEw. Since the calculation including the previous error is performed, the error integrated value does not continue to increase.

FIG. 5 is a diagram showing the flow of correction processing executed in the processing 304, processing 308, and processing 311 in FIG. 3 and the processing 403, processing 407, and processing 410 in FIG. In the correction process, the difference between the maximum voltage and the intermediate voltage that determines the pulse width of the DC current, and the difference between the minimum voltage and the intermediate voltage are equal to or greater than the minimum voltage Emin corresponding to the pulse width necessary to detect the DC current. Make corrections.

  In the correction process, in the first process 501, the difference between the first maximum voltage Ea and the first intermediate voltage Eb is compared with the minimum voltage Emin. If the difference between Ea and Eb is equal to or greater than Emin, then the process 502 is performed. If the difference between Ea and Eb is less than Emin, processing 503 is executed next. In the process 502, since correction is not necessary, the first maximum voltage Ea is directly substituted for the second maximum voltage Ea ′, and the process 504 is executed.

In the process 503, since correction is necessary, a value obtained by adding the minimum voltage Emin to the first intermediate voltage Eb is substituted into the second maximum voltage Ea ′, and the process 504 is executed. As a result, the second maximum voltage
The difference between Ea and the first intermediate voltage Eb (same as the second intermediate voltage Eb) is the minimum voltage Emin, and the magnitude relationship does not change.

  In the process 504, the difference between the first intermediate voltage Eb and the first minimum voltage Ec is compared with the minimum voltage Emin. If the difference between Eb and Ec is equal to or greater than Emin, the process 505 is executed, and the difference between Eb and Ec Is less than Emin, the process 506 is executed next.

  In the process 505, since correction is not necessary, the first minimum voltage Ec is directly substituted for the second minimum voltage Ec ′, and the process 507 is executed.

  In the process 506, since correction is necessary, a value obtained by subtracting the minimum voltage Emin from the first intermediate voltage Eb is substituted for the second minimum voltage Eb ′, and the process 507 is executed. Thus, the difference between the second minimum voltage Ec and the first intermediate voltage Eb (same as the second intermediate voltage Eb) becomes the minimum voltage Emin, and the magnitude relationship does not change. In process 507, the first intermediate voltage Eb is substituted into the second intermediate voltage Eb ′.

  By the correction processing described above, the difference between the second maximum voltage Ea ′ and the second intermediate voltage Eb ′ and the difference between the second intermediate voltage Eb ′ and the second minimum voltage Ec ′ become equal to or greater than the minimum voltage Emin. Since the magnitude relationship does not change before and after correction, the second maximum voltage Ea ′ ≧ the second intermediate voltage Eb ′ ≧ the second minimum voltage Ec ′. Note that the minimum voltage Emin is used as the value added to the first intermediate voltage Eb in the process 503 and the value subtracted from Eb in the process 506, but a value larger than the minimum voltage Emin is used instead of the minimum voltage Emin. However, the purpose of correction can be achieved. However, since the correction amount becomes large at this time, the voltage error before and after the correction becomes large.

  Also, the difference between the maximum value (Ea) and the intermediate value (Eb) is not less than a certain value (Emin), and the difference between the intermediate value (Eb) and the minimum value (Ec) is not less than a certain value (Emin). The difference between Ea) and the minimum value (Ec) is not less than a certain value (Emin), and in this embodiment, each of the three command signal differences in the first AC voltage command signal is not less than a predetermined value.

  FIG. 6 is a circuit diagram showing a configuration of the PWM control unit 6. It has a carrier wave generation unit 601, a U-phase comparison unit 602, a V-phase comparison unit 603, a W-phase comparison unit 604, and inversion units 605, 606, and 607. The carrier wave generation unit 601 outputs a carrier wave C that is a triangular wave of the frequency Fc based on the carrier wave frequency command Fc. The U-phase comparison unit 602 that outputs the gate signal Gu compares the U-phase AC voltage command signal Eu with the carrier C, and outputs an H level when the U-phase AC voltage command signal Eu is large, and an L level when it is small. Is output. The inversion unit 605 that outputs the gate signal Gx outputs the H level when the gate signal Gu is at the L level, and outputs the L level when the gate signal Gu is at the H level.

  Similarly, the V-phase comparison unit 603 that outputs the gate signal Gv compares the V-phase AC voltage command signal Ev with the carrier C, and the W-phase comparison unit 604 that outputs the gate signal Gw The command signal Ew and the carrier wave C are compared and output in the same manner as the U-phase comparison unit 602. Further, the inverting unit 606 that outputs the gate signal Gy and the inverting unit 607 that outputs the gate signal Gz output the same as the gate signal Gx.

  FIG. 7 is a diagram for explaining a specific operation of the present embodiment. In the graph shown in FIG. 7, the horizontal axis represents time, and the vertical axis represents the first AC voltage command signals Eu, Ev, and Ew, the second AC voltage command signals Eu ′, Ev ′, and Ew ′, and pulse width modulation, respectively. The carrier wave C, the error integrated values dEu, dEv and dEw, the gate signals Gu, Gv and Gw, and the direct current Idc.

The first AC voltage command signals Eu, Ev, and Ew are input signals of the voltage command correction unit 6 shown in FIG. 1, and their values are 0.3, −0.1, and −0.3, respectively. Second AC voltage command signal Eu ′,
Ev ′ and Ew ′ are obtained by correcting each difference to a predetermined value (0.3) or more based on the first AC voltage command signals Eu, Ev, and Ew. Both are changing sequentially.

  The error integrated values dEu, dEv, and dEw are integrated values of differences between the first AC voltage command signals Eu, Ev, and Ew and the second AC voltage command signals Eu ′, Ev ′, and Ew ′. The values are shown as 0.0, 0.0, and 0.1, respectively. The minimum voltage Emin is 0.3, and the absolute values of the error integrated values dEu, dEv, and dEw are all equal to or greater than a predetermined value.

  As an example, the operation of the voltage command correction unit 9 at time T1 is as follows. In the process 300 of FIG. 3, 0.3, −0.1, and −0.2 are assigned to the third AC voltage command signals Eu0, Ev0, and Ew0, respectively. At this time, since Eu0> Ev0> Ew0, the process 303 is executed through the process 301 and the process 302 in FIG. In the process 303, 0.3 is substituted for the first maximum voltage Ea, -0.1 is substituted for the first intermediate voltage Eb, and -0.2 is substituted for the first minimum voltage Ec. Next, the correction process 304 in FIG. 3, that is, the correction process shown in FIG. 5 is executed.

In the correction process 304, Ea-Eb = 0.4 is compared with the minimum voltage Emin = 0.3 in the process 501 of FIG. Since Ea-Eb is equal to or greater than Emin, the process 502 is executed, and 0.3 is substituted for the second maximum voltage Ea ′. In the next process 504, Eb-Ec = 0.1 is compared with the minimum voltage Emin = 0.3.
Since it is less than Emin, processing 506 is executed. In process 506, the second minimum voltage Ec ′ is set.
Substitute -0.4. In process 507, -0.1 is substituted for the second intermediate voltage Eb ', and the correction process ends.

  Next, the process 305 in FIG. 3 is executed, and 0.3, −0.1, and −0.4 are assigned to the second AC voltage command signals Eu ′, Ev ′, and Ew ′, respectively. In the next process 313, the error integrated values dEu, dEv, and dEw are updated to 0.0, 0.0, and -0.2, respectively.

  Based on the second AC voltage command signals Eu ′, Ev ′ and Ew ′ output from the voltage command correction unit 9 described above and the carrier wave C, the PWM control unit 6 performs pulse width modulation. The PWM control unit 6 compares the magnitudes of the carrier wave C and the second AC voltage command signals Eu ′, Ev ′, and Ew ′ that are the modulated waves, respectively. If the modulated wave is larger, the corresponding gate signal is set to H. If the level is small, the L level is output.

Therefore, in the period from time T1 to time T2, the U-phase gate signal Gu first changes to the H level from the state where the gate signals Gu, Gv and Gw are all at the L level, and the second U-phase AC voltage command signal Eu ′ and the second The V-phase gate signal Gv changes to the H level with a delay corresponding to the difference between the two V-phase AC current commands Ev ′. Thereafter, the W-phase gate signal Gw changes to the H level with a delay corresponding to the difference between the second V-phase AC voltage command signal Ev ′ and the second W-phase AC current command Ew ′. Therefore, since the difference between the second AC voltage command signals Eu ′, Ev ′, and Ew ′ is equal to or higher than the minimum voltage Emin, after any gate signal changes, until another gate signal changes. At least the lowest voltage
Time corresponding to Emin is secured.

  Next, the relationship between the direct current Idc and the gate signal in the period from time T1 to T2 will be described. FIG. 7 shows a case where the U-phase motor current Iu and the V-phase motor current Iv are positive and the W-phase motor current Iw is negative. When the gate signals Gu, Gv, and Gw are all at the L level, the gate signals Gx, Gy, and Gz are all H. At this time, since the switching elements Qu, Qv, Qw are in the OFF state and the switching elements Qx, Qy, Qz are in the ON state, the current flows from the switching elements Qx and Qy to the motor 4 and from the motor 4 to the switching element Qz. Return to the switching elements Qu and Qy again. For this reason, no current flows on the DC side, and the DC current Idc is zero.

  Next, when the U-phase gate signal Gu changes to the H level, the X-phase gate signal Gx changes to the L level, the switching element Qu is turned on, and the switching element Qx is turned off. At this time, the current flows from the positive electrode of the smoothing capacitor 3 to the motor 4 through the switching element Qu, and from the motor 4 to the negative electrode of the smoothing capacitor 3 through the switching elements Qy and Qz. Therefore, the same current as the U-phase motor current Iu flows through the direct current Idc. Therefore, if the DC current is detected during this period, the U-phase motor current Iu can be detected.

  Next, when the V-phase gate signal Gv changes to the H level, the Y-phase gate signal Gy changes to the L level, the switching element Qv is turned on, and the switching element Qy is turned off. At this time, the current flows from the positive electrode of the smoothing capacitor 3 to the motor 4 through the switching elements Qu and Qv, and flows from the motor 4 to the negative electrode of the smoothing capacitor 3 through the switching element Qz. Therefore, a current having the same magnitude and reverse polarity as the W-phase motor current Iw flows in the DC current Idc. Therefore, if a DC current is detected during this period, the W-phase motor current Iw can be detected.

  Next, when the W-phase gate signal Gw changes to the H level, the Z-phase gate signal Gz changes to the L level, the switching element Qw is turned on, and the switching element Qz is turned off. At this time, the DC current Idc is 0 as in the case where the gate signals Gu, Gv, and Gw are all at the L level.

  Therefore, after the gate signal Gu changes from the L level to the H level, the period from when the gate signal Gv changes from the L level to the H level and after the gate signal Gv changes from the L level to the H level, The period until Gw changes from the L level to the H level needs to be secured for a sufficient time to detect the DC current Idc. During this period, the difference between the second U-phase AC voltage command signal Eu ′ and the second V-phase AC voltage command signal Ev ′ and the second V-phase AC voltage command signal Ev ′ and the second W-phase AC voltage command Since it is determined by the difference in signal Ew ', when these differences are corrected to be equal to or higher than the minimum voltage Emin, the minimum voltage Emin is set to a value corresponding to a time sufficient to detect the DC current Idc. A period for detecting the DC current Idc can be secured.

  In addition, the averages of the second AC voltage command signals Eu ′, Ev ′, and Ew ′ in the period of times T1 to T8 are 0.33, −0.10, and −0.29, respectively, and the first AC voltage command signals Eu, Ev , Almost equal to Ew. The error between the average of the second AC voltage command signals Eu ′, Ev ′, and Ew ′ and the first AC voltage command signals Eu, Ev, Ew is that the W-phase error integrated value dEu is 0.1. The U-phase error integrated value dEu at times T7 to T8 is managed by being 0.2.

  Further, as is clear from FIG. 7, the absolute values of the error integrated values dEu, dEv, and dEw are less than a certain value.

  In this embodiment, the error integrated value is used to suppress the voltage error due to correction. However, in applications where the requirement for the voltage error is not strict, the process related to the error integrated value can be omitted. Specifically, the error integrated values dEu, dEv, and dEw in the process 300 of FIG. 3 are set to 0, and the first AC voltage command signals Eu, Ev, and E3 are set as third AC voltage command signals Eu0, Ev0, and Ew0. This is realized by using Ew and omitting the processing 313. Thereby, processing can be reduced. In this case, in the voltage command correction unit 9, any two alternating currents among the second alternating voltage command signals Eu ′, Ev ′, and Ew ′ are based on the first alternating voltage command signals Eu, Ev, and Ew. Processing is performed so that the difference between the voltage command signals is equal to or greater than a predetermined value.

  According to the present embodiment, the pulse width of the direct current Idc is always secured so that a current can be detected, and a necessary period is ensured between the arbitrary switching and the switching, so that no mutual interference occurs. In this embodiment, the motor current of the small-capacity inverter can be reduced to CT, and the current detection can be improved in performance, generalized, and the switching element can be protected with a large capacity. It can be carried out.

  Furthermore, in the present embodiment, a direct current can be sampled and held even with a low voltage and a high carrier, and narrow recovery associated with other phase switching can be prevented.

  In addition, according to the present embodiment, the difference between any two-phase modulated waves can be made the minimum value or more, and therefore, in the pulse output as a result of pulse width modulation, the interval at which any two pulses change can be set. It can be more than the time corresponding to the minimum value. Further, by applying this pulse width modulation method to the power converter, the pulse width of the direct current becomes longer than the time corresponding to the minimum value, so that the direct current can be detected.

  Furthermore, since the current pulse width of the direct current is always ensured to be greater than the width that allows current detection, even if the update of the correction result is an integral multiple of a half cycle of the carrier wave, current detection will not be hindered. The calculation period can be increased, the amount of calculation per unit time of the pulse width modulation method can be reduced, and the interval at which the pulses change is ensured, so that pulse width modulation that does not cause switching mutual interference can be obtained.

(Example 2)
FIG. 8 is a diagram illustrating an example in which the timing at which the voltage command correction unit updates the second AC voltage command signals Eu ′, Ev ′, and Ew ′ that are outputs is changed. In FIG. 8, 201 is a carrier wave used in pulse width modulation of the PWM control unit 6, and 801 to 804 are timings when the voltage command correction unit 9 updates the output. The voltage command correction unit 9 outputs second AC voltage command signals Eu ′, Ev ′, and Ew ′ for each cycle of the carrier wave 201. In this embodiment, since the pulse width of the direct current Idc is always ensured, current detection can always be performed in a half cycle of the carrier wave. For this reason, there is no problem in current detection even when the output timing is once in one cycle as shown in FIG. Further, the output timing cycle can be extended by an integral multiple of the half cycle of the carrier wave as long as the update cycle of the voltage command signal does not become a problem. As a result, the calculation cycle of the voltage command correction unit 9 can be lengthened, and the amount of calculation per unit time can be reduced. Other effects similar to those of the first embodiment can be obtained.

The block diagram of the pulse width modulation apparatus of this invention. The figure which shows the timing which updates the 2nd alternating voltage command signal of a voltage command correction | amendment part. The flowchart which shows the process sequence of a voltage command correction | amendment part. The flowchart which shows the process sequence of a voltage command correction | amendment part. The flowchart which shows the process sequence of the correction | amendment process part of FIG.3 and FIG.4. The circuit diagram which shows the structure of the PWM control part which concerns on this invention. The figure which shows the operation example of the pulse width modulation method of this invention. The figure which shows the timing which updates the 2nd alternating voltage command signal of a voltage command correction | amendment part.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... AC power supply, 2 ... Rectifier circuit, 3 ... Smoothing capacitor, 4 ... Motor, 5 ... Current detector, 6 ... PWM control part, 7 ... Current detection part, 8 ... Motor control part, 9 ... Voltage command correction part, 10 ... Power converter, Qu, Qv, Qw, Qx, Qy and Qz ... Switching elements.

Claims (13)

  A step of calculating the second command signal so that the difference between any two of the command signals in the three first command signals is equal to or greater than a predetermined value; and pulse width modulation based on the second command signal And a pulse width modulation method.   In the pulse width modulation method of performing pulse width modulation on the three second command signals calculated based on the three first command signals, the difference between any two of the second command signals is greater than or equal to a predetermined value and the 3 Based on the first command signal, the third error integrated value, which is the integrated value of the difference between each of the first command signals and the three second command signals, is less than or equal to a predetermined value. 2. A pulse width modulation method, comprising: a step of calculating two command signals; and a step of pulse width modulating the second command signal.   In Claim 2, the step of adding the three error integrated values to the three first command signals to calculate the three third command signals, and the difference between any two of the third command signals are predetermined. And a step of calculating the second command signal so as to be equal to or greater than a predetermined value.   4. The pulse width modulation method according to claim 1, wherein the second command signal is updated every half cycle of a carrier wave for pulse width modulation.   4. The pulse width modulation method according to claim 1, wherein the second command signal is updated at an interval that is an integral multiple of a half cycle of a pulse width modulation carrier wave. A voltage command signal correcting step for calculating a second AC voltage command signal based on the first AC voltage command signal; a PWM control step for performing pulse width modulation based on the second AC voltage command signal and outputting a gate signal; and the gate A power conversion method comprising a step of switching a DC voltage based on a signal and converting the DC voltage into an AC voltage, wherein the pulse width modulation is performed by the pulse width modulation method according to any one of claims 1 to 6. Conversion method.   7. The power conversion method according to claim 6, further comprising a motor control step of outputting the first AC voltage command signal based on a speed command signal given from outside.   A correction means for correcting the difference between any two of the command signals in the three command signals to be a predetermined value or more, and a pulse width modulation means for performing pulse width modulation on the corrected output. A pulse width modulation device.   In a pulse width modulation device that performs pulse width modulation on three second command signals calculated based on the three first command signals, a difference between any two command signals of the second command signal is equal to or greater than a predetermined value and Correction means for calculating the second command signal so that an integrated value of a difference between each of the three first command signals and the three second command signals is equal to or less than a predetermined value; A pulse width modulation device comprising: pulse width modulation means for pulse width modulating the output.   10. The calculating means for calculating the three third command signals by adding the error integrated value to the three first command signals, respectively, and a difference between any two third command signals equal to or greater than a predetermined value. And a correction means for calculating the second command signal so that the second command signal is obtained.   A voltage command correction unit that calculates a second AC voltage command signal based on the first AC voltage command signal; a PWM control unit that performs pulse width modulation based on the second AC voltage command signal and outputs a gate signal; and the gate The pulse width modulation according to any one of claims 8 to 10, wherein the pulse width modulation is a power converter that converts a DC voltage into an AC voltage having a switching element that switches the DC voltage to an AC voltage based on a signal. The power converter characterized by performing by an apparatus.   12. The power converter according to claim 11, further comprising a motor control unit that outputs the first AC voltage command signal based on a speed command given from outside. 13. The electric power according to claim 11, wherein the DC voltage is supplied by a rectifier circuit that rectifies a voltage supplied from an AC power source and a smoothing capacitor that smoothes the rectified voltage and converts it into a DC voltage. converter.

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