JP2007004908A - Otp circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain an OPT circuit provided with mechanism which can be initialized by resetting it when erroneous writing is performed. <P>SOLUTION: When transistors Q1, Q2 for selection are selected, they are turned on. Transistors Aa, Qb for opening and closing are controlled so as to be turned on normally. In this state, for example, when bit data are written in a memory transistor Q3 and it is erroneous writing, the transistor Qa for opening and closing to which the erroneous writing is made is turned off, a power source supply path to the memory transistor Q3 is cut off, the memory transistor Q3 is restored to an initial state before writing. Correct bit data are written in another memory transistor Q4 the correct bit data can be used while holding at a transistor Q6 side of latch circuits (C1, C2, FF). <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an OTP (One Time Programmable) circuit, and more particularly to an OTP circuit used in a trimming circuit incorporated in a semiconductor integrated circuit device.

  The OTP circuit is a so-called nonvolatile memory that includes a memory transistor having a floating gate and a latch circuit that holds bit data written in the memory transistor and can be written only once.

  For example, in a microcomputer as a semiconductor integrated circuit device, this OTP circuit is used as a trimming circuit for enabling various adjustments. In addition, in the nonvolatile semiconductor memory device, a part of the storage area is OTP, trimming data is stored in advance there, and trimming of various voltages, sense amplifiers, references, etc. is performed using the data. A method of improving the accuracy of products by suppressing process variations and manufacturing process variations is employed.

  However, since the memory cell of the OTP circuit can basically be written only once as described above, conventionally, extra bits are written in advance in the case of erroneous writing. There is a problem that a considerable number of memory cells need to be prepared and the circuit scale becomes large.

  The present invention has been made in view of the above, and an object of the present invention is to obtain an OTP circuit having a mechanism capable of resetting and initializing a write error.

  In order to achieve the above-described object, the present invention includes a pair of selection transistors, a pair of memory transistors having a floating gate and receiving power supply via the pair of selection transistors, a latch circuit, and the pair of transistors. In the OTP circuit including a memory cell including a pair of control transistors for controlling the bit data written in each of the memory transistors to be held in the latch circuit and reading the held value of the latch circuit, A pair of open / close transistors for individually opening and closing a power supply path is provided between the selection transistor and the pair of memory transistors.

  According to the present invention, if there is an erroneous write in one of the two lines, the current flowing through the memory transistor in which the erroneous write has been performed can be cut off and returned to the initial state. The correct bit data can be written to the memory transistor belonging to the memory cell.

  According to the present invention, since rewriting can be performed on a memory cell in which erroneous writing has been performed, the OTP circuit can be reduced. In addition, since the memory cell in which erroneous writing has been performed can be utilized, the memory cell can be reproduced, that is, the bit can be reproduced.

  Exemplary embodiments of an OTP circuit according to the present invention will be described below in detail with reference to the drawings.

  FIG. 1 is a circuit diagram showing a memory cell configuration of an OTP circuit according to an embodiment of the present invention. In FIG. 1, a memory cell of an OTP circuit generally controls a selection transistor Q1, Q2, memory transistors Q3, Q4 having a floating gate and a control gate, and a latch circuit between a power supply VDD and a ground GND. The control transistors Q5 and Q6 are arranged in series.

  A common selection signal n is applied to the gate electrodes of the selection transistors Q1 and Q2 on the power supply VDD side, and ON / OFF control is performed in the same way.

  In the intermediate memory transistors Q3 and Q4, the floating gate signals FG1 and FG2 are applied to the control gate electrodes, respectively, and bit data write control is performed by individually injecting charges. The memory transistors Q3 and Q4 are in an off operation state before writing, which is an initial state, and are turned on when a current flows and writing is performed.

  In the control transistors Q5 and Q6 on the ground GND side, capacitive elements C1 and C2 are connected between the drains and sources, and a flip-flop circuit FF is connected between the drains. Capacitance elements C1 and C2 and flip-flop circuit FF constitute a latch circuit. The control transistors Q5 and Q6 are respectively applied with control signals n1 and n2 at their respective gate electrodes, and control the operation of fetching and holding the bit data written in the memory transistors Q3 and Q4 and the operation of reading out from the latch circuit. .

  In this configuration, the bit data written to the memory transistors Q3 and Q4 cannot be erased, and therefore can be written only once.

  In this embodiment, therefore, a control signal a applied to each gate electrode of the open / close transistors Qa and Qb by interposing the open / close transistors Qa and Qb between the select transistors Q1 and Q2 and the memory transistors Q3 and Q4. , B can control the opening and closing of the power supply path between the selection transistors Q1, Q2 and the memory transistors Q3, Q4.

  That is, the selection transistors Q1 and Q2 are turned on when selected. The open / close transistors Qa and Qb are normally controlled so as to be always on. The memory transistors Q3 and Q4 are in an off operation state before writing, which is an initial state.

  In this state, for example, the control transistor Q5 is turned on to supply current to the memory transistor Q3, and the floating gate signal FG1 is manipulated to inject charges into the memory transistor Q3 (write bit data). Is an erroneous write, the switching transistor Qa on the erroneous write side is turned off, and the power supply path to the memory transistor Q3 is shut off.

  As a result, the memory transistor Q3 is reset to a state in which no current flows, that is, an initial state before writing, so that correct bit data is written to another memory transistor Q4 and the correct bit data is latched. The circuit (C1, C2, FF) can be used while being held on the control transistor Q6 side.

  As described above, according to this embodiment, when erroneous bit data is written, the line in which the erroneous bit data is written is separated from the two lines of the memory cell. As a result, the erroneously written bit data is canceled, so that the correct bit data can be written to the other line.

  Therefore, it is possible to reduce the number of memory cells prepared for preliminarily writing extra bits assuming that erroneous writing is performed, and to reduce the scale of the OTP circuit. In addition, since the memory cell that has been erroneously written can be utilized, the memory cell can be reproduced, that is, the bit can be reproduced. If a trimming circuit is configured using this OTP circuit, it is possible to perform trimming again.

  As described above, the OTP circuit according to the present invention is useful for reducing the circuit scale, and is particularly suitable for use in a trimming circuit built in a semiconductor integrated circuit device.

1 is a circuit diagram showing a memory cell configuration of an OTP circuit according to an embodiment of the present invention. FIG.

Explanation of symbols

Qa, Qb Open / close transistor Q1, Q2 Select transistor Q3, Q4 Memory transistor Q5, Q6 Control transistor C1, C2 Capacitance element FF Flip-flop circuit

Claims (1)

A pair of selection transistors, a pair of memory transistors having a floating gate and receiving power supply via the pair of selection transistors, a latch circuit, and bit data written to each of the pair of memory transistors And an OTP circuit including a memory cell composed of a pair of control transistors that perform control for reading the held value of the latch circuit.
An OTP circuit comprising a pair of open / close transistors for individually opening and closing a power supply path between the pair of selection transistors and the pair of memory transistors.

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