JP2007004424A - Bus system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a bus system that reduces delay time using a simple technique. <P>SOLUTION: A bus system that connects a CPU 11 to peripheral circuits 31-34 includes flip-flops 41-44 for sending or receiving signals between the peripheral circuits 31-34 and the CPU 11, and connection means 51, 52 for connecting the flip-flops 41-44 so that a shift register is formed. The CPU 11 is connected to the flip-flop 41 that corresponds to the peripheral circuit 31 requiring the fastest response among the peripheral circuits 31-34. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a bus system that shortens a delay time of signal transfer.

  In the development of a system LSI, the configuration of the CPU and peripheral circuits is complicated (for example, the number of bits is increased), and the burden on the bus system that connects them is increasing. As a result, the signal delay in the bus system determines the performance of the entire system, and it is necessary to reduce the delay time of the bus system.

  Therefore, conventionally, as shown in FIG. 2, when the CPU 101 and the peripheral circuits 301 to 305 are connected, the circuits directly connected to the CPU 101 are limited to, for example, the four peripheral circuits 301 to 303 and the bus bridge 601. These are connected by the primary bus, and the remaining peripheral circuits 304 and 305 are connected using the bus bridge 601 and the secondary bus, thereby minimizing the signal delay in each bus and increasing the speed ( For example, see Patent Document 1 for a bus bridge). In FIG. 2, only one write data line to the peripheral circuits 301 to 305 and one read data line from the peripheral circuits 301 to 305 are shown as a bus, and other data lines, address lines, control lines, etc. are omitted. . Reference numerals 501 and 502 denote selectors for selecting read data to be loaded into the CPU 101.

Also, as shown in FIG. 3, the CPU 102 is connected to the bus unit 701 by a bus, and the peripheral circuits 306 to 308 are connected to the bus unit 701 at a ratio of 1: 1. A method in which only the delay time between 306 to 308 and the bus unit 701 needs to be considered may be adopted. In FIG. 3, only one write data line and one read data line are shown as a bus, and other data lines, address lines, control lines, etc. are omitted.
JP-A-9-231164

  However, in the method described with reference to FIG. 2, since the buses are wired radially, the number of fan-outs increases, the delay time increases, and the selector 501 for selecting signals of each peripheral circuit is 2-1. Since the selector has a multi-stage connection configuration, an increase in delay time due to this is added, which limits the speedup of the bus system. As a result, in the LSI design, the processing time of logic synthesis for achieving the target operation speed is increased, and the layout work is repeatedly generated. In addition, the method described with reference to FIG. 3 has a problem that the configuration in the bus unit 701 is complicated and timing adjustment is difficult.

  An object of the present invention is to provide a bus system in which a delay time is reduced by a simple method.

  In order to solve the above-described problems, the present invention provides a plurality of flip-flops provided to individually transfer signals to and from the plurality of peripheral circuits in a bus system that connects the CPU and the plurality of peripheral circuits. And a connection means for connecting the plurality of flip-flops so as to form a shift register, and the flip-flop corresponding to the peripheral circuit requiring the fastest response among the plurality of peripheral circuits It is characterized in that signal transfer is first performed with the CPU.

  Here, it is preferable to provide a 2-1 selector for selecting one of the two inputs on the input side of at least one of the plurality of flip-flops.

  In addition to the CPU, a bus master is provided, and the connection means connects the plurality of flip-flops so as to form a ring-shaped shift register, and the connection of the plurality of flip-flops to the CPU is connected to the CPU. A ring connection and a connection to the CPU are performed via a first 2-1 selector, and the connection to the bus master among the plurality of flip-flops is performed by connecting the ring connection and the bus master. It is also desirable to do this via a second 2-1 selector that switches.

  Furthermore, the inputs of the plurality of flip-flops are connected to the plurality of peripheral circuits through 2-1 selectors that individually select one of the two inputs, and the individual 2-1 selectors are connected to the shift circuit. It is also desirable to configure the connecting means for connecting registers.

  At this time, a bus master is provided in addition to the CPU, and the plurality of 2-1 selectors are connected so that the plurality of flip-flops form a ring-shaped shift register. The flip-flop corresponding to the peripheral circuit requiring a high-speed response is connected to the CPU, and the flip-flop corresponding to the peripheral circuit requiring the fastest response to the bus master in the peripheral circuit is connected to the bus master. It is desirable to do.

  According to the present invention, since the number of fan-outs of the plurality of flip-flops individually corresponding to the plurality of peripheral circuits is two at the maximum, the signal transfer delay can be reduced. In addition, since a peripheral circuit requiring high speed is connected from the CPU through one flip-flop, it is possible to set a priority in the peripheral circuit according to the latency of the access time. Further, since the selector used is a 2-1 selector for selecting one of the two inputs, the signal delay at that portion can be reduced. Furthermore, when a shift register composed of a plurality of flip-flops is configured in a ring shape, a bus master can be added in addition to the CPU.

  FIG. 1 is a block diagram showing the configuration of a bus system according to one embodiment of the present invention. Reference numeral 11 denotes a CPU, 21 is a bus master, 31 to 34 are peripheral circuits, 41 to 48 are flip-flops functioning as repeaters, and 51 to 56 are 2-1 selectors for selecting one of two inputs. Here, only one wiring of each of the write data line to the peripheral circuits 31 to 34 and the read data line from the peripheral circuits 31 to 34 is shown as a representative, and other data lines, address lines, control lines, and these are shown. Related flip-flops and selectors are omitted. The flip-flops 41 to 48 operate on a common clock line, but this is also omitted.

  The outputs of the flip-flops 41 to 44 are input to the peripheral circuits 31 to 34, and are connected to form a ring-shaped shift register via the selectors 51 to 52. The outputs of the flip-flops 46 and 48 are input to the bus master 21 and the CPU 11, and are connected to form a ring-shaped shift register via the flip-flops 45 and 47 and the selectors 53 to 56. .

  The write data line from the CPU 11 is connected to the flip-flop 41 via the selector 51, and the write data line from the bus master 21 is connected to the flip-flop 43 via the selector 52. A read data line from the peripheral circuit 31 is connected to the flip-flop 48 via the selector 56, and a read data line from the peripheral circuit 32 is connected to the flip-flop 47 via the selector 55, and a read data line from the peripheral circuit 33 is read. Is connected to the flip-flop 46 via the selector 54, and the read data line from the peripheral circuit 34 is connected to the flip-flop 45 via the selector 53.

  As described above, the number of fan-outs of the flip-flops 41 to 48 is 1 or 2, and the signal delay can be shortened. Further, since the CPU 11 and the bus master 21 and the peripheral circuits 31 to 34 are connected via the shortest one flip-flop and the longest four flip-flops, the CPU 11 and the bus master 21 and each peripheral circuit. Priorities can be set for access times between 31-34. Each of the flip-flops 41 to 48 performs a shift operation. Among them, the flip-flops 41 to 44 also perform an operation of loading write data to the peripheral circuits 31 to 34, and the flip-flops 45 to 48 include the peripheral circuits 31 to 34. The operation of loading the read data from is also performed. Further, the CPU 11, the bus master 21, and the peripheral circuits 31 to 34 perform data setting (writing) when the load is permitted. Also, each flip-flop is provided with a valid bit, and when the load is loaded, the valid bit is set. When the CPU 11 and the bus master 21 obtain the read data, the clear is obtained. When the peripheral circuits 31 to 34 obtain the write data. To clear. The shift register to which each flip-flop is connected has a loop configuration, and master functions such as the CPU 11 and the bus master 21 can be arranged at any position.

  When data is written from the CPU 11 to the peripheral circuit 31, the selector 51 is switched to the CPU 11 side and the data is input to the peripheral circuit 31 via the flip-flop 41. At this time, the access time from the CPU 11 to the peripheral circuit 31 is one clock.

  When writing data from the CPU 11 to the peripheral circuit 32, the selector 51 is switched to the CPU 11 side and the data is input to the peripheral circuit 32 via the flip-flops 41 and 42. At this time, the access time from the CPU 11 to the peripheral circuit 32 is 2 clocks.

  When writing data from the CPU 11 to the peripheral circuit 33, the selector 51 is switched to the CPU 11 side, the selector 52 is switched to the flip-flop 42 side, and the data is input to the peripheral circuit 33 via the flip-flops 41, 42, and 43. . At this time, the access time from the CPU 11 to the peripheral circuit 33 is 3 clocks.

  When writing data from the CPU 11 to the peripheral circuit 34, the selector 51 is switched to the CPU 11 side, the selector 52 is switched to the flip-flop 42 side, and the data is transferred to the peripheral circuit 34 via the flip-flops 41, 42, 43, 44. Let them enter. At this time, the access time from the CPU 11 to the peripheral circuit 34 is 4 clocks.

  When writing data from the bus master 21 to the peripheral circuit 33, the selector 52 is switched to the bus master 21 side and the data is input to the peripheral circuit 33 via the flip-flop 43. At this time, the access time from the bus master 21 to the peripheral circuit 33 is one clock.

  When writing data from the bus master 21 to the peripheral circuit 34, the selector 52 is switched to the bus master 21 side, and the data is input to the peripheral circuit 34 via the flip-flops 43 and 44. At this time, the access time from the bus master 21 to the peripheral circuit 34 is 2 clocks.

  When data is written from the bus master 21 to the peripheral circuit 31, the selector 52 is switched to the bus master 21 side, the selector 51 is switched to the flip-flop 44 side, and the data is transferred to the peripheral circuit 31 via the flip-flops 43, 44, 41. Let them enter. At this time, the access time from the bus master 21 to the peripheral circuit 31 is 3 clocks.

  When writing data from the bus master 21 to the peripheral circuit 32, the selector 52 is switched to the bus master 21 side, the selector 51 is switched to the flip-flop 44 side, and the data is transferred via the flip-flops 43, 44, 41, 42 to the peripheral circuit. 32. At this time, the access time from the bus master 21 to the peripheral circuit 32 is 4 clocks.

  When the CPU 11 reads data from the peripheral circuit 31, the selector 56 is switched to the peripheral circuit 31 side and the data is input to the CPU 11 via the flip-flop 48. At this time, the access time from the peripheral circuit 31 to the CPU 11 is one clock.

  When the CPU 11 reads data from the peripheral circuit 32, the selector 56 is switched to the flip-flop 47 side, the selector 55 is switched to the peripheral circuit 32 side, and the data is input to the CPU 11 via the flip-flops 47 and 48. . At this time, the access time from the peripheral circuit 32 to the CPU 11 is two clocks.

  When the CPU 11 reads data from the peripheral circuit 33, the selector 56 is switched to the flip-flop 47 side, the selector 55 is switched to the flip-flop 46 side, the selector 54 is switched to the peripheral circuit 33 side, and the flip-flops 46, 47 are switched. , 48, the data is input to the CPU 11. At this time, the access time from the peripheral circuit 33 to the CPU 11 is 3 clocks.

  When the CPU 11 reads data from the peripheral circuit 34, the selector 56 is switched to the flip-flop 47, the selector 55 is switched to the flip-flop 46, the selector 54 is switched to the flip-flop 45, and the selector 53 is switched to the peripheral circuit 34. The data is input to the CPU 11 via the flip-flops 45, 46, 47 and 48. At this time, the access time from the peripheral circuit 34 to the CPU 11 is 4 clocks.

  When the bus master 21 reads data from the peripheral circuit 33, the selector 54 is switched to the peripheral circuit 33, and the data is input to the bus master 21 via the flip-flop 46. At this time, the access time from the peripheral circuit 33 to the bus master 21 is one clock.

  When the bus master 21 reads data from the peripheral circuit 34, the selector 54 is switched to the flip-flop 45 side, the selector 53 is switched to the peripheral circuit 34 side, and the data is transferred to the bus master 21 via the flip-flops 45 and 46. Let them enter. At this time, the access time from the peripheral circuit 34 to the bus master 21 is 2 clocks.

  When the bus master 21 reads data from the peripheral circuit 31, the selector 54 is switched to the flip-flop 45 side, the selector 53 is switched to the flip-flop 48 side, the selector 56 is switched to the peripheral circuit 31 side, and the flip-flop 48, The data is input to the bus master 21 via 45 and 46. At this time, the access time from the peripheral circuit 31 to the bus master 21 is 3 clocks.

  When the bus master 21 reads data from the peripheral circuit 32, the selector 54 is switched to the flip-flop 45, the selector 53 is switched to the flip-flop 48, the selector 56 is switched to the flip-flop 47, and the selector 55 is switched to the peripheral circuit. Switching to the 32 side, the data is input to the bus master 21 via the flip-flops 47, 48, 45, 46. At this time, the access time from the peripheral circuit 32 to the bus master 21 is 4 clocks.

  As described above, the access time between the CPU 11 and the peripheral circuit 31 is 1 clock, 2 clocks between the peripheral circuit 32, 3 clocks with the peripheral circuit 33, and 4 clocks with the peripheral circuit 34. Thus, there are 1 clock between the bus master 21 and the peripheral circuit 33, 2 clocks between the peripheral circuit 34, 3 clocks with the peripheral circuit 31, and 4 clocks with the peripheral circuit 32.

  Therefore, by assigning peripheral circuits corresponding to the priority order of access to the CPU 11 and the bus master 21 as the peripheral circuits 31 to 34, it is possible to ensure the high speed required for each peripheral circuit.

It is a block diagram which shows the structure of the bus system of the Example of this invention. It is a block diagram which shows the structure of the conventional bus system. It is a block diagram which shows the structure of another conventional bus system.

Explanation of symbols

11, 101, 102: CPU
21: Bus masters 31-34, 301-308: Peripheral circuits 41-48: Flip-flops 51-56, 501, 502: Selector 601: Bus bridge 701: Bus unit

Claims (5)

In a bus system that connects a CPU and a plurality of peripheral circuits,
A plurality of flip-flops provided to individually transfer signals to and from the plurality of peripheral circuits, and connection means for connecting the plurality of flip-flops so as to form a shift register. A bus system characterized in that the flip-flop corresponding to the peripheral circuit requiring the fastest response among the peripheral circuits first performs signal transfer with the CPU. The bus system according to claim 1,
A bus system comprising a 2-1 selector for selecting one of two inputs on an input side of at least one flip-flop of the plurality of flip-flops. The bus system according to claim 2,
A bus master is provided in addition to the CPU, and the connection means connects the plurality of flip-flops to form a ring-shaped shift register, and the connection of the plurality of flip-flops to the CPU is the ring-shaped And a first 2-1 selector for switching the connection to the CPU, and the connection to the bus master among the plurality of flip-flops is switched to the ring-shaped connection and the connection to the bus master. 2. A bus system, which is performed via a 2-1 selector. The bus system according to claim 1,
The inputs of the plurality of flip-flops are connected to the plurality of peripheral circuits through 2-1 selectors that individually select one of the two inputs, and the individual 2-1 selectors are connected to the shift register. A bus system comprising the connection means for performing connection. The bus system according to claim 4,
In addition to the CPU, a bus master is provided, and the plurality of 2-1 selectors connect the plurality of flip-flops to form a ring-shaped shift register, so that the fastest response to the CPU in the peripheral circuit is achieved. The flip-flop corresponding to the required peripheral circuit is connected to the CPU, and the flip-flop corresponding to the peripheral circuit requiring the fastest response to the bus master in the peripheral circuit is connected to the bus master. Characteristic bus system.

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