JP2006351056A - Semiconductor memory device and its test method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device and its test method by which test time is shortened, cost required for the test is reduced and the latitude in the test can be improved. <P>SOLUTION: The semiconductor memory device is provided with: a block address decoder circuit in which a block address signal is decoded for selecting an arbitrary block, one of block selection signals DECD associated separately for every block can be output while being selected and the all other signals being non-selected; and a non-selection state latch circuit 2b in which an own block is fixed forcedly to a non-selection state independently of an input state of the block selection signal DECD for every block. While the non-selection state latch circuit 2b is reset, a selection state or a non-selection state of each block corresponding is decided in accordance with an input state of the block selection signal DECD, in the prescribed test mode, the block address decoder circuit sets a plurality of block selection signals DECD to the selection state, to be output. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a test technique for a semiconductor memory device, in particular, a memory cell array in which a plurality of memory cells capable of storing data are arranged in a matrix in the row direction and the column direction as one block, and the memory cell array is divided into a plurality of blocks. The present invention relates to a semiconductor memory device including the entire memory cell array and a test method thereof.

  In general, a semiconductor memory device has a memory cell array in which a plurality of memory cells each storing data in a row direction and a column direction are arranged in a matrix as one block, and the entire memory cell array has a plurality of blocks. It is configured. In addition, the semiconductor memory device has a block decoder that controls access to the memory cell array in units of blocks, a row decoder that controls a word line that reads data stored in each memory cell, and a voltage or current corresponding to the data. A column decoder that controls the bit lines, an address generation circuit that generates an internal address signal corresponding to an address input from the outside to each decoder, and the like.

  In a product test such as a reliability test in a semiconductor memory device, the cost required for the test generally depends on the test time. Therefore, the test cost can be reduced by shortening the test time. For this reason, conventionally, for example, the test time is shortened by simultaneously performing tests on all the memory blocks.

  Here, for example, a reliability test for a semiconductor memory device includes an electrical stress method in which a failure is detected by setting a predetermined node of a memory block to a high voltage. In this electrical stress test, if a node to which a high voltage is applied has a defect and a leakage path exists, the leakage current becomes very large due to the high voltage. For this reason, the voltage level of each node to which a high voltage is applied is lowered, so that a desired electrical stress cannot be applied, and the test may not be performed effectively. In this case, for example, in order to suppress the leakage current caused by the defective block at the time of performing the test, the defective block having the leakage path is deselected and excluded from the test target, thereby removing memory blocks other than the defective block. A test can be performed.

  For example, in a semiconductor memory device having a plurality of memory blocks, a test is performed by comparing all the memory blocks in a selected state and comparing block address signals. There is a semiconductor memory device in which a memory block that is not to be specified is specified and the selected state of the memory block that is not to be tested is released to be in a non-selected state (see, for example, Patent Document 1). In this semiconductor memory device, when a test is performed, a test for a defective block is not performed by canceling the selected state of a defective block not to be tested and making it non-selected. Since the test for the defective block is not performed, the leakage current caused by the defective block can be reduced and the voltage drop can be suppressed.

  Here, FIG. 7 shows a configuration of the semiconductor memory device described in Patent Document 1. In this semiconductor memory device, when setting a test mode for performing a product test or the like, all Pi, Qi, and Ri are set to the H level (power supply potential level), and thereafter, when SBDIch is set to the H level, Select the memory block. Subsequently, when an address of a defective block detected in advance is inputted and UBDIch becomes H level, the selection state of the defective block is canceled and the non-selection state is set. Subsequently, when / ERA becomes L level (ground potential level), the transfer gate is controlled according to the selected state of each memory block. As a result, only normal memory blocks can be collectively tested.

JP-A-9-288899

  However, in the semiconductor memory device described in Patent Document 1, after all the memory blocks are collectively selected, the selected state of a memory block such as a defective block that is not tested is canceled and is not selected. Therefore, when the test is performed, both the operation for selecting and the operation for selecting the non-selected state are required. In addition, since the memory block not to be tested is specified by the block address, an address comparison circuit is required for each memory block, resulting in a problem that the circuit scale increases.

  Furthermore, in the semiconductor memory device of the above-mentioned Patent Document 1, in a predetermined test mode, only one of a case where all the memory blocks are tested at once and a case where a test is performed for each memory block can be selected. A plurality of memory blocks cannot be selected at the same time, and the degree of freedom in testing is small.

  Further, in recent years, the capacity of semiconductor memory devices has been increasing, and in particular, when testing a large capacity semiconductor memory device having a very large number of memory blocks, all the memory blocks to be tested are normal. Even in the memory block, the leakage current becomes very large in the entire semiconductor memory device. For this reason, in particular, in the test using the electrical stress method, when a high voltage is applied, the voltage drop due to the leakage current cannot be ignored, and the voltage level necessary for the electrical stress application test cannot be maintained. In some cases, a batch test could not be performed. In this case, since the semiconductor memory device of Patent Document 1 cannot perform tests on all the memory blocks at once, the test must be performed by applying a high voltage to each memory block, thereby shortening the test time. There is a problem that can not be.

  By the way, in general, a redundant block is prepared in advance in a semiconductor memory device in order to relieve a defective block. However, there are more defective blocks than the number of prepared redundant blocks, and some memory areas cannot be used. Conventionally, semiconductor memory devices have been treated as defective products. However, in recent years, even in a semiconductor memory device in which some of the memory areas cannot be used, by setting advantageous conditions such as a lower price than a semiconductor memory device in which the entire memory area can be used, The demand for such a semiconductor memory device is increasing. However, a semiconductor memory device in which a part of the memory area cannot be used has many defects. In particular, in a test using an electrical stress method in which a high voltage is applied, a voltage drop occurs due to a leakage current caused by a defect in a defective block. There are cases where the electrical stress application test for all memory blocks cannot be performed at once. In this case, an electrical stress application test for a normal memory block must be performed for each memory block, which increases the test time and cost for the electrical stress application test and cannot be supplied as a product. was there.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor memory device capable of reducing the test time and the cost for the test and increasing the degree of freedom for the test. In the point.

  In order to achieve the above object, a semiconductor memory device according to the present invention comprises a memory cell array in which a plurality of memory cells capable of storing data are arranged in a matrix in the row direction and the column direction as one block. Is a semiconductor memory device comprising a plurality of blocks, and the entire memory cell array is configured, and in order to select an arbitrary block from the entire memory cell array, a block address signal is decoded and each block is individually handled A block address decoder circuit capable of outputting one of the attached block selection signals in a selected state and all others in a non-selected state, and determining the selected state or non-selected state of its own block for each of the blocks Regardless of the input state of the block selection signal, the block is forcibly fixed to the non-selected state. A selection state latch circuit, and in a reset state in which the non-selection state latch circuit is not fixed to the non-selection state, the selection state or non-selection of each block corresponding to the input state of the block selection signal A state is determined, and in a predetermined test mode, the block address decoder circuit is configured so that a plurality of the block selection signals can be set to a selected state and output.

  In the semiconductor memory device according to the present invention having the above characteristics, individual block decoder circuits including at least the final stage decode circuit that outputs the block selection signal in the block address decoder circuit are adjacent to the corresponding block, respectively. The second feature is that the non-selected state latch circuit and the individual block decoder circuit are arranged in pairs for each block.

  In the semiconductor memory device according to the present invention having any one of the above characteristics, the non-selection state latch circuit is configured to be able to be fixed in a non-selection state when the block selection signal of the corresponding block is in a selection state. The third feature.

  The semiconductor memory device according to the present invention having any one of the above features is characterized in that the non-selected state latch circuit is configured to be able to release the state fixed to the non-selected state and return to the reset state. It is characterized by.

  In the semiconductor memory device according to the present invention having any one of the above features, in each of the memory cell arrays, the memory cells in the same row are connected to a common row selection line, and the memory cells in the same column are connected to a common column selection line. It is configured that all the row selection lines of the block selected by the block selection signal set and output in the selected state are set in the selected state in the predetermined test mode. It is characterized by.

  In the semiconductor memory device according to the first to fourth aspects of the present invention, in each of the memory cell arrays, the memory cells in the same row are connected to a common row selection line, and the memory cells in the same column are Connected to a common column selection line, and in the predetermined test mode, all the column selection lines of the block selected by the block selection signal set and output in the selected state are set to the selected state. This is a sixth feature.

  The semiconductor memory device according to the present invention having any one of the above characteristics is configured such that the entire memory cell array includes a plurality of planes formed by aggregating two or more blocks, and the block address decoder circuit in a predetermined test mode. However, according to a seventh aspect of the present invention, the block selection signal can be output by setting a selection state and a non-selection state of the block selection signal for each plane.

  The semiconductor memory device according to the present invention having any one of the above features includes a defective memory cell array including the memory cells that are defective in operation in memory cell units, row units, column units, or block units in the entire memory cell array. An eighth feature is that at least one block is included.

  In order to achieve the above object, a test method for a semiconductor memory device according to the present invention is the semiconductor memory device according to the eighth feature, wherein all the non-selected state latch circuits corresponding to the defective memory cell array are brought into a non-selected state. After the fixing, in the predetermined test mode, the block address decoder circuit is controlled to select all or a plurality of blocks of the entire memory cell array at the same time.

  The semiconductor memory device according to the present invention having the above-described features forcibly fixes its own block to the non-selected state for each block regardless of the input state of the block selection signal that determines the selected state or non-selected state of the own block. Since the non-selection state latch circuit is provided, blocks that are not tested in a predetermined test mode can be automatically excluded from the test target inside the apparatus. That is, in product tests such as reliability tests, even if the block is specified by an external block address signal, the block is forcibly fixed in the non-selected state inside the device by the non-selected state latch circuit. Can do. As a result, compared with the case where all the blocks are selected at once and the block where the test is not performed is set to the non-selected state, the process for setting the block which is not tested to the non-selected state by the non-selected state latch circuit is performed. Since it is not necessary, the test time and cost can be reduced. Furthermore, since a non-selection state latch circuit is provided for each block, it can be determined whether or not it is a block to be tested without comparing block addresses, and the block selection state in a predetermined test mode, The configuration for setting the non-selected state can be simplified.

  Further, since the non-selection state latch circuit is configured to forcibly set the defective block in the non-selection state inside the device in a predetermined test mode, for example, all the blocks in the entire memory cell array or a part of a plurality of blocks are arranged. It can control to select simultaneously. In addition, for example, a test can be performed for each plane formed by aggregating two or more blocks, and the degree of freedom in the test can be increased. In this case, if the selection state is made in units of planes from the outside, the defective blocks in the plane are automatically made non-selected in the apparatus, so that the labor required for the test can be simplified. Therefore, it is particularly useful for a semiconductor memory device that has a very large storage capacity and it is difficult to perform a collective test on all memory blocks, and it is possible to reduce test time and cost.

  In addition, according to the present invention, for example, in a semiconductor memory device that has a large number of defective blocks and cannot use a part of a memory area, and cannot perform an electrical stress application test due to a voltage drop due to a leakage current. However, since a defective block is automatically fixed in a non-selected state internally in a predetermined test mode, it is possible to perform a test collectively only on a normally operating block. As a result, it is possible to perform an electrical stress application test on a semiconductor memory device that could not be subjected to an electrical stress application test due to a voltage drop due to a leakage current, and can be shipped as a product. become. As a result, an improvement in yield can be expected.

  According to the present invention, in the predetermined test mode, the non-selected state latch circuit can forcibly set the block not to be tested in the device to the non-selected state. No need to switch to. In addition, because blocks that are not tested can be automatically excluded from the test target inside the device, not only can all blocks be selected simultaneously in a given test mode, but some blocks can be selected or specified simultaneously. It is also possible to select only this plane and perform the test. Therefore, it is particularly useful for a large-capacity semiconductor memory device that cannot perform tests on all blocks at once, and it is possible to shorten the test time and the cost required for the tests.

  Furthermore, according to the present invention, it is possible to perform a test collectively only on a normally operating block. For this reason, a part of the memory area cannot be used, and the electrical stress application test cannot be performed. Therefore, the electrical stress application test can be performed even on a semiconductor memory device which has been regarded as a defective product. Accordingly, it becomes possible to supply a semiconductor memory device in which such a part of the memory area cannot be used as a product, and an improvement in yield can be expected.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a semiconductor memory device according to the present invention (hereinafter referred to as “the present device” as appropriate) will be described below with reference to the drawings.

<First Embodiment>
1st Embodiment of this invention apparatus is described based on FIGS. In the present embodiment, assuming that a selected state and a non-selected state are set in units of memory blocks in a predetermined test mode, an address signal input from the outside includes a block address signal. The case will be described.

  Here, FIG. 1 is a block diagram showing a configuration of the device 1 of the present invention in the present embodiment. The device 1 of the present invention has a memory cell array 4 in which a plurality of memory cells capable of storing data are arranged in a matrix in the row direction and the column direction as one block, and a plurality of memory cell arrays 4 are provided. As shown in FIG. 1, a block address generation circuit 7, a row address generation circuit 8, a word line drive circuit 9, a column address generation circuit 10, a bit line drive circuit 11, a global column decoder 12, and an I / O (input / output buffer) 13 is provided.

  The block address generation circuit 7 decodes a block address signal to select one arbitrary block from the entire memory cell array, and puts one of the block selection signals DECD associated with each block into a selected state. All the others are in a non-selected state and can be output. Specifically, when an address signal is input to the device 1 of the present invention from the outside via the I / O 13, the block address generation circuit 7 directly or predecodes the block address signal in the address signal, The data is output to the block decoder 2a provided in the block 6. In this embodiment, when the block address generation circuit 7 is configured to output the predecoded signal to the block decoder 2a, the block address generation circuit 7 includes a predecode circuit. In this embodiment, the block address generation circuit 7 outputs the signal DIN1 and the signal DIN2 to the block decoder 2a. The number of signals to be output is set according to the number of memory blocks 6.

  Further, the block address generation circuit 7 is configured to be able to output a plurality of block selection signals DECD in a selected state in a predetermined test mode.

  The row address generation circuit 8 directly or predecodes the row address portion of the address signal and outputs it to the row decoder 3 of the memory block 6. The column address generation circuit 10 directly or predecodes the column address portion of the address signal and outputs it to the global column decoder 12 and the local column decoder 5 of the memory block 6. The word line driving circuit 9 applies a voltage to a word line (row selection line) of the memory cell array 4 according to a predetermined access operation, for example, a read operation and a write operation. The bit line drive circuit 11 applies a voltage to the bit line (column selection line) of the memory cell array 4 according to the set access operation.

  As shown in FIG. 2, the memory block 6 includes a block decoder 2a, a non-selected state latch circuit 2b, a row decoder 3, a memory cell array 4, and a local column decoder 5.

  In the present embodiment, as shown in FIG. 2, the memory cell array 4 is configured by connecting memory cells in the same row to a common word line and connecting memory cells in the same column to a common bit line. In the test mode, the memory cell array 4 of the present embodiment is configured such that all word lines of the memory block 6 selected by the signal ROW set and output in the selected state are set in the selected state. Yes.

  The block decoder 2 a has a function as an individual block decoder circuit including at least the decoding circuit at the final stage that outputs at least the block selection signal DECD in the block address generation circuit 7, and is provided for each memory block 6. The block decoder 2a of the present embodiment is arranged adjacent to the corresponding memory block 6, and is configured to be paired with the non-selected state latch circuit 2b. A control signal DECD is output.

  The non-selection state latch circuit 2b forcibly deselects its own memory block 6 regardless of the input state of the block selection signal DECD that determines the selection state or non-selection state of its own memory block 6 in a predetermined test mode. It is configured to be fixable to the state. The non-selected state latch circuit 2b is connected to the row decoder 3 and the local column decoder 5, and is a signal that is a negative logical sum (NOR) of the block selection signal DECD and the signal LATD with respect to the row decoder 3 and the local column decoder 5. BOUT is output.

  More specifically, the non-selected state latch circuit 2b of the present embodiment outputs an H level signal LATD when it is fixed in the non-selected state. At this time, as shown in FIG. 2, the signal BOUT is at the L level regardless of the state of the block selection signal DECD because one input of the NOR gate is fixed at the H level. On the other hand, in the reset state that is not fixed to the non-selected state, the non-selected state latch circuit 2b outputs the L level signal LATD. At this time, the output of the signal BOUT is determined according to the input level of the block selection signal DECD output from the block decoder 2a.

  Next, the operation of each memory block 6 in the present embodiment will be described with reference to FIGS.

  First, an access operation to the memory cell array 4 such as a normal read operation and a write operation of the device 1 of the present invention will be described. Here, FIG. 3 is a voltage waveform diagram showing the state of each node of the device 1 of the present invention in the normal access operation.

  In the standby state, as shown in FIG. 3, the L level (ground potential level) is input to the node / LR and the node LE of the non-selected state latch circuit 2b. As a result, the signal LATD of the non-selected state latch circuit 2b becomes L level, and the output of the signal BOUT (NOR of the block selection signal DECD and the signal LATD) is determined according to the output of the block selection signal output from the block decoder 2a. . In other words, the output of the block selection signal DECD is determined according to the signal DIN1 and the signal DIN2 obtained by directly or predecoding the address signal by the block address generation circuit 7. In the standby state, the signal DIN1 and the signal DIN2 are L level for all the memory blocks 6, and therefore the output of the signal BOUT is L level.

  In addition, voltages corresponding to the access operation are input to the voltage VPX and the voltage VPW. Further, the input level of the signal XAWL is inputted with a potential lower than the threshold voltage (absolute value) of the PMOS transistor than the voltage VPX, and the input level of the signal YABL is inputted with a potential lower than the threshold of the PMOS transistor than the voltage VPW. The PMOS transistor is turned on. As a result, the signal ROW and the signal COL become L level, and the entire memory cell array 4 is unselected in all the memory blocks 6.

  During the access operation, the H level is input to the node XR of the row decoder 3 of the memory block 6 selected by the row address and the node LYS of the local column decoder 5 of the memory block 6 selected by the column address. Here, in the memory block 6 selected by the address signal, the H level (power supply potential level) is input to the signals DIN1 and DIN2 of the block decoder 2a, and the block selection signal DECD becomes the L level. As a result, the internal signal BOUT becomes H level. Further, the signal ROW (word line) and the signal COL (bit line selection signal) are voltages corresponding to the access operation, similarly to the voltage VPX and the voltage VPW. As a result, in the memory block 6 selected by the input address signal, each memory cell on the selected word line and the selected bit line is selected. Then, a potential corresponding to the access operation is input to the voltage VPX by the word line driving circuit 9 and a potential corresponding to the access operation is input to the node GCOL by the bit line driving circuit 11 to the selected memory cell. An access operation to the cell is performed.

  In the access operation, in the memory block 6 not specified by the input address signal, that is, in the memory block 6 in which at least one of the signal DIN1 and the signal DIN2 from the block address generation circuit 7 is L level, the output from the block decoder 2a The block selection signal DECD to be performed becomes H level, and the internal signal BOUT becomes L level. As a result, the signal ROW of the row decoder 3 and the signal COL of the local column decoder 5 become L level, and are in a non-selected state.

  Next, the operation in the test mode of the device 1 of the present invention will be described. Here, FIG. 4 is a voltage waveform diagram showing the operation of the device 1 of the present invention in the test mode, and here, a description will be given assuming that all word lines are selected at once. In the present embodiment, it is assumed that the entire memory cell array includes at least one block of defective memory cell arrays including memory cells that malfunction in memory cell units, row units, column units, or block units. A defective block including a memory cell that causes an operation failure is treated as a non-selected block so as not to be selected in a predetermined test mode.

  In the test mode, prior to starting the test of each memory block 6, the non-selected state latch circuit 2b of the memory block 6 (non-selected block) that is not subjected to the test is fixed to the non-selected state. In the present embodiment, the block selection signal DECD is set to either the non-selected state or the reset state using the node / LR and the node LE of the non-selected state latch circuit 2b. Specifically, in this embodiment, when the node LE is changed from the L level to the H level when the H level voltage is input to the node / LR of the non-selected state latch circuit 2b, the signal LATD is changed to the H level ( When the node LE is at the L level and an L level voltage is input to the node / LR, the unselected state is released and the signal LATD becomes the L level (reset state). It is. The selection of the non-selected state latch circuit 2b fixed to the non-selected state is performed by the block decoder 2a using the signal DIN1 and the signal DIN2.

  To fix the non-selected state of the non-selected state latch circuit 2b, first, an H level voltage is input to the node / LR of the non-selected state latch circuit 2b of each memory block 6, and the non-selected state / reset state can be set. To make sure Next, in order to select the non-selected state latch circuit 2b to be fixed in the non-selected state, an address signal for specifying the non-selected block is input from the outside via the I / O 13. Then, the block address generation circuit 7 inputs the H level to the signal DIN1 and the signal DIN2 of the block decoder 2a of the memory block 6 corresponding to the block address signal among the input address signals. As a result, the block selection signal DECD of the selected block decoder 2a becomes L level, and the signal DECDB of the non-selected state latch circuit 2b becomes H level. Thereafter, when an H level is input to the node LE, in the selected memory block 6 (non-selected block), the signal LATD of the non-selected state latch circuit 2b becomes H level and becomes a non-selected state. Here, after the signal LATD is set to the H level, the node LE is set to the L level and fixed so that the latch data is not rewritten. If there are a plurality of non-selected blocks, the above-described processing is performed on all the non-selected blocks, and the non-selected state latch circuit 2b of the non-selected block is fixed to the non-selected state.

  After fixing the non-selection state latch circuit 2b of the non-selection block to the non-selection state, all the word lines of all the memory blocks 6 are selected at once, and the memory cell array 4 is tested. Specifically, in order to select all the word lines of all the memory blocks 6, the H level is input to the signals DIN 1 and DIN 2 of the block decoder 2 a of all the memory blocks 6 and the node XR of the row decoder 3. . At this time, in the memory block 6 in which the non-selected state latch circuit 2b is fixed in the non-selected state, since the signal LATD is fixed at the H level, both the signal DIN1 and the signal DIN2 are at the H level and the block selection signal DECD is Even at L, the signal BOUT is at L level. That is, all the word lines included in the memory block 6 in which the non-selected state latch circuit 2b is fixed to the non-selected state are in the non-selected state. Thereafter, by applying a predetermined voltage to the voltage VPX using the word line driving circuit 9, all the words of all the memory blocks 6 except the memory block 6 in which the non-selected state latch circuit 2b is fixed to the non-selected state are displayed. Tests can be performed on the lines in a batch.

  Here, after completion of the test, the selected state of all the memory blocks 6 is canceled, and the non-selected state latch circuit 2b is not selected for the memory block 6 in which the non-selected state latch circuit 2b is fixed to the non-selected state. Release the state and return to the reset state. Specifically, by setting the node / LR to L level, the signal LATD of the non-selected state latch circuit 2b of the non-selected block is changed from H level to L level, and the non-selected state latch circuit 2b is returned to the reset state.

  In the present embodiment, since a defective block is handled as a non-selected block, the device 1 of the present invention can test only the memory block 6 that operates normally. Thereby, for example, in the electrical stress application test, it is not necessary to consider the voltage drop due to the leakage current of the defective block, and the test of the normally operating memory block 6 excluding the defective block can be performed collectively. For this reason, for example, even when some memory areas cannot be used, an electrical stress application test can be performed, and conditions that are advantageous in terms of cost and delivery time are set compared to products that can use all memory cell areas. By doing so, it can be supplied as a product.

Second Embodiment
A second embodiment of the device 1 of the present invention will be described with reference to FIG. In the present embodiment, the case where the memory cell selection procedure in the test mode is different will be described.

  The operation of the device 1 of the present invention during the test mode in this embodiment will be described with reference to FIG. Here, FIG. 5 is a voltage waveform diagram showing the operation of the device 1 of the present invention in the test mode. In the first embodiment, the case where all the word lines of all the memory blocks 6 are set to the selected state has been described. However, in this embodiment, all the bit lines of all the memory blocks 6 are collectively collected. A case where the selected state is set will be described.

  In the test mode, first, in the non-selected block, the non-selected state latch circuit 2b is fixed to the non-selected state as in the first embodiment. Thereafter, in order to select all the bit lines of all the memory blocks 6, the H level is input to the signals DIN 1 and DIN 2 of the block decoder 2 a of all the memory blocks 6 and the node LYS of the local column decoder 5. To do. At this time, in the memory block 6 in which the non-selected state latch circuit 2b is fixed in the non-selected state, the signal LATD is fixed at the H level, so that the signal BOUT becomes the L level regardless of the block selection signal DECD. That is, all the bit lines included in the memory block 6 in which the non-selected state latch circuit 2b is fixed in the non-selected state are in the non-selected state. Thereafter, by applying a predetermined voltage to the node GCOL using the bit line driving circuit 11, all the memory blocks 6 except the memory block 6 in which the non-selected state latch circuit 2b is fixed to the non-selected state are Tests can be conducted collectively.

  Here, as in the first embodiment, after the test is completed, the selected state of all the memory blocks 6 is canceled, and the memory block 6 in which the non-selected state latch circuit 2b is fixed to the non-selected state is not selected. Release the state and return to the reset state. Specifically, by setting the node / LR to the L level, the signal LATD of the block decoder 2a of the non-selected block is changed from the H level to the L level, the non-selected state is released, and the reset state is set.

<Third Embodiment>
A third embodiment of the device 1 of the present invention will be described with reference to FIG. In the present embodiment, a case where the configuration of the memory cell array 4 is different from that of the first and second embodiments will be described. In the first and second embodiments, the case where all the memory blocks 6 constituting the memory cell array are simultaneously selected in a predetermined test mode has been described. However, in this embodiment, some of the plurality of memory blocks are selected. Description will be made assuming that 6 is simultaneously selected as the plane 20.

  Here, FIG. 6 is a block diagram showing a configuration of the device 1 of the present invention in the present embodiment. The device 1 of the present embodiment of the present embodiment is configured so that the entire memory cell array 4 includes a plurality of planes 20 in which two or more blocks are aggregated, and includes a plane address generation circuit 21. In the present embodiment, a description will be given on the assumption that the tests for all the memory blocks 6 in the selected plane 20 are collectively performed, and the other planes 20 are not tested. In the present embodiment, the address signal input from the outside of the device 1 of the present invention includes a plane address signal.

  As shown in FIG. 6, the plane 20 includes two or more memory blocks 6, a block address generation circuit 7, a row address generation circuit 8, a word line drive circuit 9, a column address generation circuit 10, a bit line drive circuit 11, and A global column decoder 12 is provided. Since these configurations and functions are the same as those in the first and second embodiments, the description thereof is omitted in this embodiment.

  The plane address generation circuit 21 decodes a plane address signal in the address signal and outputs a plane 20 selection signal to the plane 20 specified by the plane address signal. Thereby, only the plane 20 specified by the address signal can be accessed.

  Subsequently, the operation of the device 1 of the present invention in this embodiment will be described. In this embodiment, by selecting a predetermined plane 20 by an address signal, only the memory block 6 in the selected plane 20 is accessed.

  Specifically, during a normal access operation, the inventive device 1 of this embodiment has only the memory block 6 of the plane 20 specified by the address signal in FIG. 3 as in the first and second embodiments. Perform the indicated access action.

  In the test mode, the inventive device 1 of the present embodiment collectively performs a test on all the memory blocks 6 in the plane 20 for each plane 20 specified by the address signal. Then, the memory block 6 of the plane 20 specified by the address signal performs the operation shown in FIG. 4 or 5 as in the first or second embodiment. On the other hand, in the plane 20 that is not selected by the address signal, the signal for controlling the internal voltage is not effective and the standby state is maintained, and the test is not performed.

  In this embodiment, even if the memory block 6 in the selected plane 20 includes a defective block, the defective block is forcibly fixed to the non-selected state by the non-selected state latch circuit 2b. Thus, it is possible to collectively test the normally operating memory blocks 6 in the selected plane 20 without being aware of the defective blocks.

<Another embodiment>
Next, another embodiment of the device 1 of the present invention will be described.

  <1> In the third embodiment, the plane 20 is divided into the block address generating circuit 7, the row address generating circuit 8, the word line driving circuit 9, the column address generating circuit 10, the bit line driving circuit 11, and the global column decoder 12. However, these circuits are not necessarily provided in the plane 20 and may be provided outside the plane 20.

  <2> In each of the above embodiments, the block decoder 2 a is provided in the memory block 6. However, the present invention is not limited to this, and the block decoder 2 a may be provided outside the memory block 6.

  <3> Further, in each of the above embodiments, the non-selected state latch circuit 2b is provided in the memory block 6 as a pair with the block decoder 2a, but may be provided outside the memory block 6.

1 is a block diagram showing a configuration example of a semiconductor memory device according to the present invention. 1 is a circuit diagram showing a configuration example of a memory block of a semiconductor memory device according to the present invention. Voltage waveform diagram showing an example of normal operation of the semiconductor memory device according to the present invention Voltage waveform diagram showing an operation example of the semiconductor memory device according to the present invention in the test mode Voltage waveform diagram showing an operation example of the semiconductor memory device according to the present invention in the test mode The block diagram which shows the structure of 3rd Embodiment of the semiconductor memory device based on this invention. Circuit diagram showing a configuration example of a semiconductor memory device according to the prior art

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor memory device 2a Block decoder 2b Non-selection state latch circuit 3 Row decoder 4 Memory cell array 5 Local column decoder 6 Memory block 7 Block address generation circuit 8 Row address generation circuit 9 Word line drive circuit 10 Column address generation circuit 11 Bit line drive circuit 12 Global column decoder 13 I / O
20 plane 21 plane address generation circuit

Claims (9)

A semiconductor memory device in which a memory cell array in which a plurality of memory cells capable of storing data are arranged in a matrix in each of a row direction and a column direction is used as one block, and the entire memory cell array is configured by including a plurality of blocks of the memory cell array. Because
In order to select an arbitrary block from the entire memory cell array, the block address signal is decoded, one of the block selection signals associated with each block is selected, and all others are not selected. A block address decoder circuit which can be output in a state;
A non-selection state latch circuit for forcibly fixing the self block to the non-selection state regardless of the input state of the block selection signal for determining the selection state or non-selection state of the block for each block; ,
In the reset state where the non-selection state latch circuit is not fixed to the non-selection state, the selection state or non-selection state of each corresponding block is determined according to the input state of the block selection signal,
2. A semiconductor memory device according to claim 1, wherein the block address decoder circuit is configured to be capable of outputting a plurality of block selection signals in a selected state in a predetermined test mode. An individual block decoder circuit including a decoding circuit at the final stage that outputs at least the block selection signal in the block address decoder circuit is disposed adjacent to the corresponding block, respectively.
2. The semiconductor memory device according to claim 1, wherein the non-selected state latch circuit and the individual block decoder circuit are configured in pairs for each block.   3. The semiconductor memory device according to claim 1, wherein the non-selection state latch circuit is configured to be fixed to a non-selection state when the block selection signal of the corresponding block is in a selection state.   4. The semiconductor according to claim 1, wherein the non-selected state latch circuit is configured to be able to release the state fixed in the non-selected state and return to the reset state. 5. Storage device. Each memory cell array is configured such that the memory cells in the same row are connected to a common row selection line, and the memory cells in the same column are connected to a common column selection line,
5. In the predetermined test mode, all the row selection lines of the block selected by the block selection signal set and output in the selected state are set in the selected state. The semiconductor memory device according to any one of the above. Each memory cell array is configured such that the memory cells in the same row are connected to a common row selection line, and the memory cells in the same column are connected to a common column selection line,
5. In the predetermined test mode, all the column selection lines of the block selected by the block selection signal set and output in the selected state are set in the selected state. The semiconductor memory device according to any one of the above. The entire memory cell array is configured with a plurality of planes formed by aggregating two or more blocks,
7. The block address decoder circuit is configured such that, in a predetermined test mode, the block selection signal can be output by setting a selection state and a non-selection state of the block selection signal in units of the planes. The semiconductor memory device according to any one of the above.   2. The defective memory cell array including at least one block including the memory cell that causes an operation failure in a memory cell unit, a row unit, a column unit, or a block unit is included in the entire memory cell array. 8. The semiconductor memory device according to any one of items 7. A test method for a semiconductor memory device according to claim 8, comprising:
After fixing all the non-selected state latch circuits corresponding to the defective memory cell array to the non-selected state,
A test method for a semiconductor memory device, wherein, in the predetermined test mode, the block address decoder circuit controls to select all or a plurality of blocks of the entire memory cell array at the same time.