JP2006344920A - Printed circuit board, manufacturing method therefor, semiconductor chip mounting substrate, manufacturing method therefor, and semiconductor package - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a printed circuit board (mother board, semiconductor chip mounting substrate, multilayer interconnection board) and semiconductor package having excellent insulation reliability without causing bridges, and their manufacturing methods. <P>SOLUTION: The printed-circuit board has copper interconnect lines 1. An insulator 3 is formed between copper interconnect lines 1. Part of the insulator 3 formed between the copper interconnect lines 1 is removed, and part of the copper interconnect lines 1 is exposed. On the surface of the exposed copper interconnect line, either the structure of a nickel plating coat 4 and gold plating coat 6 in that order, or that of a nickel plating coat 4, palladium plating coat 5, and gold plating coat 6 in that order is formed. The semiconductor package is composed of the semiconductor mounting substrate with a semiconductor chip connector on one surface of the printed circuit board and external connector formed on the other surface, a semiconductor chip mounted on the semiconductor chip mounting substrate, and resin that seals the semiconductor chip. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a printed wiring board, a semiconductor chip mounting substrate, a semiconductor package, a printed wiring board manufacturing method, and a semiconductor chip mounting substrate manufacturing method.

  The development of the information society in recent years has been remarkable, and consumer devices have been reduced in size, weight, performance, and functionality, such as personal computers and mobile phones. Industrial equipment includes wireless base stations, optical communication devices, and servers. In addition, there is a demand for improvement in functions in the same way regardless of whether it is large or small, such as routers and other network-related devices. In addition, with the increase in the amount of information transmitted, the frequency of signals handled tends to increase year by year, and high-speed processing and high-speed transmission technology are being developed.

  With regard to mounting relations, the development of system-on-chip (SoC), system-in-package (SiP), etc., as new high-density mounting technologies, as well as higher-speed and higher-performance LSIs such as CPUs, DSPs, and various types of memory are actively developed. Has been done. For this reason, build-up type multilayer wiring boards have come to be used for semiconductor chip mounting boards and motherboards in order to cope with high frequency, high density wiring, and high functionality.

  Electronic device manufacturers have been competing in high-density packaging to achieve smaller, thinner, and lighter products, and rapid technological progress has been made in narrowing the multi-pin pitch of packages. From QFP (Quad Flat Package) to BGA (Ball Grid Array) / CSP (Chip Size Package) mounting on the surface. Gold wire bonding is generally used as a method for connecting a semiconductor chip and a semiconductor mounting substrate, and gold plating, which is an adhesive layer of gold wire, is required for terminals on the substrate side. With the increase in the speed and integration of semiconductor chips, the wiring on the substrate has become finer, and it is difficult to route the conductor wiring in conventional electroplating, so electroless plating that allows plating on independent patterns is possible The demand for is growing.

  However, when electroless nickel / gold plating is applied to copper wiring, the phenomenon of "bridge" in which electroless nickel plating is deposited not only on the copper wiring but also on the surrounding resin in the electroless nickel plating process Occurs, causing a short circuit failure in the wiring. Therefore, it is important to ensure insulation reliability between copper wirings after electroless nickel plating. In order to satisfy this characteristic, the following method has been performed as a conventional method.

There is a method (Patent Document 1) for preventing “bridge” by immersing a base material in a solution containing thiosulfate immediately before the electroless nickel pretreatment step. Further, there is a method (Patent Document 2) for preventing “bridge” by adding a water washing step after applying O ₂ plasma after copper wiring is formed.
Japanese Patent No. 3387507 Japanese Patent Laid-Open No. 11-40951

With the increase in the speed and integration of semiconductor chips, the wiring of the substrate has become finer, a relatively thin plating layer is formed on the surface, a plating resist is formed thereon, and wiring is performed by electroplating. A semi-additive method in which a relatively thin plating layer is removed by soft etching after forming a required thickness and the plating resist is peeled off is used. Wiring width / wiring interval (hereinafter referred to as L / S) = 35 μm. Products having fine wiring of / 35 μm level have been mass-produced. In either the method of immersing the substrate in a solution containing thiosulfate immediately before the electroless nickel pretreatment step, or the method of performing the water washing step after applying the O ₂ plasma after the copper wiring formation. There is a problem that the bridge suppressing effect is weak and abnormal deposition of electroless nickel plating occurs.

  The object of the present invention was made to improve the above-mentioned problems of the prior art, and a printed wiring board (for example, a motherboard, a multilayer wiring board) excellent in insulation reliability without occurrence of a bridge, A semiconductor chip mounting substrate, a semiconductor package, a printed wiring board manufacturing method, and a semiconductor chip mounting substrate manufacturing method are provided.

  In order to solve the above problems, a method for manufacturing a printed wiring board according to the present invention includes a step of forming an insulator between a plurality of copper wires, and after forming the insulator, nickel plating is performed on the plurality of copper wires. Forming a film and a gold plating film in order or forming a nickel plating film, a palladium plating film and a gold plating film in order.

  Here, after forming the nickel plating film, a gold plating film may be formed on the nickel plating film. Moreover, after forming a nickel plating film, you may form a palladium plating film and a gold plating film in order on a nickel plating film.

  In the printed wiring board manufacturing method of the present invention, the nickel plating film and the gold plating film, or the nickel plating film, the palladium plating film and the gold plating film are formed in a state where the insulator is disposed between the copper wirings. It is possible to manufacture a printed wiring board in which a bridge is not easily generated between them and the insulation between copper wirings is improved. The reason why the bridge is difficult to occur is considered as follows, for example.

  If metal residues such as Cu, Cr, Pd, etc. exist between a plurality of copper wirings, it is considered that abnormal precipitation of nickel occurs with the metal residues as nuclei. On the other hand, in the method for manufacturing a printed wiring board according to the present invention, since such a metal residue is covered with an insulator, it is possible to suppress the occurrence of a bridge due to abnormal precipitation of nickel.

  In addition, when nickel plating is performed, abnormal plating of nickel may occur due to, for example, accumulation of hydrogen gas due to poor stirring efficiency of the plating solution between a plurality of copper wirings. On the other hand, in the method for manufacturing a printed wiring board according to the present invention, hydrogen gas does not easily accumulate between copper wirings due to the insulator, so that the occurrence of bridges due to abnormal nickel precipitation can be suppressed.

  Further, the step of forming the insulator includes a step of forming an insulator covering the plurality of copper wirings, and a step of removing a part of the insulators such that a part of the plurality of copper wirings is exposed. It is preferable to contain. Thereby, an insulator can be easily formed between a plurality of copper wirings.

  In addition, when removing a part of the insulator, it is preferable to use at least one of a dry etching process, a wet etching process, and a mechanical polishing process. Thereby, a part of insulator can be removed easily.

  In the dry etching process, anisotropic etching is preferably performed. In this case, an insulator tends to remain on the side surface of the copper wiring.

  In the wet etching process, a solution containing at least one of chromic acid, chromate, dichromate, manganate, permanganate, ozone, hydrogen peroxide / sulfuric acid, and nitric acid is used. It is preferable. In this case, since the etching rate of the insulator is increased, a part of the insulator can be removed in a short time.

  In the process by mechanical polishing, it is preferable to use at least one of buffalo, sandpaper, and sandblast. Thereby, a part of insulator can be removed easily.

  Moreover, it is preferable that the said insulator has a thermosetting organic insulating material as a main component. Thereby, an insulator can be formed easily.

  In the manufacturing method of the semiconductor chip mounting substrate of the present invention, the plurality of copper wirings provided on one surface of the printed wiring board manufactured by the manufacturing method of the printed wiring board of the present invention are connected to the semiconductor chip. The plurality of copper wirings provided on the other surface of the printed wiring board are external connection terminals.

  In the method for manufacturing a semiconductor chip mounting substrate of the present invention, the above-described method for manufacturing a printed wiring board of the present invention is used. For this reason, in the obtained semiconductor chip mounting substrate, it is difficult for bridges to occur between the copper wirings, and the insulation between the copper wirings is improved.

  The printed wiring board of the present invention includes a plurality of copper wirings, a nickel plating film and a gold plating film sequentially provided on the plurality of copper wirings, or a nickel plating film sequentially provided on the plurality of copper wirings, palladium A plating film and a gold plating film; and an insulator disposed between the plurality of copper wirings.

  Here, a gold plating film may be provided on the nickel plating film. A palladium plating film may be provided between the nickel plating film and the gold plating film.

  In the printed wiring board of the present invention, it is difficult for a bridge to occur between the copper wirings, and the insulation between the copper wirings is improved.

  Moreover, it is preferable that the said insulator has a thermosetting organic insulating material as a main component. Thereby, an insulator can be formed easily.

  A semiconductor chip mounting board of the present invention includes the printed wiring board of the present invention, and the plurality of copper wirings provided on one surface of the printed wiring board are semiconductor chip connection terminals for connecting to the semiconductor chip. The plurality of copper wirings provided on the other surface of the printed wiring board are external connection terminals.

  A semiconductor chip mounting board of the present invention includes the printed wiring board. For this reason, in the semiconductor chip mounting substrate of the present invention, a bridge is hardly generated between the copper wirings, and the insulation between the copper wirings is improved.

  A semiconductor package of the present invention includes the semiconductor chip mounting substrate of the present invention and the semiconductor chip mounted on the semiconductor chip mounting substrate.

  A semiconductor package of the present invention includes the semiconductor chip mounting substrate. For this reason, in the semiconductor package of this invention, a bridge | bridging does not occur easily between copper wiring, and the insulation between copper wiring improves.

  In order to achieve the above object, an insulator is formed between the copper wirings, a part of the insulating material between the copper wirings is removed to expose a part of the copper wirings, and the exposed parts are exposed. Basically, the present invention is configured as follows, for example, in the order of nickel plating film, gold plating film, or nickel plating film, palladium plating film, gold plating film on the copper wiring. The

(1) An insulating material is formed between the copper wiring, a part of the insulating material between the copper wiring is removed, a part of the copper wiring is exposed, and the exposed copper wiring is nickel-plated on the surface A printed wiring board having a copper wiring having a structure formed in the order of a film, a gold plating film, or a nickel plating film, a palladium plating film, and a gold plating film.
(2) The print according to (1), wherein a part of the insulator between the copper wirings is removed by at least one of a dry etching process, a wet etching process, and a process by mechanical polishing. Wiring board.

(3) The printed wiring board according to (2), wherein the dry etching process is an anisotropic etching process.
(4) The wet etching process includes a solution containing at least one oxidizer of chromic acid, chromate, dichromate, manganate, permanganate, ozone, hydrogen peroxide / sulfuric acid, and nitric acid. The printed wiring board according to (2), wherein the processing is performed by the following.
(5) The printed wiring board according to (2), wherein the process by mechanical polishing is performed by using buffalo, sandpaper, or sandblast.

(6) The printed wiring board according to any one of (1) to (5), wherein the insulator includes a thermosetting organic insulating material as a main component.
(7) The printed wiring board according to any one of (1) to (6), wherein a semiconductor chip connection terminal is formed on one surface of the printed wiring board, and an external connection terminal is formed on the other surface. A semiconductor chip mounting substrate characterized by the above.
(8) A step of forming an insulator between the copper wires, a step of removing a part of the insulator between the copper wires and exposing a part of the copper wires, nickel on the surface of the exposed copper wires A method for producing a printed wiring board comprising a step of forming a plating film, a gold plating film, or a nickel plating film, a palladium plating film, and a gold plating film.

(9) The printed wiring according to (8), wherein the step of removing a part of the insulator between the copper wirings is at least one of a dry etching process, a wet etching process, and a process by mechanical polishing. A method for manufacturing a substrate.
(10) The printed wiring board manufacturing method according to (9), wherein the dry etching process is an anisotropic etching process.
(11) A solution in which the wet etching process includes at least one oxidizing agent of chromic acid, chromate, dichromate, manganate, permanganate, ozone, hydrogen peroxide / sulfuric acid, and nitric acid. (9) The printed wiring board manufacturing method as described in (9) above.

(12) The method for manufacturing a printed wiring board according to (9), wherein the process by mechanical polishing is performed using buffalo, sandpaper, or sandblast.
(13) The method for manufacturing a printed wiring board according to any one of (8) to (12), wherein the insulator includes a thermosetting organic insulating material as a main component.
(14) The printed wiring board according to any one of (8) to (13), wherein a semiconductor chip connection terminal is formed on one surface of the printed wiring board and an external connection terminal is formed on the other surface. The manufacturing method of the semiconductor chip mounting board | substrate characterized by further having a process.
(15) A semiconductor chip mounting substrate described in (7) or a semiconductor chip mounting substrate manufactured by the method for manufacturing a semiconductor chip mounting substrate described in (14), a semiconductor chip mounted on the semiconductor chip mounting substrate, A semiconductor package comprising a resin for sealing the semiconductor chip.

  According to the present invention, there is provided a printed wiring board, a semiconductor chip mounting board, a semiconductor package, a printed wiring board manufacturing method, and a semiconductor chip mounting board manufacturing method that are excellent in insulation reliability without occurrence of a bridge. The

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. Here, the semiconductor chip mounting substrate will be mainly described. However, a method of forming an insulator between the copper wiring and a method of removing a part of the insulator between the copper wiring and exposing a part of the copper wiring. The wiring surface treatment method, the interlayer insulating layer (build-up layer) forming method, and the like can be similarly performed on a multilayer wiring board. In the description of the drawings, the same reference numerals are used for the same or equivalent elements, and duplicate descriptions are omitted.

(Printed wiring board manufacturing method)
Hereinafter, a method for manufacturing a printed wiring board according to the embodiment will be described. The method for manufacturing a printed wiring board according to this embodiment includes a step of forming an insulator between a plurality of copper wirings, and after forming the insulator, a nickel plating film and a gold plating film on the plurality of copper wirings Or sequentially forming a nickel plating film, a palladium plating film, and a gold plating film. The step of forming the insulator preferably includes a step of forming an insulator covering the plurality of copper wirings and a step of removing a part of the insulator so that a part of the plurality of copper wirings is exposed. .

(Insulator)
As the insulator, a thermosetting resin, a thermoplastic resin, or a mixed resin thereof can be used. In particular, it is preferable to use a thermosetting organic insulating material as a main component. Thermosetting resins include phenolic resin, urea resin, melamine resin, alkyd resin, acrylic resin, unsaturated polyester resin, diallyl phthalate resin, epoxy resin, polybenzimidazole resin, polyamide resin, polyamideimide resin, silicone resin, cyclohexane Resin synthesized from pentadiene, resin containing tris (2-hydroxyethyl) isocyanurate, resin synthesized from aromatic nitrile, trimerized aromatic dicyanamide resin, resin containing triallyl trimetallate, furan resin, ketone resin, A xylene resin, a thermosetting resin containing a condensed polycyclic aromatic, a benzocyclobutene resin, or the like can be used. Examples of the thermoplastic resin include polyimide resin, polyphenylene oxide resin, polyphenylene sulfide resin, aramid resin, and liquid crystal polymer.

  The step of forming an insulator covering the plurality of copper wirings is performed as follows, for example.

(Insulator coating and curing method)
Insulating material can be applied to a substrate using a coating device such as a roll coater, slit die coater, dip coater, spin coater or screen printing, or to a substrate by spray spraying. It is not limited to. In the case of using a thermosetting resin, it is a usual method to harden after applying an insulating material, but it is more preferable to cure after placing in a vacuum state or in a vacuum state.

  For the formation of the insulator, the coating → drying process can be repeated several times. It is also possible to semi-cure after applying an insulating material, to bond a carrier film or copper foil by a laminating method or the like, and to cure by pressing. The bonding of the carrier film or the copper foil is preferably a vacuum roll laminating method, and more preferably cured by a vacuum press.

  In addition, an uncured or semi-cured insulator coated on one side of a carrier film or copper foil can be attached to a substrate by a laminating method or the like, and the insulator can be bonded to the substrate. As the carrier film, a polyimide film is preferable from the viewpoint of heat resistance, and in particular, a polyimide film in which copper is formed on the surface by vapor deposition or sputtering is preferable. Moreover, about a copper foil, it is preferable to make a shiny surface side and an insulator contact, and the thing without a rust prevention metal is more preferable.

  The step of removing a part of the insulator is performed as follows, for example.

(Insulator removal process)
As a method of removing a part of the insulator between the copper wirings, it can be removed by at least one of a dry etching process, a wet etching process, and a mechanical polishing process, and these processes should be performed in combination as appropriate. Is more preferable. In removing part of the insulator, it is preferable to use at least one of a dry etching process, a wet etching process, and a process by mechanical polishing.

(Dry etching process)
The dry process for removing a part of the insulating material between the copper wirings is a plasma etching method, a reactive ion etching (RIE) method, a reactive ion beam etching (RIBE) method, or an atmospheric pressure plasma etching method. Good. An anisotropic etching method is particularly preferable. That is, it is preferable to perform anisotropic etching in the dry etching process. Examples of the apparatus used for the plasma etching method include a barrel type, a parallel plate type, and a down flow type apparatus, and are not particularly limited. The apparatus used for the reactive ion etching (RIE) method includes a parallel plate type, a magnetron type, a two-frequency type, an ECR type, a helicon type, and an ICP type apparatus, and is not particularly limited. Examples of the apparatus used for the reactive ion beam etching (RIBE) method include an ECR type, a Kaufman type, and an ICP type apparatus, and are not particularly limited. In any case, an etching gas can be appropriately selected, and any of an inorganic gas, an organic compound vapor, or a mixture thereof can be used.

Examples of the inorganic gas include He, Ne, Ar, Kr, Xe, N ₂ , NO, N ₂ O, CO, CO ₂ , NH ₃ , SO ₂ , Cl ₂ , freon gas (CF ₄ , CH ₂ F ₂ , C ₄ F ₆ , C ₅ F ₈ , CHF ₃ , CH _3, etc.), or a mixed gas thereof, and a mixed gas in which O ₂ or O ₃ is mixed into these gases. Among these, Ar is a more preferable gas because a stable resin surface can be obtained. The organic compound vapor is not particularly limited, and examples thereof include an organic silicon compound, an unsaturated compound such as acrylic acid, an organic nitrogen compound, an organic fluorine compound, and a general organic solvent. It is also preferable to mix an appropriate amount of organic compound vapor in Ar gas so as to obtain an appropriate vapor pressure.

(Wet etching process)
As a wet etching process for removing a part of the insulating material between the copper wirings, there is a method of treating with an alkaline solution, a solution containing an oxidizing agent, or a combination thereof, and the insulating material is 1 μm or more. What is necessary is just the process by the solution to etch. In particular, a solution containing at least one oxidizing agent such as chromic acid, chromate, dichromate, manganate, permanganate, ozone, hydrogen peroxide / sulfuric acid, and nitric acid is more preferable. That is, in wet etching, chromic acid, chromate, dichromate, manganate, permanganate, ozone, hydrogen peroxide / sulfuric acid (solution containing hydrogen peroxide and sulfuric acid), and nitric acid. It is preferable to use a solution containing at least one kind. As the alkaline solution, at least one compound containing an amino group such as alkali metal or alkaline earth metal hydroxide such as sodium hydroxide, potassium hydroxide or sodium carbonate, ethylenediamine, methylamine or 2-aminoethanol is used. A solution containing the above can be used, and a solution containing a complexing agent is preferable.

(Process by mechanical polishing)
As a process by mechanical polishing, a process using buffalo, sandpaper, sandblast, or the like is possible, and any mechanical polishing may be used without particular limitation. In the process by mechanical polishing, it is preferable to use at least one of buffalo, sandpaper, and sandblast. The surface roughness of the copper wiring after the mechanical polishing is preferably less than 1.5 μm in Ra, more preferably less than 1.0 μm, and even more preferably less than 0.4 μm. . It is more preferable to perform chemical polishing after performing mechanical polishing and exposing the upper part of the copper wiring. As this chemical polishing liquid, nitric acid-sulfuric acid-hydrochloric acid polishing liquid, nitric acid-sulfuric acid-hydrochloric acid-chromic acid polishing liquid, nitric acid-based polishing liquid, phosphoric acid-based polishing liquid, chromic acid-based polishing liquid, sulfuric acid-based polishing liquid, A hydrogen peroxide-based polishing liquid, sulfuric acid / hydrogen peroxide-based polishing liquid, copper chloride-based polishing liquid, iron chloride-based polishing liquid, ammonia persulfate-based polishing liquid, ammonia / alkali-based polishing liquid, and the like can be used.

(Nickel plating film)
The nickel plating film is a nickel alloy such as Ni-P, Ni-P-Cu, Ni-B, Ni-P-B-W, or pure Ni, as long as it contains nickel. Not limited. Moreover, the film of nickel or an alloy containing nickel may be formed by electroplating, and is more preferably formed by electroless plating. The thickness of the nickel plating film is preferably 0.5 μm to 10 μm. If the thickness is less than 0.5 μm, the success rate of wire bonding after heat treatment tends to decrease. The upper limit is determined by L / S, but is preferably up to 10 μm.

(Palladium plating film)
The palladium plating film may be formed by displacement palladium plating, electroless palladium plating, or a combination thereof. The palladium film may be formed by electroplating. The thickness of the palladium plating film is preferably 0.05 μm to 2 μm. If it is less than 0.05 μm, the success rate of wire bonding after the heat treatment tends to decrease. Also, the upper limit is limited almost exclusively for economic reasons, and is usually preferably up to 2 μm.

(Gold plating film)
The gold plating film may be formed by performing electroless gold plating after performing displacement gold plating or displacement gold plating. The gold plating film may be formed by electroplating. The thickness of the gold plating film is preferably 0.04 μm to 2 μm. If the thickness is less than 0.04 μm, the success rate of wire bonding after heat treatment tends to decrease. Also, the upper limit is limited almost exclusively for economic reasons, and is usually preferably up to 2 μm.

(Printed wiring board)
(Insulator structure formed by forming an insulator between copper wiring and removing part of the insulation between the copper wiring)
The structure of the insulator formed by forming an insulator between the copper wiring and removing a part of the insulator between the copper wiring is not particularly limited, but FIG. 1B and FIG. It is preferable that the structure is as shown in FIG. 3 (b) and FIG. 4 (c).

  The printed wiring board according to the embodiment includes a plurality of copper wirings 1 and a plurality of copper wirings 1 as shown in FIG. 1 (c), FIG. 2 (c), FIG. 3 (c), and FIG. A nickel plating film 4, a palladium plating film 5, and a gold plating film 6 provided in this order, and an insulator 3 disposed between the plurality of copper wirings 1 are provided. The copper wiring 1 is provided on the core substrate 2. Further, a palladium plating film 5 is preferably provided on the nickel plating film 4, and a gold plating film 6 is preferably provided on the palladium plating film 5. In such a printed wiring board, a bridge is not easily generated between the copper wirings 1, and the insulation between the copper wirings 1 is improved.

  Hereinafter, the manufacturing method of the printed wiring board according to the embodiment will be described in detail with reference to FIGS.

(Method to remove part of the insulation between copper wiring)
A first method of forming an insulator between copper wirings and removing a part of the insulator between the copper wirings to expose a part of the copper wiring will be described with reference to FIG.
A thermosetting resin, a thermoplastic resin, or a varnish of a mixed resin thereof is applied onto a copper wiring by a coater such as a roll coater, a slit die coater, a dip coater, a spin coater, a screen printing, or spray printing, and cured. Then, an insulator having a cross-sectional shape as shown in FIG. Thereby, an insulator covering the plurality of copper wirings is formed. At this time, it is preferable to appropriately select the viscosity of the insulator and the number of coatings so that the thickness of the insulating film on the copper wiring is sufficiently thinner than the thickness of the insulating material on the resin between the copper wirings. Next, as shown in FIG. 1B, a part of the insulator between the copper wirings is removed by anisotropic etching to expose a part of the copper wiring. Thereby, a part of the insulator is removed so that a part of the plurality of copper wirings is exposed.

A second method of forming an insulator between the copper wirings and removing a part of the insulator between the copper wirings to expose a part of the copper wiring will be described with reference to FIG.
A curable resin, a thermoplastic resin, or a varnish of a mixed resin thereof is applied onto a copper wiring by a coater such as a roll coater, a slit die coater, a dip coater, a spin coater, or a screen printing or spray spraying and semi-cured. . Next, a carrier film or copper foil is bonded by a roll laminating method, cured by pressing, and the thickness of the insulating film on the upper part of the copper wiring as shown in FIG. An insulator having a cross-sectional shape that is sufficiently thinner than an object is formed. Thereby, an insulator covering the plurality of copper wirings is formed.

  The carrier film is preferably laminated by a vacuum roll laminating method, and more preferably cured by a vacuum press. As the carrier film, a polyimide film is preferable from the viewpoint of heat resistance, and in particular, a polyimide film in which copper is formed on the surface by vapor deposition or sputtering is preferable. Moreover, about a copper foil, it is preferable to make a shiny surface side and an insulator contact, and the thing without a rust prevention metal is more preferable. Next, as shown in FIG. 2B, a part of the insulator between the copper wirings is removed to expose a part of the copper wirings by a dry etching process, a wet etching process, or a process combining them. Thereby, a part of the insulator is removed so that a part of the plurality of copper wirings is exposed.

A third method of forming an insulator between copper wirings and removing a part of the insulator between the copper wirings to expose a part of the copper wiring will be described with reference to FIG.
Apply varnish of curable resin, thermoplastic resin or mixed resin on copper wiring by roll coater, slit die coater, dip coater, spin coater, screen printing etc. or spray spray or uncured Alternatively, a cross-section as shown in FIG. 3 (a) can be obtained by applying a semi-cured insulator applied to one side of a carrier film or copper foil to a substrate by a roll laminating method and bonding the insulator to the substrate. Form a shaped insulator. Thereby, an insulator covering the plurality of copper wirings is formed. Next, the insulator is polished by a mechanical polishing process such as buffalo, sandpaper, sandblast, etc., and finally a part of the resin between the upper part of the copper wiring and the copper wiring is polished. As shown in FIG. 2, a part of the copper wiring is exposed. Thereby, a part of the insulator is removed so that a part of the plurality of copper wirings is exposed.

With reference to FIG. 4, a fourth method of forming an insulator between the copper wirings and removing a part of the insulator between the copper wirings to expose a part of the copper wiring will be described.
Apply varnish of curable resin, thermoplastic resin or mixed resin on copper wiring by roll coater, slit die coater, dip coater, spin coater, screen printing etc. or spray spray or uncured Alternatively, a semi-cured insulator coated on one side of a carrier film or copper foil is bonded to a substrate by a roll laminating method, and the insulator is adhered to the substrate, whereby the cross section as shown in FIG. Form a shaped insulator. Thereby, an insulator covering the plurality of copper wirings is formed.

  Next, the insulator is polished by a mechanical polishing process such as buffalo, sandpaper, sandblasting, etc., and a film thickness of 1 μm to 30 μm, preferably 1 μm to 20 μm, more preferably 1 μm on the upper part of the copper wiring. By forming a film thickness of 10 μm to 10 μm, the insulator is polished so as to finally have a cross-sectional shape as shown in FIG. Next, as shown in FIG. 4C, a part of the insulator between the copper wirings is removed to expose a part of the copper wirings by a dry etching process, a wet etching process, or a process combining them. . Thereby, a part of the insulator is removed so that a part of the plurality of copper wirings is exposed.

(Plating film formed on the surface of copper wiring exposed by removing part of the insulation between copper wiring)
As the plating film formed on the exposed copper wiring surface after removing some of the insulation between the copper wiring, the order of nickel plating film, gold plating film, or the order of nickel plating film, palladium plating film, gold plating film Although the shape is not particularly limited, it is preferable that the shape is as shown in FIGS. 1C, 2C, 3C, and 4D. Thereby, a nickel plating film etc. are formed on a plurality of copper wirings.

(Pretreatment of copper wiring surface before insulator formation)
As the copper wiring surface treatment before forming the insulator, the copper wiring surface irregularity forming treatment, Si-O-Si forming treatment, coupling agent treatment, photocatalyst particle application treatment, adhesion improver treatment, corrosion inhibitor treatment, etc. It is possible to perform the process.

(Method for forming irregularities on the surface of copper wiring)
As a method for forming irregularities on the surface of the copper wiring, there are a method using an acidic solution, a method using an alkaline solution, and a method using a treatment liquid having an oxidizing agent or a reducing agent.

(Acid solution)
As the acidic solution, a compound selected from hydrochloric acid, sulfuric acid, nitric acid, phosphoric acid, acetic acid, formic acid, cupric chloride, ferric sulfate and other iron compounds, alkali metal chlorides, ammonium persulfate, etc., or a combination thereof You may process by aqueous solution or the aqueous solution containing acidic hexavalent chromium, such as chromic acid, chromic acid-sulfuric acid, chromic acid-hydrofluoric acid, dichromic acid, dichromic acid-borohydrofluoric acid. Regarding the concentration and treatment time of these treatment liquids, it is preferable to select and use conditions appropriately so that the surface roughness Ra is 0.01 μm to 0.4 μm.

(Alkaline solution)
As the alkaline solution, a hydroxide solution of an alkali metal or alkaline earth metal such as sodium hydroxide, potassium hydroxide, or sodium carbonate can be used, and these solutions are added with an organic acid, a chelating agent, or the like. It is also possible to use it. Regarding the concentration and treatment time of these treatment liquids, it is preferable to select and use conditions appropriately so that the surface roughness Ra is 0.01 μm to 0.4 μm.

(Treatment liquid with oxidizing agent or reducing agent)
The copper wiring may be immersed in an aqueous solution containing an oxidizing agent to form a copper oxide film on the copper surface, and then the copper oxide film may be reduced by a reduction treatment to form a fine uneven shape on the copper wiring surface. In that case, after processing using the acidic or alkaline solution, it is possible to perform the processing in combination, and the processing may be performed so that the surface roughness Ra is 0.01 μm to 0.4 μm. . As the aqueous solution containing the oxidizing agent, an oxidizing agent such as sodium chlorite can be used, and an aqueous solution containing an OH anion source and a buffering agent such as trisodium phosphate is preferable.

The aqueous solution for the reduction treatment is an aqueous solution in which formaldehyde, paraformaldehyde, paraformaldehyde, an aromatic aldehyde compound is added to an alkaline solution adjusted to pH 9.0 to 13.5, or hypophosphorous acid and hypophosphorous acid. An aqueous solution containing an acid salt or the like can be used.
Moreover, it is preferable to perform the degreasing process which cleans the wiring surface using a solvent, acidic aqueous solution, or alkaline aqueous solution as pre-processing of these processes. The degreasing treatment is not particularly limited as long as alkaline and acidic aqueous solutions are used, but the acidic aqueous solution or the alkaline aqueous solution is preferable. Furthermore, it is preferable to clean the wiring surface with a 1-5 N sulfuric acid aqueous solution. The degreasing treatment and the sulfuric acid cleaning may be appropriately combined.

(Formation of Si-O-Si)
As the compound having a Si—O—Si bond, silica glass, a compound having a ladder structure, and the like are preferable.

(Silica glass)
Silica glass (SiO ₂ ) has a thickness of 0.002 μm to 5 μm, preferably 0.005 μm to 1 μm, and more preferably 0.01 μm to 0.2 μm. When the thickness of the silica glass is 5.0 μm or more, via processing by a laser or the like in the via hole forming process tends to be difficult, and when the thickness is less than 0.002 μm, formation of the silica glass layer tends to be difficult.

(Compound containing ladder structure)
The compound containing a ladder structure is a compound containing a ladder structure represented by the general formula (1), wherein each R is independently a hydrogen atom, a reactive group, a hydrophilic group, or a hydrophobic group. It can be chosen. As reactive groups, amino groups, hydroxyl groups, carboxyl groups, epoxy groups, mercapto groups, thiol groups, oxazoline groups, cyclic ester groups, cyclic ether groups, isocyanate groups, acid anhydride groups, ester groups, amino groups , Formyl group, carbonyl group, vinyl group, hydroxy-substituted silyl group, alkoxy-substituted silyl group, halogen-substituted silyl group and the like.

  Examples of hydrophilic groups include polysaccharide groups, polyether groups, hydroxyl groups, carboxyl groups, sulfuric acid groups, sulfonic acid groups, phosphoric acid groups, phosphonium bases, heterocyclic groups, amino groups, salts and esters thereof. Examples of the hydrophobic group include compounds selected from an aliphatic hydrocarbon group having 1 to 60 carbon atoms, an aromatic hydrocarbon group having 6 to 60 carbon atoms, a heterocyclic group, and a polysiloxane residue. Of these, a reactive group is most preferred.

（式中、Ｒはそれぞれが単独に、水素原子、反応性基、親水性基または疎水性基から選択されたもの）

(Wherein each R is independently selected from a hydrogen atom, a reactive group, a hydrophilic group or a hydrophobic group)

(Coupling agent)
As the treatment of the copper wiring surface, it is possible to perform the treatment using a solution containing a coupling agent. Furthermore, after the compound having the Si—O—Si bond is formed on the surface of the copper wiring, the treatment can be performed using a solution containing a coupling agent. The content of the coupling agent is preferably 0.01% by weight to 5% by weight and more preferably 0.1% by weight to 1.0% by weight with respect to the entire solution. By using the coupling agent, the adhesion strength between the copper wiring and the insulator can be improved.

  Examples of the coupling agent to be used include a silane coupling agent, an aluminum coupling agent, a titanium coupling agent, and a zirconium coupling agent. Among them, a silane coupling agent is preferable, for example, a silane coupling agent is , Having a functional group such as an epoxy group, amino group, mercapto group, imidazole group, vinyl group, or methacryl group in the molecule, and containing at least one of these silane coupling agents or a mixture of two or more thereof A solution can be used. As the solvent used for preparing the silane coupling agent solution, water, alcohol, ketones, or the like can be used. A small amount of acid such as acetic acid or hydrochloric acid can be added to promote hydrolysis of the coupling agent.

  The content of the coupling agent is preferably 0.01% by weight to 5% by weight and more preferably 0.1% by weight to 1.0% by weight with respect to the entire solution. The treatment with the coupling agent can be carried out by a method such as immersion, spray spraying, coating, etc. in the coupling agent solution prepared as described above. The substrate treated with the above silane coupling agent is dried by natural drying, heat drying, or vacuum drying. Depending on the type of coupling agent used, it may be washed with water or ultrasonically before drying. It is.

(Photocatalyst particles)
After the compound having the Si—O—Si bond described above is formed, TiO ₂ , ZnO, SrTiO ₃ , CdS, GaP, InP, GaAs, BaTiO ₃ , BaTi ₄ O ₉ , K ₂ NbO ₃ , Nb ₂ O ₅ , Fe ₂ O ₃ , Ta ₂ O ₅ , K ₃ Ta ₃ Si ₂ O ₃ , WO ₃ , SnO ₂ , Bi ₂ O ₃ , BiVO ₄ , NiO, Cu ₂ O, SiC, MoS ₂ , InPb, RuO ₂ It is also possible to apply photocatalyst particles that are layered oxides containing at least one element selected from Ti, Nb, Ta, V, and CeO ₂ . Of these catalysts, TiO ₂ which is harmless and excellent in chemical stability is most preferable. As TiO ₂ , any of anatase, rutile and brookite can be used.

  In the compound containing the ladder structure represented by the general formula (1), the photocatalyst particles can be mixed and applied. Further, the photocatalyst particles can be used before, after, or before and after the treatment with the silane coupling agent, or further mixed in the silane coupling agent. After the photocatalyst particles are applied and dried, heat treatment and light irradiation can be performed as necessary. As the type of light irradiation, ultraviolet light, visible light, and infrared light can be used, but it is most preferable to use ultraviolet light.

(Adhesion improver)
As the adhesion improving agent, a thermosetting resin, a thermoplastic resin, or a mixed resin thereof can be used, but a thermosetting organic insulating material is preferably a main component. Adhesion improvers include phenol resin, urea resin, melamine resin, alkyd resin, acrylic resin, unsaturated polyester resin, diallyl phthalate resin, epoxy resin, polybenzimidazole resin, polyamide resin, polyamideimide resin, silicone resin, cyclohexane Resin synthesized from pentadiene, resin containing tris (2-hydroxyethyl) isocyanurate, resin synthesized from aromatic nitrile, trimerized aromatic dicyanamide resin, resin containing triallyl trimetallate, furan resin, ketone resin, A xylene resin, a thermosetting resin containing a condensed polycyclic aromatic, a benzocyclobutene resin, a fluorine resin, a polyimide resin, a polyphenylene oxide resin, a polyphenylene sulfide resin, an aramid resin, a liquid crystal polymer, or the like can be used.

(Corrosion inhibitor)
It is possible to apply a corrosion inhibitor to at least a part of the copper wiring surface, and the corrosion inhibitor only needs to contain at least one S-containing organic compound or N-containing organic compound. Specific examples of the corrosion inhibitor herein include compounds containing a sulfur atom such as a mercapto group, sulfide group, or disulfide group, or N containing —N═, N═N, or —NH ₂ in the molecule. It is a compound containing at least one organic compound, and can be used in addition to the acidic solution, the alkaline solution or the coupling agent solution described above, before or after the treatment with the solution containing the coupling agent, It is possible to perform the treatment using a solution containing a corrosion inhibitor.

(Compounds containing sulfur atoms such as mercapto groups, sulfide groups, or disulfide groups)
Examples of the compound containing a sulfur atom such as a mercapto group, a sulfide group, or a disulfide group include aliphatic thiols (HS— (CH ₂ ) _n —R (wherein n is an integer from 1 to 23, R Represents a monovalent organic group, a hydrogen group or a halogen atom), and R is preferably an amino group, an amide group, a carboxyl group, a carbonyl group or a hydroxyl group, It is not limited to this, C1-C18 alkyl group, C1-C8 alkoxy group, acyloxy group, haloalkyl group, halogen atom, hydrogen group, thioalkyl group, thiol group, and may be substituted. A phenyl group, a biphenyl group, a naphthyl group, a heterocyclic ring, etc. are mentioned.

  Further, the amino group, amide group, carboxyl group, and hydroxyl group in R may be one, preferably one or more, and may further have a substituent such as the above alkyl group. In the formula, it is preferable to use a compound in which n is an integer from 1 to 23, more preferably a compound in which n is an integer from 4 to 15, and n is an integer from 6 to 12. Particular preference is given to the compounds shown. These compounds include thiazole derivatives (thiazole, 2-aminothiazole, 2-aminothiazole-4-carboxylic acid, aminothiophene, benzothiazole, 2-mercaptobenzothiazole, 2-aminobenzothiazole, 2-amino-4- Methylbenzothiazole, 2-benzothiazolol, 2,3-dihydroimidazo [2,1-b] benzothiazol-6-amine, ethyl 2- (2-aminothiazol-4-yl) -2-hydroxyiminoacetate 2-methylbenzothiazole, 2-phenylbenzothiazole, 2-amino-4-methylthiazole, etc.), thiadiazole derivatives (1,2,3-thiadiazole, 1,2,4-thiadiazole, 1,2,5-thiadiazole) 1,3,4-thiadiazole, 2-amino-5-ethyl 1,3,4-thiadiazole, 5-amino-1,3,4-thiadiazole-2-thiol, 2,5-mecapto-1,3,4-thiadiazole, 3-methylmercapto-5-mercapto-1,2 , 4-thiadiazole, 2-amino-1,3,4-thiadiazole, 2- (ethylamino) -1,3,4-thiadiazole, 2-amino-5-ethylthio-1,3,4-thiadiazole), Mercaptobenzoic acid, mercaptonaphthol, mercaptophenol, 4-mercaptobiphenyl, mercaptoacetic acid, mercaptosuccinic acid, 3-mercaptopropionic acid, thiouracil, 3-thiourazole, 2-thiouramil, 4-thiouramil, 2-mercaptoquinoline, thioformic acid, 1-thiocoumarin, thiocumothiazone, thiocresol, thiosalicy Acid, thiothianuric acid, thionaphthol, thiotolene, thionaphthene, thionaphthene carboxylic acid, thionaphthenequinone, thiobarbituric acid, thiohydroquinone, thiophenol, thiophene, thiophthalide, thiobutene, thiolthione carbonate, thiolutidone, thiolhistidine, 3-carboxypropyl disulfide 2-hydroxyethyl disulfide, 2-aminopropionic acid, dithiodiglycolic acid, D-cysteine, di-t-butyl disulfide, thiocyan, thiocyanic acid and the like.

(Compound containing at least one N-containing organic compound containing —N═ or N═N or —NH ₂ in the molecule)
Preferred compounds as the compound containing at least one N-containing organic compound containing —N═, N═N, or —NH ₂ in the molecule are triazole derivatives (1H-1,2,3-triazole, 2H-1,2, , 3-triazole, 1H-1,2,4-triazole, 4H-1,2,4-triazole, benzotriazole, 1-aminobenzotriazole, 3-amino-5-mercapto-1,2,4-triazole, 3-amino-1H-1,2,4-triazole, 3,5-diamino-1,2,4-triazole, 3-oxy-1,2,4-triazole, aminourazole, etc.), tetrazole derivatives (tetrazolyl) Tetrazolylhydrazine, 1H-1,2,3,4-tetrazole, 2H-1,2,3,4-tetrazole, 5-amino-1H-te Tolazole, 1-ethyl-1,4-dihydroxy-5H-tetrazol-5-one, 5-mercapto-1-methyltetrazole, tetrazole mercaptan, etc., oxazole derivatives (oxazole, oxazolyl, oxazoline, benzoxazole, 3-amino-5 -Methylisoxazole, 2-mercaptobenzoxazole, 2-aminooxazoline, 2-aminobenzoxazole, etc.), oxadiazole derivatives (1,2,3-oxadiazole, 1,2,4-oxadiazole, 1 , 2,5-oxadiazole, 1,3,4-oxadiazole, 1,2,4-oxadiazolone-5, 1,3,4-oxadiazolone-5, etc.), oxatriazole derivatives (1 , 2,3,4-oxatriazole, 1,2,3,5-oxatriazo ), Purine derivatives (purine, 2-amino-6-hydroxy-8-mercaptopurine, 2-amino-6-methylmercaptopurine, 2-mercaptoadenine, mercaptohypoxanthine, mercaptopurine, uric acid, guanine, adenine, Xanthine, theophylline, theobromine, caffeine, etc.), imidazole derivatives (imidazole, benzimidazole, 2-mercaptobenzimidazole, 4-amino-5-imidazolecarboxylic acid amide, histidine, etc.), indazole derivatives (indazole, 3-indazolone, indazolol) ), Pyridine derivatives (2-mercaptopyridine, aminopyridine, etc.), pyrimidine derivatives (2-mercaptopyrimidine, 2-aminopyrimidine, 4-aminopyrimidine, 2-amino-4,6-dihi Roxypyrimidine, 4-amino-6-hydroxy-2-mercaptopyrimidine, 2-amino-4-hydroxy-6-methylpyrimidine, 4-amino-6-hydroxy-2-methylpyrimidine, 4-amino-6-hydroxypyrim Zolo [3,4-d] pyrimidine, 4-amino-6-mercaptopyrazolo [3,4-d] pyrimidine, 2-hydroxypyrimidine, 4-mercapto-1H-pyrazolo [3,4-d] pyrimidine, 4 -Amino-2,6-dihydroxypyrimidine, 2,4-diamino-6-hydroxypyrimidine, 2,4,6-triaminopyrimidine, etc.), thiourea derivatives (thiourea, ethylenethiourea, 2-thiobarbituric acid, etc.) ), Amino acids (glycine, alanine, tryptophan, proline, oxyproline, etc.), 1,3,4-thioo Oxadiazolone-5, thiocoumazone, 2-thiocoumarin, thiosaccharin, thiohydantoin, thiopyrine, γ-thiopyrine, guanazine, guanazole, guanamine, oxazine, oxadiazine, melamine, 2,4,6-triaminophenol, triaminobenzene, aminoindole Aminoquinoline, aminothiophenol, aminopyrazole and the like.

(Corrosion inhibitor solution)
Water and an organic solvent can be used for the preparation of the solution containing the corrosion inhibitor. The type of the organic solvent is not particularly limited, but alcohols such as methanol, ethanol, n-propyl alcohol and n-butyl alcohol, ethers such as di-n-propyl ether, di-n-butyl ether and diallyl ether, Aliphatic hydrocarbons such as hexane, heptane, octane, and nonane, and aromatic hydrocarbons such as benzene, toluene, and phenol can be used. One or more of these solvents can be used in combination.

(Corrosion inhibitor concentration and treatment time)
The concentration of the corrosion inhibitor solution is preferably from 0.1 to 5000 ppm. Furthermore, 0.5 to 3000 ppm is more preferable, and 1 to 1000 ppm is particularly preferable. If the concentration of the corrosion inhibitor is less than 0.1 ppm, the migration suppressing effect is not sufficient, and sufficient adhesion strength between the copper wiring and the insulator tends not to be obtained. When the concentration of the corrosion inhibitor exceeds 5000 ppm, a migration suppressing effect is obtained, but sufficient adhesion strength between the copper wiring and the insulator tends not to be obtained. There is no particular limitation on the time for treating the copper wiring surface with the solution containing the corrosion inhibitor, and it is preferable to change it appropriately according to the type and concentration of the corrosion inhibitor.

(Semiconductor chip mounting substrate)
In FIG. 5, the cross-sectional schematic diagram of one Example (2 single-sided buildup layers) of the semiconductor chip mounting substrate of this invention was shown. Here, an embodiment in which the buildup layer is formed only on one side will be described. However, the buildup layer may be formed on both sides as shown in FIG.

  In the semiconductor chip mounting substrate shown in FIG. 5, the first wiring 106a including the semiconductor chip connection terminal and the first interlayer connection terminal 101 is formed on the core substrate 100 which is an insulating layer on the side where the semiconductor chip is mounted. Is done. A second wiring 106 b including a second interlayer connection terminal 103 is formed on the other side of the core substrate 100, and the first interlayer connection terminal 101 and the second interlayer connection terminal 103 are connected to the second interlayer connection terminal 103 of the core substrate 100. Electrical connection is made through one interlayer connection IVH (interstitial via hole) 102. A build-up layer 104 is formed on the second wiring 106b side of the core substrate 100, and a third wiring 106c including a third interlayer connection terminal is formed on the build-up layer 104. The terminal 103 and the third interlayer connection terminal are electrically connected via the second interlayer connection IVH 108. An insulator is formed between the wirings 106a, a part of the insulator between the copper wirings is removed to expose a part of the copper wiring, and finally the insulator 110 is formed.

  The semiconductor chip mounting substrate shown in FIG. 5 includes the printed wiring board according to the embodiment. The plurality of copper wirings provided on one surface of the printed wiring board are semiconductor chip connection terminals for connection to the semiconductor chip. The first wiring 106a includes a copper wiring and a semiconductor chip connection terminal. A plurality of copper wirings provided on the other surface of the printed wiring board are external connection terminals 107. In this semiconductor chip mounting substrate, a bridge is hardly generated between the wirings 106a, and the insulation between the wirings 106a is improved.

  When a plurality of buildup layers 104 are formed, the same structure is laminated, and external connection terminals 107 connected to the motherboard are formed on the outermost buildup layer 104. The external connection terminal 107 is electrically connected to the third wiring 106 c by the third interlayer connection IVH 105. The shape of the wiring, the arrangement of each connection terminal, and the like are not particularly limited, and can be appropriately designed for manufacturing a semiconductor chip to be mounted and a target semiconductor package. Further, the semiconductor chip connection terminal and the first interlayer connection terminal 101 can be shared. Furthermore, an insulating coating 109 such as a solder resist can be provided on the outermost layer as required.

(Core substrate)
The material of the core substrate 100 is not particularly limited, but an organic substrate, a ceramic substrate, a silicon substrate, a glass substrate, or the like can be used. In consideration of the thermal expansion coefficient and insulation, it is preferable to use ceramic or glass. Among the non-photosensitive glasses, soda lime glass (component example: SiO ₂ 65 to 75 wt%, Al ₂ O ₃ 0.5 to ₄ wt%, CaO 5 to 15 wt%, MgO 0.5 to 4 wt%, Na ₂ O 10-20 wt%), borosilicate glass (component example: SiO ₂ 65-80 wt%, B ₂ O ₃ 5-25 wt%, Al ₂ O ₃ 1-5 wt%, CaO 5-8 wt%, MgO 0.5 ˜2 wt%, Na ₂ O 6-14 wt%, K ₂ O 1-6 wt%) and the like. As the photosensitive glass include those containing gold ions and silver ions as a photosensitive agent into Li _{2 O-SiO} 2 based crystallized glass.

  As the organic substrate, a substrate or a resin film obtained by laminating a material in which a glass cloth is impregnated with a resin can be used. As the resin to be used, a thermosetting resin, a thermoplastic resin, or a mixed resin thereof can be used, but a thermosetting organic insulating material is preferable. Thermosetting resins include phenolic resin, urea resin, melamine resin, alkyd resin, acrylic resin, unsaturated polyester resin, diallyl phthalate resin, epoxy resin, polybenzimidazole resin, polyamide resin, polyamideimide resin, silicone resin, cyclohexane Resin synthesized from pentadiene, resin containing tris (2-hydroxyethyl) isocyanurate, resin synthesized from aromatic nitrile, trimerized aromatic dicyanamide resin, resin containing triallyl trimetallate, furan resin, ketone resin, A xylene resin, a thermosetting resin containing a condensed polycyclic aromatic, a benzocyclobutene resin, or the like can be used. Examples of the thermoplastic resin include polyimide resin, polyphenylene oxide resin, polyphenylene sulfide resin, aramid resin, and liquid crystal polymer.

A filler may be added to these resins. Examples of the filler include silica, talc, aluminum hydroxide, aluminum borate, aluminum nitride, and alumina.
The thickness of the core substrate 100 is preferably 100 to 800 μm, more preferably 150 to 500 μm, from the viewpoint of IVH formation.

(Build-up layer)
The interlayer insulating layer (build-up layer) 104 is made of an insulating material, and a thermosetting resin, a thermoplastic resin, or a mixed resin thereof can be used as the insulating material. The buildup layer 104 is preferably composed mainly of a thermosetting organic insulating material. Thermosetting resins include phenolic resin, urea resin, melamine resin, alkyd resin, acrylic resin, unsaturated polyester resin, diallyl phthalate resin, epoxy resin, polybenzimidazole resin, polyamide resin, polyamideimide resin, silicone resin, cyclohexane Resin synthesized from pentadiene, resin containing tris (2-hydroxyethyl) isocyanurate, resin synthesized from aromatic nitrile, trimerized aromatic dicyanamide resin, resin containing triallyl trimetallate, furan resin, ketone resin, A xylene resin, a thermosetting resin containing a condensed polycyclic aromatic, a benzocyclobutene resin, or the like can be used. Examples of the thermoplastic resin include polyimide resin, polyphenylene oxide resin, polyphenylene sulfide resin, aramid resin, and liquid crystal polymer.

  A filler may be added to the insulating material. Examples of the filler include silica, talc, aluminum hydroxide, aluminum borate, aluminum nitride, and alumina.

(Coefficient of thermal expansion)
It is preferable that the thermal expansion coefficient of the semiconductor chip and the thermal expansion coefficient of the core substrate 100 are approximated, and the thermal expansion coefficient of the core substrate 100 and the thermal expansion coefficient of the buildup layer 104 are approximated. It is not limited to. Furthermore, when the thermal expansion coefficients of the semiconductor chip, the core substrate 100, and the buildup layer 104 are α1, α2, and α3 (ppm / ° C.), it is more preferable that α1 ≦ α2 ≦ α3.

  Specifically, the thermal expansion coefficient α2 of the core substrate 100 is preferably 7 to 13 ppm / ° C, more preferably 9 to 11 ppm / ° C. The thermal expansion coefficient α3 of the buildup layer 104 is preferably 10 to 40 ppm / ° C., more preferably 10 to 20 ppm / ° C., and particularly preferably 11 to 17 ppm / ° C.

(Young's modulus)
The Young's modulus of the buildup layer 104 is preferably 1 to 5 GPa in terms of stress relaxation against thermal stress. It is preferable to add the filler in the buildup layer 104 by appropriately adjusting the addition amount so that the thermal expansion coefficient of the buildup layer 104 is 10 to 40 ppm / ° C. and the Young's modulus is 1 to 5 GPa.

(Manufacturing method of semiconductor chip mounting substrate)
Hereinafter, a method for manufacturing a semiconductor chip mounting substrate according to the embodiment will be described. In the method for manufacturing a semiconductor chip mounting substrate according to the present embodiment, a plurality of copper wirings provided on one surface of the printed wiring board manufactured by the method for manufacturing a printed wiring board according to the present embodiment are formed on the semiconductor chip. This is a semiconductor chip connection terminal for connection. The plurality of copper wirings provided on the other surface of the printed wiring board are external connection terminals.

  The semiconductor chip mounting substrate can be manufactured by a combination of the following manufacturing methods. The order of the manufacturing process is not particularly limited as long as it does not depart from the object of the present invention.

(Wiring formation method)
As a wiring forming method, a metal foil is formed on the surface of the core substrate 100 or the build-up layer 104, and unnecessary portions of the metal foil are removed by etching (subtract method), or the surface of the core substrate 100 or the build-up layer 104 is formed. A method of forming a wiring by plating only at a necessary position (additive method), a thin metal layer (seed layer) is formed on the surface of the core substrate 100 or the buildup layer 104, and then a wiring required by electrolytic plating is formed. There is a method (semi-additive method) of removing a thin metal layer by etching after the formation.

(Wiring formation by etching)
An etching resist is formed in a portion that becomes a wiring of the metal foil, and a chemical etching solution is sprayed and sprayed on a portion exposed from the etching resist, and unnecessary metal foil is removed by etching to form a wiring. For example, when a copper foil is used as the metal foil, an etching resist material that can be used for an ordinary wiring board can be used as the etching resist. For example, a resist ink is silk-screen printed to form an etching resist, or a negative photosensitive dry film for etching resist is laminated on a copper foil, and a photomask that transmits light is superimposed on the wiring shape. Then, an etching resist is formed by exposing with ultraviolet light and removing the unexposed portion with a developer. As the chemical etching solution, a chemical etching solution used for a normal wiring board, such as a solution of cupric chloride and hydrochloric acid, a ferric chloride solution, a solution of sulfuric acid and hydrogen peroxide, and an ammonium persulfate solution can be used.

(Wiring formation by plating)
Further, the wiring can be formed only by performing plating only on necessary portions on the core substrate 100 or the buildup layer 104, and a wiring forming technique by normal plating can be used. For example, after depositing an electroless plating catalyst on the core substrate 100, a plating resist is formed on a surface portion where plating is not performed, and immersed in an electroless plating solution. Then, electroless plating is performed to form wiring.

(Wiring formation by semi-additive method)
As a method for forming a seed layer of the semi-additive method on the surface of the core substrate 100 or the build-up layer 104, there are a method by vapor deposition or plating and a method of bonding a metal foil. Also, a subtractive metal foil can be formed by the same method.

(Formation of seed layer by vapor deposition or plating)
A seed layer can be formed on the surface of the core substrate 100 or the build-up layer 104 by vapor deposition or plating. For example, when a base metal and a thin film copper layer are formed by sputtering as a seed layer, the sputtering apparatus used to form the thin film copper layer is a bipolar sputtering, a three-pole sputtering, a four-pole sputtering, a magnetron sputtering, a mirror. Tron sputtering or the like can be used. A target used for sputtering is sputtered 5 to 50 nm using, for example, a metal such as Cr, Ni, Co, Pd, Zr, Ni / Cr, or Ni / Cu as a base metal in order to ensure adhesion. Thereafter, a seed layer can be formed by sputtering 200 to 500 nm using copper as a target.

  Alternatively, the surface of the core substrate 100 or the build-up layer 104 can be formed by electroless copper plating of 0.5 to 3 μm.

(Method of bonding metal foil)
When the core substrate 100 or the buildup layer 104 has an adhesive function, the seed layer can also be formed by bonding metal foils together by pressing or laminating. However, since it is very difficult to directly bond a thin metal layer, there are methods such as a method of thinning a thick metal foil and then thinning it by etching or a method of peeling a carrier layer after bonding a metal foil with a carrier. is there. For example, as the former, there is a three-layer copper foil of carrier copper / nickel / thin film copper, and carrier copper is removed with an alkali etching solution and nickel is removed with a nickel etching solution. For example, as the latter, a peelable copper foil using aluminum, copper, insulating resin or the like as a carrier can be used, and a seed layer of 5 μm or less can be formed. Alternatively, a 9 to 18 μm thick copper foil may be attached, and the seed layer may be formed by etching so that the thickness is 5 μm or less.

(Semi-additive wiring formation)
A plating resist is formed in a necessary pattern on the seed layer formed by the above-described method, and wiring is formed by electrolytic copper plating through the seed layer. Thereafter, the plating resist is peeled off, and finally the seed layer is removed by etching or the like to form a wiring.

(Wiring shape)
The shape of the wiring is not particularly limited, but at least a semiconductor chip connection terminal 16 (wire bond terminal or the like) is provided on the side on which the semiconductor chip is mounted, and an external connection terminal 19 (solder) electrically connected to the mother board on the opposite side. A portion on which a ball or the like is mounted), a development wiring 20 that connects them, an interlayer connection terminal, and the like (see FIGS. 9 and 10). The wiring arrangement is not particularly limited, but as shown in FIG. 9 (inner layer wiring, interlayer connection terminals, etc. are omitted), a fan-in type in which an external connection terminal 19 is formed inside the semiconductor chip connection terminal 16 or A fan-out type in which the external connection terminals 19 are formed outside the semiconductor chip connection terminals 16 as shown in FIG. 10 or a combination of these may be used. FIG. 9 is a plan view of the fan-in type semiconductor chip mounting substrate, and FIG. 10 is a plan view of the fan-out type semiconductor chip mounting substrate. The shape of the semiconductor chip connection terminal 16 is not particularly limited as long as wire bond connection or flip chip connection is possible. Moreover, wire-bond connection and flip-chip connection are possible for both fan-out and fan-in types. In the flip chip connection, a die bond film adhesion region 14 and a semiconductor chip mounting region 15 are set in the semiconductor package region 13. In the wire bond connection, the die bond film adhesion region 17 and the semiconductor chip mounting region 18 are set in the semiconductor package region 13. Furthermore, if necessary, a dummy pattern 21 (see FIG. 10) that is not electrically connected to the semiconductor chip may be formed. The shape and arrangement of the dummy pattern 21 are not particularly limited, but it is preferable that the dummy pattern 21 be arranged uniformly in the semiconductor chip mounting region 15 or 18. As a result, voids are less likely to occur when a semiconductor chip is mounted with a die bond adhesive, and reliability can be improved.

(Bahia Hall)
The semiconductor chip mounting substrate may have a plurality of wiring layers. In this case, a via hole for electrically connecting the wirings of each layer can be provided. The via hole can be formed by providing a connection hole in the core substrate 100 or the buildup layer 104 and filling the hole with a conductive paste, plating, or the like (see FIG. 5). Examples of the hole processing method include mechanical processing such as punching and drilling, laser processing, chemical etching processing using a chemical solution, and dry etching using plasma.

  As a method for forming a via hole in the build-up layer 104, there is a method in which a conductive layer is formed on the build-up layer 104 in advance by a conductive paste or plating, and this is stacked on the core substrate 100 by a press or the like.

(Formation of insulation coating)
An insulating coating can be formed on the external connection terminal side of the semiconductor chip mounting substrate. The pattern can be formed by printing if it is a varnish-like material, but it is preferable to use a photosensitive solder resist, a coverlay film, or a film-like resist in order to ensure higher accuracy. As a material, an epoxy-based material, a polyimide-based material, an epoxy acrylate-based material, or a fluorene-based material can be used.

  Since such an insulating coating has shrinkage at the time of curing, if it is formed only on one side, a large warp tends to occur on the substrate. Therefore, an insulating coating can be formed on both surfaces of the semiconductor chip mounting substrate as necessary. Furthermore, since the warpage varies depending on the thickness of the insulating coating, it is more preferable to adjust the thickness of the insulating coating on both sides so that no warpage occurs. In that case, it is preferable to conduct preliminary examination and determine the thicknesses of the insulating coatings on both sides. In order to obtain a thin semiconductor package, the thickness of the insulating coating is preferably 50 μm or less, and more preferably 30 μm or less.

Hereinafter, the method for manufacturing the semiconductor chip mounting substrate according to the embodiment will be described in detail with reference to FIG.
Such a semiconductor chip mounting substrate can be manufactured by the following processes. FIGS. 6A to 6I are cross-sectional schematic views showing an example of an embodiment of a method for manufacturing a semiconductor chip mounting substrate of the present invention. However, the order of the manufacturing process is not particularly limited as long as it does not depart from the object of the present invention.

(Process a)
(Step a) is a step of forming the first wiring 106a on the core substrate 100 as shown in FIG.
For example, an etching resist can be formed in the shape of the first wiring 106a on the core substrate 100 having a copper layer formed on one side, and the wiring 106a can be manufactured using an etching solution such as copper chloride or iron chloride. In order to produce a copper layer on a substrate (core substrate 100), after forming a thin film by sputtering, vapor deposition, plating, etc., a copper layer is obtained by plating to a desired thickness by electrolytic copper plating. Can do.

  Note that the first wiring 106a includes the first interlayer connection terminal 101 and the semiconductor chip connection terminal (portion electrically connected to the semiconductor chip), and a semi-additive method is used as a method for forming the fine wiring. May be.

(Process b)
In step (b), as shown in FIG. 6B, a first interlayer connection IVH 102 (via hole) for connecting the first interlayer connection terminal 101 and a second wiring 106b described later. Is a step of forming.

The via hole can be formed by using laser light when the core substrate 100 is a non-photosensitive base material. Examples of the non-photosensitive substrate include the non-photosensitive glass described above, but are not limited thereto. In this case, the laser beam to be used is not limited, and a CO ₂ laser, a YAG laser, an excimer laser, or the like can be used. Further, when the core substrate 100 is a photosensitive base material, a region other than the via hole is masked, and the via hole portion is irradiated with ultraviolet light. Examples of the photosensitive base material include the above-described photosensitive glass, but are not limited thereto. In this case, via holes are formed by heat treatment and etching after irradiation with ultraviolet light. Further, when the core substrate 100 is a base material that can be chemically etched by a chemical solution such as an organic solvent, a via hole can be formed by chemical etching. The formed via hole can be filled with a conductive paste or plating to form an electrically conductive layer for interlayer connection in order to electrically connect the interlayer.

(Process c)
Step (c) is a step of forming the second wiring 106b on the surface of the core substrate 100 opposite to the first wiring 106a, as shown in FIG. 6 (c). A copper layer is formed on the surface opposite to the first wiring 106a of the core substrate 100 in the same manner as in the step (a), an etching resist is formed on the copper layer in a necessary wiring shape, and etching such as copper chloride or iron chloride is performed. The second wiring 106b is formed using a liquid. As a method for forming a copper layer, a copper layer is obtained by forming a copper thin film by sputtering, vapor deposition, electroless plating, etc. in the same manner as in (Step a) and then copper plating to a desired thickness using electrolytic copper plating. It is done.

  Note that the second wiring 106b includes the second interlayer connection terminal 103, and a semi-additive method may be used as a method for forming the fine wiring.

(Process d)
Step (d) is a step of forming a buildup layer (interlayer insulating layer) 104 on the surface on which the second wiring 106b is formed as shown in FIG. 6 (d). First, the surface of the second wiring 106b is subjected to the degreasing treatment or the sulfuric acid cleaning. It is immersed in an aqueous solution containing an acid, an alkali or an oxidizing agent, and the treatment is carried out so that the Ra (average roughness) of the copper wiring surface becomes 0.01 to 0.4 μm. When immersed in an aqueous solution containing an oxidizing agent, the surface of the copper wiring surface is set to 0.01 to 0.4 μm by further immersion in an aqueous solution containing a reducing agent and reducing the copper oxide film. Process.

  Next, the buildup layer 104 is formed on the surface of the core substrate 100 and the surface of the second wiring 106b. As the insulating material for the build-up layer 104, a thermosetting resin, a thermoplastic resin, or a mixed resin thereof can be used as described above, but it is preferable to use a thermosetting material as a main component. In the case of a varnish-like material, the build-up layer 104 can be obtained by printing or spin coating, or in the case of a film-like insulating material, using a technique such as lamination or pressing. When the insulating material includes a thermosetting material, it is desirable to further heat and cure.

(Process e)
(Step e) is a step of forming a second interlayer connection IVH (via hole) 108 in the buildup layer 104 as shown in FIG. 6E. As a means for forming the via hole, A general laser drilling device can be used. A CO ₂ laser, a YAG laser, an excimer laser, or the like can be used as the type of laser used in the laser drilling machine, but a CO ₂ laser is preferable in terms of productivity and hole quality. Further, when the IVH diameter is less than 30 μm, a YAG laser capable of focusing the laser beam is suitable. In the case where the buildup layer 104 is a material that can be chemically etched by a chemical solution such as an organic solvent, a via hole can be formed by chemical etching.

(Process f)
(Step f) is a step of forming the third wiring 106c on the buildup layer 104 in which the second via hole is formed, as shown in FIG. 6 (f). Further, as a process for forming a fine wiring of L / S = 35 μm / 35 μm or less, the above-described semi-additive method is preferable. A seed layer is formed on the buildup layer 104 by a method such as vapor deposition or plating, or a method of bonding a metal foil. A plating resist is formed in a necessary pattern on the seed layer formed by the above-described method, and wiring is formed by electrolytic copper plating through the seed layer. Thereafter, the plating resist is peeled off, and finally the seed layer is removed by etching or the like, so that the fine wiring 106c can be formed.

(Process g)
(Step d) to (Step f) may be repeated to produce two or more buildup layers 104 as shown in FIG. 6 (g). In this case, the interlayer connection terminal formed in the outermost buildup layer 104 becomes the external connection terminal 107.

(Process h)
(Step h) is a step of forming the insulator 110 between the wirings 106a as shown in FIG. 6H, and removing a part of the resin (insulator) to expose a part of the copper wiring. .

  The insulator 110 formed between the wirings 106a can be formed by curing a varnish of a thermosetting resin, a thermoplastic resin, or a mixed resin thereof. The varnish of thermosetting resin, thermoplastic resin, or mixed resin is applied to the substrate using spray coater, slit die coater, dip coater, spin coater, screen printing, etc., spray spraying. Can be applied to the substrate, and is not limited to these methods. When it is limited to a thermosetting resin, it is a normal method to cure after coating, but it is more preferable to cure after placing in a vacuum state.

  The insulator can be formed by repeating the coating → drying process several times. It is also possible to apply a thermosetting resin, a thermoplastic resin, or a varnish of a mixed resin thereof, and then semi-cure it, to bond a carrier film or copper foil by a roll laminating method, and to cure by pressing. The bonding of the carrier film or the copper foil is preferably a vacuum roll laminating method, and more preferably cured by a vacuum press.

  In addition, an uncured or semi-cured insulator coated on one side of a carrier film or copper foil can be bonded to a substrate by a laminating method or a roll laminating method, and the insulator can be adhered to the substrate. As the carrier film, a polyimide film is preferable from the viewpoint of heat resistance, and in particular, a polyimide film in which copper is formed on the surface by vapor deposition or sputtering is preferable. Moreover, about a copper foil, it is preferable to make a shiny surface side and an insulator contact, and the thing without a rust prevention metal is more preferable.

  As a method of removing a part of the resin (insulator) and exposing a part of the copper wiring, it can be formed by at least one of a dry etching process, a wet etching process and a mechanical polishing process. These processes are more preferably performed in combination as appropriate.

(Process i)
(Step i) is a step of forming an insulating coating 109 for protecting wirings other than the semiconductor chip connection terminals and the external connection terminals 107, as shown in FIG. 6 (i). As the insulating coating material, a solder resist is generally used, and a thermosetting type or an ultraviolet curing type can be used, but an ultraviolet curing type capable of finishing the resist shape with high accuracy is preferable.

(Process j)
In (step j), it is preferable to wash the substrate on which the insulating coating 109 is formed.

(Process k)
In (Step k), for example, a nickel plating film and a gold plating film are sequentially formed on the wiring by using an electroless plating method. Further, a nickel plating film, a palladium plating film, and a gold plating film may be formed in order on the wiring.

(Shape of semiconductor chip mounting substrate)
The shape of the semiconductor chip mounting substrate 22 is not particularly limited, but is preferably a frame shape as shown in FIG. By making the shape of the semiconductor chip mounting substrate 22 in this way, the semiconductor package can be efficiently assembled. Hereinafter, a preferable frame shape will be described in detail.

  As shown in FIG. 11, a block 23 is formed in which a plurality of semiconductor package regions 13 (parts to be a single semiconductor package) are arranged in rows and columns at regular intervals. Further, such a block 23 is formed in a plurality of rows and columns. In FIG. 11, only two blocks 23 are shown, but the blocks 23 may also be arranged in a lattice shape as necessary. Here, the width of the space portion between the semiconductor package regions 13 is preferably 50 to 500 μm, and more preferably 100 to 300 μm. Furthermore, it is most preferable that the blade width of the dicer used when the semiconductor package is cut later is made the same.

  By arranging the semiconductor package region 13 in this way, the semiconductor chip mounting substrate 22 can be effectively used. Moreover, it is preferable to form the positioning mark 11 etc. in the edge part of the semiconductor chip mounting substrate 22, and it is more preferable that it is a pin hole by a through hole. The shape and arrangement of the pin holes may be selected so as to match the forming method and the semiconductor package assembly apparatus.

  Furthermore, it is preferable to form a reinforcing pattern 24 in the space between the semiconductor package regions 13 or outside the block 23. The reinforcing pattern 24 may be separately manufactured and bonded to the semiconductor chip mounting substrate 22, but is preferably a metal pattern formed at the same time as the wiring formed in the semiconductor package region 13. More preferably, the same plating as that for the wiring, such as nickel or gold, is applied or an insulating coating is applied. When the reinforcing pattern 24 is made of such a metal, it can be used as a plating lead for electrolytic plating. Moreover, it is preferable to form the cutting alignment mark 25 at the time of cutting with a dicer outside the block 23. In this way, the frame-shaped semiconductor chip mounting substrate 22 can be manufactured.

(Semiconductor package)
FIG. 7 is a schematic cross-sectional view showing an example of a semiconductor package according to the present invention (flip chip type semiconductor package). The semiconductor package shown in FIG. 7 is obtained by further mounting a semiconductor chip 111 on the semiconductor chip mounting substrate, and by flip-chip connecting the semiconductor chip 111 and the semiconductor chip connection terminals using connection bumps 112. It can be obtained by electrical connection.

  Further, in these semiconductor packages, it is preferable to seal between the semiconductor chip 111 and the semiconductor chip mounting substrate with an underfill material 113 as shown in the figure. The thermal expansion coefficient of the underfill material 113 is preferably approximated to the thermal expansion coefficients of the semiconductor chip 111 and the core substrate 100, but is not limited thereto. More preferably, (thermal expansion coefficient of semiconductor chip) (thermal expansion coefficient of underfill material) ≦ (thermal expansion coefficient of core substrate). Furthermore, the semiconductor chip 111 can be mounted using an anisotropic conductive film (ACF) or an adhesive film (NCF) that does not contain conductive particles. In this case, since it is not necessary to seal with the underfill material 113, it is more preferable. Furthermore, it is particularly preferable to use ultrasonic waves together with the semiconductor chip 111 because electrical connection can be performed at a low temperature and in a short time.

  FIG. 8 shows a cross-sectional view of an embodiment of a wire bond type semiconductor package. For mounting the semiconductor chip 111, a general die bond paste can be used, but a die bond film 117 is more preferable. The electrical connection between the semiconductor chip 111 and the semiconductor chip connection terminal is generally performed by wire bonding using a gold wire 115. The semiconductor chip 111 can be sealed by transfer molding using a semiconductor sealing resin 116. In that case, at least the face surface of the semiconductor chip 111 is sealed with a semiconductor sealing resin 116, but only a necessary portion of the sealing region may be sealed, but the entire semiconductor package region as shown in FIG. It is more preferable to seal. This is particularly true when a substrate (semiconductor chip mounting substrate) and a sealing resin (semiconductor sealing resin 116) are simultaneously cut with a dicer or the like in a semiconductor chip mounting substrate in which a plurality of semiconductor package regions are arranged in rows and columns. It is an effective method.

In order to make an electrical connection with the motherboard, for example, solder balls 114 can be mounted on the external connection terminals 107 (see FIG. 5). For the solder balls 114, eutectic solder or Pb-free solder is used. As a method for fixing the solder ball 114 to the external connection terminal 107, an N ₂ reflow apparatus is generally used, but is not limited to this.

In a semiconductor chip mounting substrate in which a plurality of semiconductor package regions are arranged in rows and columns, the semiconductor package region is finally cut into individual semiconductor packages using a dicer or the like.
The semiconductor package shown in FIGS. 7 and 8 includes the semiconductor chip mounting substrate according to the embodiment and the semiconductor chip 111 mounted on the semiconductor chip mounting substrate. In such a semiconductor package, a bridge is hardly generated between the copper wirings, and the insulation between the copper wirings is improved.

Hereinafter, the present invention will be described in detail based on examples, but the present invention is not limited thereto.
Example 1
(Process a)
A 0.4 mm thick soda glass substrate (thermal expansion coefficient 11 ppm / ° C.) was prepared as the core substrate 100, a 200 nm copper thin film was formed on one surface by sputtering, and then plated to a thickness of 20 μm by electrolytic copper plating. In addition, sputtering was performed on condition 1 shown below using the apparatus model number MLH-6315 by Nippon Vacuum Technology Co., Ltd. After that, an etching resist is formed in a portion to be the first wiring 106a, and etching is performed using a ferric chloride etching solution to include a copper wiring of L / S = 30 μm / 40 μm level. 1 interlayer connection terminal 101 and semiconductor chip connection terminal) were formed (see FIG. 6A).
Condition 1
Current: 3.5A
Voltage: 500V
Argon flow rate: 35 SCCM
Pressure: 5 × 10 ⁻³ Torr (4.9 × 10 ⁻² Pa)
Deposition rate: 5 nm / second

(Process b)
An IVH hole having a hole diameter of 50 μm was formed with a laser until it reached the first interlayer connection terminal 101 from the surface opposite to the first wiring 106a of the glass substrate on which the first wiring 106a was formed. YAG laser LAVIA-UV2000 (manufactured by Sumitomo Heavy Industries, Ltd., trade name) was used as the laser, and IVH holes were formed under the conditions of a frequency of 4 kHz, a shot number of 50, and a mask diameter of 0.4 mm.

  The obtained IVH hole was filled with conductive paste MP-200V (trade name, manufactured by Hitachi Chemical Co., Ltd.), cured at 160 ° C. for 30 minutes, and electrically connected to the first interlayer connection terminal 101 of the glass substrate. A first interlayer connection IVH (via hole) 102 connected to is formed (see FIG. 6B).

(Process c)
In order to electrically connect to the first interlayer connection IVH (first via hole) 102 formed in (Step b), a surface of the glass substrate opposite to the first wiring 106a is sputtered to 200 nm. After forming the copper thin film, plating was performed to a thickness of 10 μm by electrolytic copper plating. Sputtering was performed in the same manner as in (Step a). Further, an etching resist is formed in the shape of the second wiring 106b as in (Step a), and etching is performed using a ferric chloride etchant to include the second wiring 106b (including the second interlayer connection terminal 103). ) Was formed (see FIG. 6C).

(Process d)
After immersing the surface on the second wiring 106b side formed in (step c) in acidic degreasing solution Z-200 (trade name, manufactured by World Metal Co., Ltd.) adjusted to 200 ml / L for 2 minutes at a liquid temperature of 50 ° C. Then, it was washed with hot water by immersing it in water at a liquid temperature of 50 ° C. for 2 minutes, and further washed with water for 1 minute. Subsequently, it was immersed in a 3.6 N sulfuric acid aqueous solution for 1 minute and washed with water for 1 minute. After passing through these steps, an aqueous solution adjusted to pH 5 with acetic acid was adjusted so that the concentration of γ-aminopropyltriethoxysilane A-1100 (trade name, manufactured by Nihon Unicar Co., Ltd.) was 0.5% by weight. It was immersed in the solution at 25 ° C. for 1 minute. Furthermore, it dried for 3 minutes at 120 degreeC, without washing with water.

  Next, an interlayer insulating layer (build-up layer) 104 was formed as follows. That is, an insulating varnish of a cyanate ester-based resin composition was applied onto a glass substrate by a spin coating method at a condition of 1500 rpm to form an insulating layer having a thickness of 20 μm, and then from room temperature (25 ° C.) to 6 ° C./min. It heated to 230 degreeC with the temperature increase rate, was thermoset by hold | maintaining at 230 degreeC for 80 minutes, and formed the buildup layer 104 of 15 micrometers (refer FIG.6 (d)).

(Process e)
An IVH hole having a hole diameter of 50 μm was formed with a laser until reaching the second interlayer connection terminal 103 from the surface of the buildup layer 104. YAG laser LAVIA-UV2000 (trade name, manufactured by Sumitomo Heavy Industries, Ltd.) was used as the laser, and IVH holes were formed under the conditions of a frequency of 4 kHz, a shot number of 20 and a mask diameter of 0.4 mm (FIG. 6 ( e)).

(Process f)
In order to form the third wiring 106c and the second via hole, a base metal Ni layer 20 nm serving as a seed layer was formed by sputtering, and a thin film copper layer 200 nm was further formed. Sputtering was performed under the condition 2 shown below using MLH-6315 manufactured by Nippon Vacuum Technology Co., Ltd.

Condition 2
(nickel)
Current: 5.0A
Current: 350V
Voltage argon flow rate: 35 SCCM
Pressure: 5 × 10 ⁻³ Torr (4.9 × 10 ⁻² Pa)
Deposition rate: 0.3 nm / second (copper)
Current: 3.5A
Voltage: 500V
Argon flow rate: 35 SCCM
Pressure: 5 × 10 ⁻³ Torr (4.9 × 10 ⁻² Pa)
Deposition rate: 5 nm / second

Next, a plating resist layer having a thickness of 20 μm was formed on the seed layer by spin coating using a plating resist PMER P-LA900PM (trade name, manufactured by Tokyo Ohka Kogyo Co., Ltd.). Exposure was performed at 1000 mJ / cm ² , and immersion rocking was performed at 23 ° C. for 6 minutes using PMER developer P-7G to form a resist pattern of L / S = 10 μm / 10 μm. Then, pattern copper plating was performed about 5 micrometers using the copper sulfate plating solution. The plating resist was removed by dipping for 1 minute at room temperature (25 ° C.) using methyl ethyl ketone. For quick etching of the seed layer, a 5-fold diluted solution of CPE-700 (manufactured by Mitsubishi Gas Chemical Co., Ltd., trade name) is used for etching removal by immersing and shaking at 30 ° C. for 30 seconds, and wiring. 106c was formed (see FIG. 6F).

(Process g)
Thereafter, the steps (d) to (step f) were repeated again to form a further outermost layer wiring including the buildup layer 104 and the external connection terminal 107 (see FIG. 6G).

(Process h)
Next, the insulator 110 was formed as follows (see FIG. 6H). That is, an insulating varnish of a cyanate ester resin composition is applied to the surface side on which the first wiring 106a is formed by a spin coat method at a condition of 2000 rpm, and the temperature is increased from room temperature (25 ° C.) to 6 ° C./min. Heating to 230 ° C. at a speed and thermosetting by maintaining at 230 ° C. for 80 minutes, an insulating material having a cross-sectional shape shown in FIG. Next, under the conditions shown below, a part of the insulator between the copper wirings was removed by anisotropic etching, and a part of the copper wiring was exposed as shown in FIG.
Device name: Reactive sputter etching device (ULVAC CSE-1110)
Power: 125W
Gas and flow rate: Ar 17.5 SCCM, O ₂ 50 SCCM
Processing time: 10 min
(Process i)
Next, an insulating coating (solder resist) 109 was formed (see FIG. 6I).

(Process j)
The substrate was immersed in a 30 g / L potassium hydroxide solution at 50 ° C. for 3 minutes, washed with hot water at 50 ° C. for 1 minute, and then washed with water for 5 minutes. Next, it was immersed in a degreasing solution Z-200 (trade name, manufactured by World Metal Co., Ltd.) at 50 ° C. for 3 minutes and washed with water for 2 minutes.

(Process k)
Next, it was immersed in a 100 g / L ammonium persulfate solution for 1 minute, washed with water for 2 minutes, immersed in 100% sulfuric acid for 1 minute, and washed with water for 2 minutes. Next, immersion treatment was performed at 25 ° C. for 5 minutes in SA-100 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a plating activation treatment solution, and washed with water for 2 minutes. Next, immersion treatment was performed at 85 ° C. for 15 minutes in NIPS-100 (trade name, manufactured by Hitachi Chemical Co., Ltd.) which is an electroless nickel plating solution. Next, it was immersed in APP (Ishihara Pharmaceutical Co., Ltd., trade name) which is an electroless palladium plating solution at 50 ° C. for 20 minutes. Next, immersion treatment was performed at 85 ° C. for 10 minutes in HGS-100 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a displacement gold plating. Next, immersion treatment was performed at 65 ° C. for 40 minutes in HGS-2000 (trade name, manufactured by Hitachi Chemical Co., Ltd.) which is an electroless gold plating solution.

  By performing (step j) to (step k), electroless nickel is applied to the outermost layer wiring including the first wiring 106a (including the first interlayer connection terminal 101 and the semiconductor chip connection terminal) and the external connection terminal 107. A plating film (film thickness: 5 μm), a palladium plating film (film thickness: 0.2 μm), and a gold plating film (film thickness: 0.4 μm) are sequentially formed, and FIG. 5 (cross-sectional view for one package), FIG. A fan-in type BGA semiconductor chip mounting substrate as shown in 9 (plan view for one package) and FIG. 11 (overall view of the semiconductor chip mounting substrate) was produced.

(Process l)
Using a die bond film DF-100 (manufactured by Hitachi Chemical Co., Ltd., trade name) for the semiconductor chip mounting region 17 of the semiconductor chip mounting substrate manufactured by the above (steps a) to (step k), the semiconductor chip 111 ( The required number was mounted (see FIG. 8). Next, using a wire bonder UTC230 (trade name, manufactured by Shinkawa Co., Ltd.), the terminals on the semiconductor chip 111 and the semiconductor chip connection terminals of the semiconductor chip mounting substrate were electrically connected by a gold wire 115 having a diameter of 25 μm. Further, the CEL9200 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a semiconductor sealing resin 116, is used for the semiconductor chip, and the one block 23 shown in FIG. 11 is formed at a pressure of 10 MPa, a temperature of 180 ° C. and a time of 90 seconds. Transfer molded together. Next, heat treatment is performed in an oven at a temperature of 180 ° C. for 5 hours to completely cure the sealing resin and the die bond film, and lead-tin eutectic solder balls 114 having a diameter of 0.45 mm are applied to the external connection terminals 107 with N ₂ reflow. Fused with equipment. Finally, the sealing resin and the semiconductor chip mounting substrate were simultaneously cut with a dicer equipped with a blade having a width of 200 μm to produce the semiconductor package shown in FIG.

(Example 2)
After performing (Step a) to (Step g) shown in Example 1, in the same manner as in Example 1 (Step h), the insulating varnish of the cyanate ester-based resin composition was spin-coated, under the condition of 2000 rpm. Then, after coating on the surface side on which the first wiring 106a was formed, semi-curing was performed at 160 ° C. for 10 minutes. The copper side surface of a copper sputtered polyimide film etcher flex (made by Mitsui Chemicals, Inc., trade name) having a copper sputtered film thickness of 0.25 μm and a polyimide film thickness of 12.5 μm is brought into contact with the semi-cured insulator and superimposed, The cross-sectional shape shown in FIG. 2 (a) is heated at a pressure of 1.0 MPa from room temperature (25 ° C.) to 230 ° C. at a rate of temperature increase of 6 ° C./min and held at 230 ° C. for 80 minutes. The insulator was formed. Next, under the conditions shown below, a part of the insulator between the copper wirings was removed by anisotropic etching, and a part of the copper wiring was exposed as shown in FIG.
Device name: Reactive sputter etching device (ULVAC CSE-1110)
Power: 125W
Gas and flow rate: Ar 17.5 SCCM, O ₂ 50 SCCM
Processing time: 2 min
Thereafter, the same steps as (Step i) to (Step 1) of Example 1 were performed, and a fan-in type BGA semiconductor chip mounting substrate and a semiconductor package were manufactured.

(Example 3)
After performing (Step a) to (Step g) shown in Example 1, the following steps were performed. A base material obtained by semi-curing a cyanate ester resin composition on a copper side surface of a copper sputtered polyimide film etcher flex (made by Mitsui Chemicals, Inc., trade name) having a copper sputtered film thickness of 0.25 μm and a polyimide film thickness of 12.5 μm The first wiring 106a is overlapped so as to be in contact with the surface side, and heated at a pressure of 3.0 MPa from room temperature (25 ° C.) to 230 ° C. at a temperature rising rate of 6 ° C./min. It was cured by holding for 80 minutes, the copper sputtered polyimide film was peeled off, and an insulator having a cross-sectional shape shown in FIG. 3A having a thickness of about 25 μm was formed.

Next, polishing was performed with a 1000 buff (trade name, manufactured by Kakuda Brush Co., Ltd.) whose abrasive grains are aluminum oxide under the conditions of a buff rotation speed of 1200 rpm, a buff motor current value conversion pressure of 10 A, and a line speed of 8 m / min. (First mechanical polishing). Next, polishing (second mechanical polishing) was performed under the conditions of a buff rotation speed of 1200 rpm, a buff motor current value conversion pressure of 2 A, and a line speed of 8 m / min, and part of the insulation between the copper wirings was removed. A part of the copper wiring was exposed as shown in 3 (b). Furthermore, it was immersed in a mixed aqueous solution of CuCl ₂ , HCl and H ₂ O ₂ (water: 90 Vol%, CuCl ₂ : 3 Vol%, HCl: 5 Vol%, H ₂ O ₂ : ₂ Vol%) at 25 ° C. for 30 seconds and chemically polished. Went. Thereafter, the same steps as (Step i) to (Step 1) of Example 1 were performed, and a fan-in type BGA semiconductor chip mounting substrate and a semiconductor package were manufactured.

Example 4
After performing (Step a) to (Step g) shown in Example 1, the following steps were performed. Substrates obtained by semi-curing a cyanate ester resin composition on the copper side of a copper sputtered polyimide film etcher flex (made by Mitsui Chemicals, Inc., trade name) having a copper sputtered film thickness of 0.25 μm and a polyimide film thickness of 12.5 μm Are heated to 230 ° C. at a temperature rising rate of 6 ° C./min from room temperature (25 ° C.) at a pressure of 3.0 MPa at a pressure of 3.0 MPa. And then cured for 80 minutes, the copper sputtered polyimide film was peeled off, and an insulator having a cross-sectional shape shown in FIG. 4A having a thickness of about 25 μm was formed.

  Next, in order to finally have the cross-sectional shape shown in FIG. 4B, the buff rotation speed is 1200 rpm with a 1000 buff (trade name, manufactured by Kakuda Brush Co., Ltd.) whose abrasive grains are aluminum oxide. The insulator was polished under the conditions of a buff motor current value converted pressure of 10 A and a line speed of 8 m / min. Next, treatment with a solution containing an oxidizing agent having high oxidizing power by permanganate was performed. For the treatment, a desmear treatment system (trade name: Circoposit 200MLB, manufactured by Shipley Far East Co., Ltd.) was used. Specifically, as a swelling treatment, immersion treatment was performed at 70 ° C. for 5 minutes using a mixed aqueous solution of Circposit MLB conditioner 211 and Circposit Z (water: 70 Vol%, conditioner 211: 20 Vol%, Circposit Z: 10 Vol%). .

  Next, as a removal treatment, immersion treatment was performed at 70 ° C. for 10 minutes with a mixed aqueous solution of circuposit MLB promoter 213A and circuposit MLB promoter 213B (water: 75 Vol%, promoter 213A: 10 Vol%, promoter 213B: 15 Vol%). Next, as a neutralization treatment, immersion treatment was performed at 40 ° C. for 5 minutes with a circular deposit MLB neutralizer 216-4 (water: 80 Vol%, neutralizer 216-4: 20 Vol%) to remove part of the insulation between the wires. Then, a part of the copper wiring was exposed as shown in FIG. Thereafter, the same steps as (Step i) to (Step 1) of Example 1 were performed, and a fan-in type BGA semiconductor chip mounting substrate and a semiconductor package were manufactured.

(Example 5)
After performing (Step a) to (Step g) shown in Example 1, the following steps were performed. Substrates obtained by semi-curing a cyanate ester resin composition on the copper side of a copper sputtered polyimide film etcher flex (made by Mitsui Chemicals, Inc., trade name) having a copper sputtered film thickness of 0.25 μm and a polyimide film thickness of 12.5 μm Are heated to 230 ° C. at a temperature rising rate of 6 ° C./min from room temperature (25 ° C.) at a pressure of 3.0 MPa at a pressure of 3.0 MPa. And then cured for 80 minutes, the copper sputtered polyimide film was peeled off, and an insulator having a cross-sectional shape shown in FIG. 4A having a thickness of about 25 μm was formed.

Next, in order to finally have the cross-sectional shape shown in FIG. 4B, the buff rotation speed is 1200 rpm with a 1000 buff (trade name, manufactured by Kakuda Brush Co., Ltd.) whose abrasive grains are aluminum oxide. The insulator was polished under the conditions of a buff motor current value converted pressure of 10 A and a line speed of 8 m / min. Next, under the conditions shown below, a part of the insulator between the wirings was removed by an anisotropic etching method, and a part of the copper wiring was exposed as shown in FIG.
Device name: Reactive sputter etching device (ULVAC CSE-1110)
Power: 125W
Gas and flow rate: Ar 17.5 SCCM, O ₂ 50 SCCM
Processing time: 15 min
Thereafter, the same steps as (Step i) to (Step 1) of Example 1 were performed, and a fan-in type BGA semiconductor chip mounting substrate and a semiconductor package were manufactured.

(Comparative Example 1)
The same steps as those described in Example 1 (step h) were performed.

(Comparative Example 2)
(Step a) to (Step g) shown in Example 1 were performed, and then (Step i) to (Step j) were performed. Next, it was immersed in a treatment solution having the following composition at 30 ° C. for 3 minutes, washed with hot water at 50 ° C. for 1 minute, and then washed with water for 5 minutes. Then, the process similar to (process k)-(process 1) shown in Example 1 was performed.
Potassium thiosulfate (trade name, manufactured by Kanto Chemical Co., Ltd.): 50 g / L
pH: 6
pH adjuster: Sodium citrate (trade name, manufactured by Kanto Chemical Co., Ltd.)

(Comparative Example 3)
(Step a) to (Step g) shown in Example 1 were performed, and then (Step i) to (Step j) were performed. Next, it was immersed in a treatment solution having the following composition at 30 ° C. for 3 minutes, washed with hot water at 50 ° C. for 1 minute, and then washed with water for 5 minutes. Then, the process similar to (process k)-(process 1) shown in Example 1 was performed.
Sodium thiosulfate (trade name, manufactured by Kanto Chemical Co., Inc.): 30 g / L
pH: 9
pH adjuster: Potassium pyrophosphate (trade name, manufactured by Kanto Chemical Co., Inc.)

(Comparative Example 4)
(Step a) to (Step g) shown in Example 1 were performed, and then (Step i) to (Step j) were performed. Next, it was immersed in a treatment solution having the following composition at 30 ° C. for 3 minutes, washed with hot water at 50 ° C. for 1 minute, and then washed with water for 5 minutes. Then, the process similar to (process k)-(process 1) shown in Example 1 was performed.
Ammonium thiosulfate (trade name, manufactured by Kanto Chemical Co., Inc.): 30 g / L
pH: 9
pH adjuster: Potassium pyrophosphate (trade name, manufactured by Kanto Chemical Co., Inc.)

(Comparative Example 5)
(Step a) to (Step g) shown in Example 1 were performed. The O ₂ plasma etching process was performed on the surface side of the first wiring 106a (including the first interlayer connection terminal 101 and the semiconductor chip connection terminal) and washed in running water for 5 minutes. After performing this treatment, (Step i) to (Step 1) shown in Example 1 were performed.
Apparatus: O ₂ plasma asher (DEM-451M manufactured by Nidec Anerva)
Power: 300W
Gas and flow rate: O ₂ 50SCCM
Gas pressure: 10Pa
Self bias: -700V
Processing time: 15 min
Table 1 shows the precipitation and insulation reliability test results after electroless plating.

(Electroless plating deposition)
An electroless nickel plating film (film thickness: 5 μm), palladium plating film (film) on the outermost layer wiring including the first wiring 106a (including the first interlayer connection terminal 101 and the semiconductor chip connection terminal) and the external connection terminal 107 Thickness: 0.2 μm) and gold plating film (film thickness: 0.4 μm) were sequentially formed, and the deposition properties of electroless plating were evaluated (see FIG. 5). A part of the semiconductor chip connection terminal 16 of the first wiring 106a is observed from the upper surface. Table 1 shows that no bridge is generated (see FIG. 13), electroless plating protrusion 27 from the semiconductor chip connection terminal 16 and Those having the occurrence of bridges such as electroless plating abnormal precipitation 28 on the insulating resin 26 were evaluated as x (see FIG. 14).

(Insulation reliability test)
Using the semiconductor chip mounting substrate subjected to the processing described in Examples 1 to 5 and Comparative Examples 1 to 5, an insulation reliability test was performed for 1000 hours under the conditions of 85 ° C., 85%, and DC 20V. Moreover, the insulation resistance was measured by applying DC 20V using R8340A ULTRA HIGH RESISTANCE METER manufactured by Advantest. In Table 1, evaluation was made with ○ having an insulation resistance of 1.0 × 10 ⁻⁷ Ω or more and × with less than 1.0 × 10 ⁻⁷ Ω.

  As is clear from Table 1, in the semiconductor chip mounting substrates according to Examples 1 to 5, there was no occurrence of electroless plating bridges and the insulation reliability was extremely good. On the other hand, in the comparative examples shown in Comparative Examples 1 to 5, a bridge was generated and the insulation reliability was insufficient.

It is sectional drawing of the copper wiring which coat | covered the insulator and electroless-plating film | membrane with which one Embodiment of this invention is applied. It is sectional drawing of the copper wiring which coat | covered the insulator and electroless-plating film | membrane with which one Embodiment of this invention is applied. It is sectional drawing of the copper wiring which coat | covered the insulator and electroless-plating film | membrane with which one Embodiment of this invention is applied. It is sectional drawing of the copper wiring which coat | covered the insulator and electroless-plating film | membrane with which one Embodiment of this invention is applied. It is sectional drawing of the semiconductor chip mounting substrate to which one Embodiment of this invention is applied. It is process drawing which shows one Embodiment of the manufacturing method of the semiconductor chip mounting substrate of this invention. 1 is a cross-sectional view of a flip chip type semiconductor package to which an embodiment of the present invention is applied. 1 is a cross-sectional view of a wire bond type semiconductor package to which an embodiment of the present invention is applied. 1 is a plan view of a fan-in type semiconductor chip mounting substrate to which an embodiment of the present invention is applied. 1 is a plan view of a fan-out type semiconductor chip mounting substrate to which an embodiment of the present invention is applied. It is a top view showing the frame shape of the semiconductor chip mounting board | substrate with which one Embodiment of this invention is applied. It is sectional drawing of the semiconductor chip mounting substrate to which one Embodiment of this invention is applied. It is a top view of the semiconductor chip connection terminal which is a part of 1st wiring 106a without generation | occurrence | production of a bridge | bridging after electroless plating. It is a top view of the semiconductor chip connection terminal which is a part of 1st wiring with generation | occurrence | production of a bridge | bridging after electroless plating.

Explanation of symbols

1 Copper wiring 2 Core substrate 3 Insulator 4 Nickel plating film 5 Palladium plating film 6 Gold plating film 11 Positioning mark (positioning guide hole)
13 Semiconductor package area 14 Die bond film adhesion area (flip chip type)
15 Semiconductor chip mounting area (flip chip type)
16 Semiconductor chip connection terminal 17 Die bond film adhesion area (wire bond type)
18 Semiconductor chip mounting area (wire bond type)
19 External connection terminal 20 Deployed wiring 21 Dummy pattern 22 Semiconductor chip mounting substrate 23 Block 24 Reinforcement pattern 25 Cutting alignment mark 26 Insulating resin 27 Electroless plating protrusion 28 Electroless plating abnormal precipitation 100 Core substrate 101 First interlayer connection terminal 102 IVH (via hole) for first interlayer connection
103 Second interlayer connection terminal 104 Build-up layer (interlayer insulating layer)
105 Third layer connection IVH (via hole)
106a First wiring 106b Second wiring 106c Third wiring 107 External connection terminal 108 Second interlayer connection IVH (via hole)
109 Insulation coating (solder resist)
110 Insulator 111 Semiconductor chip 112 Connection bump 113 Underfill material 114 Solder ball 115 Gold wire 116 Sealing resin 117 for semiconductor Die bond film

Claims (12)

Forming an insulator between a plurality of copper wirings;
After forming the insulator, forming a nickel plating film and a gold plating film in order on the plurality of copper wirings, or forming a nickel plating film, a palladium plating film and a gold plating film in order,
A method for manufacturing a printed wiring board, comprising: The step of forming the insulator includes
Forming an insulator covering the plurality of copper wirings;
Removing a part of the insulator so that a part of the plurality of copper wirings is exposed;
The manufacturing method of the printed wiring board of Claim 1 containing this.   3. The method of manufacturing a printed wiring board according to claim 2, wherein when removing a part of the insulator, at least one of a dry etching process, a wet etching process, and a process by mechanical polishing is used.   The method for manufacturing a printed wiring board according to claim 3, wherein anisotropic etching is performed in the dry etching process.   The wet etching process uses a solution containing at least one of chromic acid, chromate, dichromate, manganate, permanganate, ozone, hydrogen peroxide / sulfuric acid, and nitric acid. Item 4. A printed wiring board manufacturing method according to Item 3.   The method for manufacturing a printed wiring board according to claim 3, wherein at least one of baffle, sandpaper, and sandblast is used in the process by mechanical polishing.   The manufacturing method of the printed wiring board as described in any one of Claims 1-6 in which the said insulator has a thermosetting organic insulating material as a main component. A semiconductor for connecting the plurality of copper wirings provided on one surface of the printed wiring board manufactured by the method for manufacturing a printed wiring board according to claim 1 to a semiconductor chip. Chip connection terminal,
A method for manufacturing a semiconductor chip mounting board, wherein the plurality of copper wirings provided on the other surface of the printed wiring board are external connection terminals. Multiple copper wires,
A nickel plating film and a gold plating film sequentially provided on the plurality of copper wirings, or a nickel plating film, a palladium plating film and a gold plating film sequentially provided on the plurality of copper wirings;
An insulator disposed between the plurality of copper wirings;
A printed wiring board comprising:   The printed wiring board according to claim 9, wherein the insulator is mainly composed of a thermosetting organic insulating material. A printed wiring board according to claim 9 or 10,
The plurality of copper wirings provided on one surface of the printed wiring board are semiconductor chip connection terminals for connecting to a semiconductor chip,
A semiconductor chip mounting board, wherein the plurality of copper wirings provided on the other surface of the printed wiring board are external connection terminals. A semiconductor chip mounting substrate according to claim 11,
The semiconductor chip mounted on the semiconductor chip mounting substrate;
A semiconductor package comprising:

Images