JP2006344873A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

A semiconductor device capable of reducing junction leakage current by forming a silicide layer without increasing the area of a source / drain region and a method for manufacturing the same are provided.
A gate insulating film and a gate electrode are formed on an active region partitioned by an element isolation region formed on a semiconductor substrate. A source / drain region 16 is formed in the semiconductor substrate 11 located on the side of the side surface of the gate electrode 14 and below the side wall insulating film 15. Then, a protective insulating film 17 is formed to cover the element isolation region 12 and the corner portion 16 a of the source / drain region 16. By this protective insulating film 17, a silicide layer 18a is formed on the source / drain region 16 except for the corner portion 16a. Thereby, the junction leakage current generated at the corner portion 16a of the source / drain region 16 can be reduced.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a MIS transistor having a silicide layer in a source / drain region and a manufacturing method thereof.

  In recent years, with miniaturization, high integration, and high speed, a semiconductor device has a silicide layer formed on a gate electrode or a source / drain region by using a salicide technique in order to reduce parasitic resistance in the gate electrode or the source / drain region. Is forming. In such a configuration, it has become important to suppress junction leakage current from the source / drain region to the substrate, which is caused by forming a silicide layer on the source / drain region.

  Therefore, conventionally, a method has been proposed in which the silicide layer is formed apart from the end of the element isolation region (see, for example, Patent Document 1).

  A conventional semiconductor device having a silicide layer in the source / drain region will be described below with reference to the drawings. 8A and 8B are diagrams illustrating a configuration of a conventional semiconductor device, in which FIG. 8A is a plan view and FIG. 8B is a cross-sectional view taken along line XX in FIG.

  8 includes an element isolation region 102 formed in a semiconductor substrate 101, a gate insulating film 103 formed on an active region including a semiconductor substrate 101 surrounded by the element isolation region 102, and a gate insulating film. The gate electrode 104 formed on the gate electrode 103, the side wall insulating film 105 formed on the side surface of the gate electrode 104, and the source / drain region 106 formed on the semiconductor substrate 101 located below the side wall insulating film 105. And an insulating film 107 covering the periphery of the element isolation region 102 and the source / drain region 106, and a silicide layer 108 formed on the source / drain region 106 exposed in the opening of the insulating film 107.

In this conventional configuration, since the peripheral portion on the source / drain region 106 in contact with the element isolation region 102 is covered with the insulating film 107, the source / drain region 106 separated from the end portion 102 a of the element isolation region 102. A silicide layer 108 is formed thereon. As a result, the silicide layer 108 is separated from the junction position between the source / drain region 106 and the semiconductor substrate 101, so that junction leakage current can be reduced.
Japanese Patent Laid-Open No. 7-14847

  However, in the conventional configuration as described above, the insulating film 107 is formed from the end portion 102 a of the element isolation region 102 to the position where it enters the peripheral portion on the source / drain region 106. Therefore, it is necessary to make the area of the source / drain region 106 larger than the area of the silicide layer 108, and there is a problem that the area of the active region of the MIS transistor increases.

  An object of the present invention is to provide a semiconductor device capable of reducing junction leakage current by forming a silicide layer without increasing the area of a source / drain region, and a method for manufacturing the same.

  A semiconductor device of the present invention includes an element isolation region formed in a semiconductor substrate, an active region made of a semiconductor substrate surrounded by the element isolation region, and a silicide layer formed on the active region, In addition, a silicide layer is not formed at least on a corner portion in contact with the element isolation region.

  In the semiconductor device, a protective film is formed on a corner portion in contact with the element isolation region.

  In the semiconductor device, the gate electrode formed on the active region, the sidewall insulating film formed on the side surface of the gate electrode, and the source / drain region formed in the active region located below the side wall insulating film The silicide layer is not formed on the corner portion of the source / drain region.

  In the semiconductor device, a silicide layer is formed on the source / drain region located between the corner portion of the source / drain region where the silicide layer is not formed and the sidewall insulating film.

  In the semiconductor device, a dummy gate electrode and a dummy side wall insulating film formed from a conductive film and an insulating film common to the gate electrode and the side wall insulating film are provided on corner portions of the source / drain regions.

  In the semiconductor device, the silicide layer is not formed at both ends in the gate width direction of the source / drain regions including the corner portion.

  In the semiconductor device, a gate electrode formed on the active region, a dummy gate electrode portion that covers both ends of the active region in the gate width direction and is integrally formed with the gate electrode, and the gate electrode and the dummy gate electrode Both end portions in the gate width direction of the active region including the corner portion, including a sidewall insulating film formed on the side surface of the portion and a source / drain region formed in the active region located laterally below the sidewall insulating film A silicide layer is not formed on the top.

  The method for manufacturing a semiconductor device of the present invention includes a step (a) of forming an element isolation region in a semiconductor substrate and a step of selectively forming a silicide layer on an active region made of a semiconductor substrate surrounded by the element isolation region. (B), and in the step (b), a silicide layer is not formed on at least a corner portion in contact with the element isolation region in the active region.

  In the semiconductor device manufacturing method, after the step (a), before the step (b), there is a step of forming a protective film on a corner portion in contact with the element isolation region in the active region.

  In the semiconductor device manufacturing method, after step (a) and before step (b), a step (c) of forming a gate electrode on the active region, and a sidewall insulating film on the side surface of the gate electrode A step (d), a step (e) of forming a source / drain region in the active region located laterally below the side wall insulating film, and a protective film (f) on the corner portion of the source / drain region. In step (b), a silicide layer is formed on the source / drain regions using the protective film as a silicide formation prevention film.

  In the semiconductor device manufacturing method, after step (a) and before step (b), a step (c) of forming a gate electrode on the active region, and a sidewall insulating film on the side surface of the gate electrode And a step (e) of forming a source / drain region in the active region located laterally below the side wall insulating film. In the step (c), a dummy gate is formed on a corner portion of the active region. In step (d), a dummy sidewall insulating film is formed on the side surface of the dummy gate electrode. In step (b), the dummy gate electrode and the dummy sidewall protective film are used as silicide formation prevention films to form source / drain. A silicide layer is formed on the region.

  According to the present invention, the silicide layer on the active region is formed on the active region except for the corner portion. Thereby, according to this configuration, since the silicide layer is not formed at the corner portion of the active region, the junction leakage current at the corner portion of the active region caused by the formation of the silicide layer can be reduced. Furthermore, since it is not necessary to make the active region larger than the silicide formation region as in the conventional configuration, the area of the active region can be reduced.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
1A and 1B are diagrams illustrating a configuration of a semiconductor device according to a first embodiment of the present invention, in which FIG. 1A is a plan view, FIG. 1B is a cross-sectional view taken along a line A1-A1 in FIG. c) is a cross-sectional view taken along a line A2-A2 in FIG.

  1 includes an element isolation region 12 formed in a semiconductor substrate 11, a gate insulating film 13 formed on an active region including the semiconductor substrate 11 surrounded by the element isolation region 12, and a gate insulating film. 13, a side wall insulating film 15 formed on the side surface of the gate electrode 14, and a source / drain region 16 formed in the semiconductor substrate 11 located below the side wall insulating film 15. A protective insulating film 17 covering the element isolation region 12 and the corner portion 16a of the source / drain region 16, a silicide layer 18a formed on a region of the source / drain region 16 excluding the corner portion 16a, and the gate electrode 14 A silicide layer 18b formed thereon is provided. The protective insulating film 17 is formed so as to cover the entire region of the element isolation region 12 except the region where the gate electrode 14 and the sidewall insulating film 15 are formed.

  The semiconductor device manufacturing method according to the first embodiment of the present invention will be described below with reference to FIG. 2A to 2E are cross-sectional views illustrating a manufacturing process of the semiconductor device according to the first embodiment of the present invention, and are cross-sectional views taken along a line A1-A1 in FIG.

  First, in the step shown in FIG. 2A, a trench type element isolation region 12 is formed on a P type semiconductor substrate 11 by using an STI technique to partition an active region made of the semiconductor substrate 11 serving as an element formation region. To do. Thereafter, a silicon oxide film and a polycrystalline silicon film are sequentially formed on the active region in the semiconductor substrate 11, and then the silicon oxide film and the polycrystalline silicon film are patterned to form a gate insulating film 13 on the active region in the semiconductor substrate 11. A gate electrode 14 is formed. Thereafter, N-type impurity ions are implanted into the semiconductor substrate 11 using the gate electrode 14 as a mask, and an N-type extension region (not shown) is formed in the semiconductor substrate 11 located laterally below the gate electrode 14. .

  Next, in the step shown in FIG. 2B, an insulating film is deposited on the entire surface of the semiconductor substrate 11 and then etched back to form a sidewall insulating film 15 on the side surface of the gate electrode 14. Thereafter, ion implantation of N-type impurities is performed in the semiconductor substrate 11 using the gate electrode 14, the sidewall insulating film 15, and the element isolation insulating film 12 as a mask, and the semiconductor substrate 11 located below the sidewall insulating film 15 is implanted. N-type source / drain regions 16 are formed.

  Next, in the step shown in FIG. 2C, a silicon oxide film having a thickness of 50 nm is formed on the entire surface of the semiconductor substrate 11 by using the CVD technique. Thereafter, a resist (not shown) is formed on the silicon oxide film so as to cover the corner portion of the source / drain region 16 that is in contact with the element isolation region 12 in two directions and has an opening on the region excluding the corner portion. To do. Thereafter, using the resist as a mask, the silicon oxide film is etched by dry etching or wet etching technique, so that the element isolation in the source / drain region 16 is performed as shown in the plan view of FIG. A protective insulating film 17 is formed to cover the four corner portions 16 a that are in two directions in contact with the end portion 12 a of the region 12. At this time, it is desirable to remove the silicon oxide film on the gate electrode 14 to expose the upper surface of the gate electrode 14. In this embodiment, the protective insulating film 17 is formed so as to cover the entire surface of the element isolation region 12 that is exposed. However, as shown in the plan view of the modified example of FIG. 17 may be formed so as to cover at least the corner portion 16 a of the source / drain region 16 including the end portion 12 a of the element isolation region 12.

  Next, in the step shown in FIG. 2D, a refractory metal film 18 made of a cobalt (Co) film having a thickness of 10 nm is formed on the entire surface of the semiconductor substrate 11. At this time, it is desirable to form a protective film (not shown) made of a TiN film having a thickness of 15 nm on the refractory metal film 18. As the refractory metal film 18, for example, a titanium (Ti) film or a nickel (Ni) film can be used instead of the cobalt (Co) film.

  Next, in the step shown in FIG. 2E, the exposed silicon (Si) reacts with the refractory metal film 18 by subjecting the semiconductor substrate 11 to RTA treatment (heat treatment) at about 500 ° C. for about 1 minute. Thus, a silicide layer 18a and a silicide layer 18b are formed on the source / drain region 16 and the gate electrode 14, respectively. Thereafter, the unreacted refractory metal film 18 remaining without reacting with Si is selectively removed.

  According to the semiconductor device and the manufacturing method thereof of the first embodiment, the silicide layer 18a on the source / drain region 16 is formed on the source / drain region 16 except for the corner portion 16a. According to this configuration, the protective insulating film 17 formed on the corner portion 16a of the source / drain region 16 serves as a protective film, and the silicide layer is not formed on the corner portion 16a of the source / drain region 16. The junction leakage current in the corner portion 16a of the source / drain region 16 caused by the above can be reduced. Further, a silicide layer 18a is formed on the entire surface of the source / drain region 16 except for the corner portion 16a. Therefore, unlike the conventional structure shown in FIG. 8, it is not necessary to make the source / drain region larger than the silicide formation region, so that the area of the source / drain region can be reduced.

(Modification of the first embodiment)
4A and 4B are diagrams showing a configuration of a modification of the semiconductor device according to the first embodiment of the present invention, where FIG. 4A is a plan view, and FIG. 4B is a cross-section at B1-B1 in FIG. FIG. 4C is a cross-sectional view taken along B2-B2 in FIG.

  In the semiconductor device according to the first embodiment shown in FIG. 1, an insulating film 17 is formed so as to cover the corner portion 16a of the source / drain region 16, thereby forming a silicide layer on the source / drain region 16 excluding the corner portion 16a. 18a is formed. At this time, the gate electrode 14 and the insulating film 17 formed at the corner are formed apart from each other, and a silicide layer 18a is formed on the source / drain region 16 positioned therebetween. Therefore, the silicide layer 18a is formed in a region excluding the corner portion 16a in both ends of the source / drain region 16 in the gate width direction.

  On the other hand, as shown in FIG. 4, the semiconductor device of this modification example is formed by forming the insulating film 17 so as to cover both end portions 16b including the corner portions of the source / drain regions 16 in the gate width direction. A silicide layer 18a is formed on the source / drain region 16 excluding both end portions 16b. Therefore, this modification is different from the semiconductor device shown in FIG. 1 in that no silicide layer is formed in the entire region of both end portions 16 b of the source / drain region 16. Since other structures have the same structure as the semiconductor device shown in FIG. 1, description thereof is omitted here.

  According to this modification, the silicide layer 18a on the source / drain region 16 is formed on a region excluding both end portions 16b of the source / drain region 16 in the gate width direction. According to this configuration, the insulating film 17 formed on the both end portions 16b of the source / drain regions 16 serves as a protective film, and no silicide layer is formed on the both end portions 16b including the corner portions of the source / drain regions 16. Junction leakage current at the corners of the source / drain regions 16 caused by the silicide layer formation can be reduced. Further, a silicide layer 18a is formed on the entire surface of the source / drain region 16 except for both end portions 16b including the corner portion. Therefore, unlike the conventional structure shown in FIG. 8, it is not necessary to make the source / drain region larger than the silicide formation region, so that the area of the source / drain region can be reduced.

(Second Embodiment)
5A and 5B are diagrams illustrating a configuration of a semiconductor device according to the second embodiment of the present invention, in which FIG. 5A is a plan view, FIG. 5B is a cross-sectional view taken along C1-C1 in FIG. c) is a cross-sectional view taken along the line C2-C2 in FIG.

  A semiconductor device shown in FIG. 5 includes an element isolation region 12 formed on a semiconductor substrate 11, a gate insulating film 13 formed on an active region including the semiconductor substrate 11 surrounded by the element isolation region 12, and a gate insulating film. 13, a side wall insulating film 15 formed on the side surface of the gate electrode 14, and a source / drain region 16 formed in the semiconductor substrate 11 located below the side wall insulating film 15. A dummy gate electrode 14a formed via a dummy gate insulating film 13a so as to cover a corner portion 16a of the source / drain region 16 and a part of the element isolation region 12 adjacent to the corner portion 16a, and a dummy gate electrode 14a The dummy sidewall insulating film 15a formed on the side surface of the source and drain region 16 of the source / drain region 16 except for the corner portion 16a. It includes a layer 18a, and a silicide layer 18b formed on the gate electrode 14, a silicide layer 18c formed on the dummy gate electrode 14a. Here, the dummy gate electrode 14a and the dummy sidewall insulating film 15a serve as a protective film, and the silicide layer 18a is formed in the corner portion 16a of the source / drain region 16 covered with the dummy gate electrode 14a and the dummy sidewall insulating film 15a. Is not formed.

  A method for manufacturing a semiconductor device according to the second embodiment of the present invention will be described below with reference to FIG. 6A to 6C are cross-sectional views illustrating the manufacturing process of the semiconductor device according to the second embodiment of the present invention, and are cross-sectional views taken along the line C1-C1 in FIG.

  First, in the step shown in FIG. 6A, a trench-type element isolation region 12 is formed on a P-type semiconductor substrate 11 by using an STI technique to partition an active region made of the semiconductor substrate 11 serving as an element formation region. To do. Thereafter, a silicon oxide film and a polycrystalline silicon film are sequentially formed on the active region in the semiconductor substrate 11. Thereafter, the silicon oxide film and the polycrystalline silicon film are patterned to form the gate insulating film 13 and the gate electrode 14 on the active region in the semiconductor substrate 11, and the dummy gate insulating film 13a and the four gate portions of the active region. A dummy gate electrode 14a is formed. At this time, the dummy gate insulating film 13a and the dummy gate electrode 14a are formed so as to cover a corner portion of the active region and a part of the element isolation region adjacent to the corner portion. Thereafter, ion implantation of N-type impurities into the semiconductor substrate 11 is performed using the gate electrode 14 and the dummy gate electrode 14a as a mask, and an N-type extension region (not shown) is formed in the semiconductor substrate 11 located laterally below the gate electrode 14. Z).

  Next, in the step shown in FIG. 6B, an insulating film is deposited on the entire surface of the semiconductor substrate 11 and then etched back to form a sidewall insulating film 15 on the side surface of the gate electrode 14 and a dummy. A dummy sidewall insulating film 15a is formed on the side surface of the gate electrode 14a. Thereafter, N-type impurity ions are implanted into the semiconductor substrate 11 using the gate electrode 14, the sidewall insulating film 15, the dummy gate electrode 14a, the dummy sidewall insulating film 15a, and the element isolation insulating film 12 as a mask. N-type source / drain regions 16 are formed in the semiconductor substrate 11 located on the lower side.

  Next, after forming a refractory metal film made of a cobalt (Co) film having a thickness of 10 nm on the entire surface of the semiconductor substrate 11 in the step shown in FIG. By performing the RTA process (heat treatment), the exposed silicon (Si) and the refractory metal film 18 are reacted to form the silicide layer 18a on the source / drain regions 16, the gate electrode 14, and the dummy gate electrode 14a. The silicide layer 18b and the silicide layer 18c are formed. Thereafter, the unreacted refractory metal film remaining without reacting with Si is selectively removed. At this time, it is desirable to form a protective film made of a TiN film on the refractory metal film. As the refractory metal film, for example, a titanium (Ti) film or a nickel (Ni) film can be used instead of the cobalt (Co) film.

  According to the semiconductor device and the manufacturing method thereof of the second embodiment, the silicide layer 18a on the source / drain region 16 is formed on the source / drain region 16 except for the corner portion 16a. According to this configuration, the dummy gate electrode 14a and the dummy sidewall insulating film 15a serve as a protective film, and no silicide layer is formed at the corner portion 16a of the source / drain region 16, so that the source / drain region 16 generated by the silicide layer formation is formed. The junction leakage current at the corner portion 16a can be reduced. Further, a silicide layer 18a is formed on the entire surface of the source / drain region 16 except for the corner portion 16a. Therefore, unlike the conventional structure shown in FIG. 8, it is not necessary to make the source / drain region larger than the silicide formation region, so that the area of the source / drain region can be reduced.

(Modification of the second embodiment)
7A and 7B are diagrams showing a configuration of a modified example of the semiconductor device according to the second embodiment of the present invention, in which FIG. 7A is a plan view and FIG. 7B is a cross-section taken along D1-D1 in FIG. FIG. 7C is a cross-sectional view taken along the line D2-D2 in FIG.

  In the semiconductor device according to the second embodiment shown in FIG. 5, a corner film 16a is formed by forming a protective film including a dummy gate electrode 14a and a dummy sidewall insulating film 15a so as to cover the corner parts 16a of the source / drain regions 16. A silicide layer 18a is formed on the source / drain region 16 except for. At this time, the gate electrode 14 and the dummy gate electrode 14a are formed apart from each other, and a silicide layer 18a is formed on the source / drain region 16 positioned therebetween. Therefore, the silicide layer 18a is formed in a region excluding the corner portion 16a in both ends of the source / drain region 16 in the gate width direction.

  On the other hand, as shown in FIG. 7, the semiconductor device of the present modification includes dummy gate electrode portions 14x formed integrally with the gate electrode 14 so as to cover both end portions 19a of the active region 19 in the gate width direction. By forming, the source / drain region 16 and the silicide layer 18a are not formed at both end portions 19a of the active region 19 in the gate width direction. Therefore, this modification is different from the semiconductor device shown in FIG. 5 in that the source / drain regions 16 and the silicide layer 18a are not formed at both end portions 19a of the active region 19 in the gate width direction. Since other structures have the same structure as the semiconductor device shown in FIG. 5, the description thereof is omitted here.

  According to this modification, the source / drain region 16 and the silicide layer 18a are formed in a region excluding both end portions 19a of the active region 19 in the gate width direction. According to this configuration, the dummy gate electrode portion 14x formed integrally with the gate electrode 14 formed on the both end portions 19a of the active region 19 serves as the protective film, and the end portions 19a including the corner portions of the active region 19 are formed on the both end portions 19a. Since the source / drain regions and the silicide layer are not formed, the junction leakage current at the corner of the active region 19 caused by the formation of the silicide layer can be reduced. Further, a silicide layer 18a is formed on the entire surface of the source / drain region 16 except for both end portions 19a of the active region 19 including the corner portion. Therefore, unlike the conventional structure shown in FIG. 8, it is not necessary to make the source / drain region larger than the silicide formation region, so that the area of the source / drain region can be reduced.

  As described above, the present invention is useful for a semiconductor device having a silicide layer in a source / drain region.

BRIEF DESCRIPTION OF THE DRAWINGS It is a figure which shows the structure of the semiconductor device which concerns on the 1st Embodiment of this invention, (a) is a top view, (b) is sectional drawing in A1-A1 location of Fig.1 (a), (c) is a figure. Sectional drawing in A2-A2 location of 1 (a) (A)-(e) is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. FIG. 2A is a plan view in the step shown in FIG. 2C, and FIG. 2B is a plan view of a modification in the step shown in FIG. It is a figure which shows the structure of the modification of the semiconductor device which concerns on the 1st Embodiment of this invention, (a) is a top view, (b) is sectional drawing in B1-B1 location of Fig.4 (a), (c ) Is a cross-sectional view at B2-B2 in FIG. It is a figure which shows the structure of the semiconductor device which concerns on the 2nd Embodiment of this invention, (a) is a top view, (b) is sectional drawing in C1-C1 location of Fig.5 (a), (c) is a figure. Sectional drawing in C2-C2 location of 5 (a) (A)-(c) is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is a figure which shows the structure of the modification of the semiconductor device which concerns on the 2nd Embodiment of this invention, (a) is a top view, (b) is sectional drawing in D1-D1 location of Fig.7 (a), (c ) Is a cross-sectional view taken along the line D2-D2 in FIG. It is a figure which shows the structure of the conventional semiconductor device, (a) is a top view, (b) is sectional drawing in the XX location of Fig.8 (a).

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 Semiconductor substrate 12 Element isolation region 12a End part 13 Gate insulating film 13a Dummy gate insulating film 14 Gate electrode 14a Dummy gate electrode 14x Dummy gate electrode part 15 Side wall insulating film 15a Dummy side wall insulating film 16 Source / drain region 16a Corner part 16b End Part 17 protective insulating film 18 high melting point metal film 18a, 18b, 18c silicide layer 19 active region 19a end

Claims (11)

An element isolation region formed in a semiconductor substrate;
An active region comprising the semiconductor substrate surrounded by the element isolation region;
A silicide layer formed on the active region,
The semiconductor device according to claim 1, wherein the silicide layer is not formed on at least a corner portion in contact with the element isolation region in the active region. The semiconductor device according to claim 1,
A semiconductor device, wherein a protective film is formed on the corner portion in contact with the element isolation region. The semiconductor device according to claim 1 or 2,
A gate electrode formed on the active region;
A sidewall insulating film formed on a side surface of the gate electrode;
A source / drain region formed in the active region located laterally below the sidewall insulating film,
The semiconductor device, wherein the silicide layer is not formed on the corner portion of the source / drain region. The semiconductor device according to claim 3.
A semiconductor in which the silicide layer is formed on the source / drain region positioned between a corner portion of the source / drain region where the silicide layer is not formed and the sidewall insulating film. apparatus. The semiconductor device according to claim 3 or 4,
A semiconductor device having a dummy gate electrode and a dummy sidewall insulating film formed of a conductive film and an insulating film in common with the gate electrode and the sidewall insulating film on a corner portion of the source / drain region. The semiconductor device according to claim 3.
2. The semiconductor device according to claim 1, wherein the silicide layer is not formed at both ends in the gate width direction of the source / drain region including the corner portion. The semiconductor device according to claim 1,
A gate electrode formed on the active region;
A dummy gate electrode portion that covers both ends of the active region in the gate width direction and is integrally formed with the gate electrode;
Sidewall insulating films formed on side surfaces of the gate electrode and the dummy gate electrode portion;
A source / drain region formed in the active region located laterally below the sidewall insulating film,
The semiconductor device is characterized in that the silicide layer is not formed on both end portions in the gate width direction of the active region including the corner portion. Forming an element isolation region in a semiconductor substrate (a);
(B) selectively forming a silicide layer on the active region made of the semiconductor substrate surrounded by the element isolation region;
In the step (b), the silicide layer is not formed on at least a corner portion in contact with the element isolation region in the active region. The method of manufacturing a semiconductor device according to claim 8.
After the step (a) and before the step (b), a semiconductor device comprising a step of forming a protective film on the corner portion in contact with the element isolation region in the active region Manufacturing method. In the manufacturing method of the semiconductor device according to claim 9,
After the step (a) and before the step (b),
Forming a gate electrode on the active region (c);
Forming a sidewall insulating film on a side surface of the gate electrode;
Forming a source / drain region in the active region located laterally below the sidewall insulating film;
(F) forming the protective film on corner portions of the source / drain regions,
In the step (b), the silicide layer is formed on the source / drain regions by using the protective film as a silicide formation prevention film. In the manufacturing method of the semiconductor device according to claim 9,
After the step (a) and before the step (b),
Forming a gate electrode on the active region (c);
Forming a sidewall insulating film on a side surface of the gate electrode;
And (e) forming a source / drain region in the active region located laterally below the sidewall insulating film,
In the step (c), a dummy gate electrode is formed on a corner portion of the active region,
In the step (d), a dummy sidewall insulating film is formed on a side surface of the dummy gate electrode,
In the step (b), the silicide layer is formed on the source / drain regions by using the dummy gate electrode and the dummy sidewall protective film as a silicide formation preventing film.

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