JP2006329737A - Semiconductor integrated circuit device and its test method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device and its test method permitting timing control at high accuracy and improving failure detection rate by fewer test patterns. <P>SOLUTION: The semiconductor integrated circuit device includes a plurality of circuit blocks, an internal clock generation circuit forming its clock, and a test circuit. A first circuit of the test circuit selectively transmits an external clock for scanning or the clock formed by the internal clock generation circuit, in response to a first control signal for performing an operational test of the plurality of circuit blocks. A second circuit of the test circuit is provided to each of the plurality of circuit blocks, receives the clock formed by the first circuit, and forms an internal control signal for switching a selector provided to an input part of a flip-flop circuit constituting a scan chain from the scan change side to the front stage logic side. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit device and a test method therefor, and more particularly to a technique effective when used in a scan test technique for detecting a delay fault in an internal circuit.

  A scan test is known as a method for testing an LSI (semiconductor integrated circuit device) internal circuit. The scan test is performed by synchronizing the LSI internal circuit and the external input / output unit to the same clock. However, while the LSI operates at a high speed, the LSI external input / output operation is slow relative to the LSI due to the limitation of the signal transmission speed at the tester and the input / output unit of the LSI. Therefore, the scan test speed is limited by the tester operating speed and the LSI external input / output operation. For this reason, it is difficult to perform a scan test in a test for inspecting a delay fault for confirming the operation at the LSI actual speed.

  With the recent miniaturization of LSI processes, there is an increasing need for delay fault detection in scan tests. As a means for performing a test at an LSI actual speed, there is a method of performing an actual speed test using an internally generated clock inside the LSI using a tester that can be tested at a high speed operation. The former is difficult to realize in terms of cost. The latter can be realized by providing a test circuit inside the LSI for an actual speed scan test. The existence of the following publicly known example regarding the test circuit for the scan test for such an actual speed was reported by a patent search.

Japanese Patent Laid-Open No. 2002-289976 discloses an example in which a substantially high-speed test is possible by generating a capture clock having a time interval shorter than the time interval of the scan shift clock. Japanese Patent Laid-Open No. 2003-004807 discloses an example in which scan data is shifted in with a low-frequency clock, and then this data is re-shifted with a high-frequency clock generated internally and then captured. As an example that enables real-time testing by using a low-speed clock during shift, using a PLL clock during real-speed test operation, and generating a one-cycle shift / capture switching signal from the pulse control output signal There is an open 2002-196046 gazette. A low frequency clock is used during scan shift, and a PLL generated clock is used during capture. This clock has two cycles, and Japanese Patent Laid-Open No. 2003-014822 is an example of enabling a real-time test by turning the combinational circuit twice.
JP 2002-289976 A JP 2003-004807 A JP 2002-196046 A JP 2003-014822 A

  In Patent Document 1, the shift / capture switching timing (scan enable timing) is not considered. In an actual semiconductor device test, scan enable timing design becomes a problem. In Patent Document 2, since there is a period during which a shift operation is performed with a high-frequency clock, the shift operation needs to be performed at high speed. One cycle of the capture clock is extracted at the time of the test. However, since the capture timing generation circuit is provided in the test control circuit, there is a problem that the shift / capture switching timing becomes difficult depending on the logic.

  In Patent Document 3, a scan enable signal for switching a shift mode and a capture mode at the time of a scan test is performed by an external input / output unit, and high-speed operation is impossible. Normally, in the scan test, the test is performed by a single clock method in which a test is performed by applying a clock once in the capture mode. In this method, after data is transferred to the flip-flop circuit in the shift mode, the scan enable is switched and the test is performed in the capture mode. In this method, the clock in the capture mode is one time, and the failure detection rate is likely to increase because the inside of the LSI can be considered as a combinational circuit by the shift operation. However, the actual speed scan test has a problem that it is necessary to operate the scan enable at a high speed and with high accuracy.

  In Patent Document 4, a double clock test is used in which a test is performed by applying a clock twice during capture operation. In this method, the scan enable is set to the capture mode side before the first clock application, and then the test is performed by applying the clock twice. Since scan enable does not need to be switched in the test cycle, timing problems can be alleviated. However, in the double clock method, since the clock is applied twice in the capture mode, it is handled as a two-stage sequential circuit in the test. For this reason, compared with the single clock system as in Patent Document 3, the failure detection rate is difficult to increase, and there is a problem that the test pattern becomes long.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device and a test method in which the failure detection rate is improved with a small number of test patterns while enabling timing control with high accuracy. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. A semiconductor integrated circuit device having a plurality of circuit blocks and an internal clock generation circuit for generating a clock thereof is provided with a test scan circuit having the following first circuit and second circuit. The first circuit selectively selects a scan external clock or a clock formed by the internal clock generation circuit in response to a first control signal supplied from the outside in order to perform an operation test of the plurality of circuit blocks. Tell. The second circuit is provided in each of the plurality of circuit blocks, and is provided in an input portion of a flip-flop circuit that receives a clock formed by the first circuit and forms a scan chain of the corresponding circuit block. An internal control signal for switching the selected selector from the scan chain side to the preceding logic side is formed.

  The outline of other representative ones of the inventions disclosed in the present application will be briefly described as follows. As a test method for a semiconductor integrated circuit device comprising a logic circuit, an internal clock generation circuit for forming the clock, and a scan test circuit for performing an operation test of the logic circuit with both a single clock pattern and a double clock pattern, the single clock is used. After the test with the pattern, the test with the double clock pattern is supplementarily performed.

  The failure detection rate can be improved with a small number of test patterns while enabling highly accurate timing control adapted to the clock delay in the clock transmission path.

  FIG. 1 is a schematic overall configuration diagram of an embodiment of a semiconductor integrated circuit device according to the present invention. The semiconductor integrated circuit device (hereinafter simply referred to as LSI) of this embodiment includes a PLL circuit that constitutes an internal clock generation circuit and a plurality of partial circuits A and B that operate with the clock formed thereby. The PLL circuit receives a reference clock RCLK and forms a high frequency system clock CLK by multiplying the reference clock RCLK.

  The partial circuits A and B are, for example, circuit blocks divided according to function, and are not particularly limited. However, the partial circuits A and B are not specifically limited. Corresponds to a logic circuit block or the like directed to the signal processing. In addition, the partial circuits A and B may be configured by geometrically dividing logic circuit blocks that realize one function. Alternatively, the partial circuits A and B include a plurality of circuit blocks divided according to the function and a partial block obtained by geometrically dividing the one functional block as described above. It may be. In the figure, as the plurality of circuit blocks, two such as a partial circuit A and a partial circuit B are exemplarily shown as representatives.

  In this embodiment, a capture enable generation circuit, an internally generated clock control circuit, and scan enable generation circuits A and B are provided as scan test circuits for detecting delay faults in the partial circuits A and B. Although not particularly limited, a chip scan enable signal CSEN, a scan shift clock SCLK, and a scan test mode signal SCTM are supplied from external terminals as test signals necessary for the operation of the scan test circuit. The capture enable generation circuit is controlled by a test control circuit (not shown) to generate a capture enable signal CPEN and a reset signal RESET.

  The internally generated clock control circuit is controlled by the scan test mode signal SCTM, the capture enable signal CPEN and the reset signal RSET, and outputs the shift clock SCLK or a test clock corresponding to the clock CLK as the internal clock clk in the test mode. . In the normal operation mode (user mode), the internal clock clk corresponding to the clock CLK is constantly supplied to the partial circuits A and B.

  In the scan test circuit of this embodiment, in order to detect a delay fault in the partial circuits A and B, in other words, signal propagation in the combinational circuit is performed within one cycle of the system clock CLK formed by the PLL circuit. It is detected that In this case, it is fully conceivable that the partial circuit A and the partial circuit B are slightly different in phase due to the difference in the clock propagation path of the system clock CLK formed by the PLL circuit. In this embodiment, even if there is a difference in the propagation delay time of the system clock between the partial circuits A and B as described above, no trouble occurs in the detection of the delay faults of the partial circuits A and B. Therefore, dedicated scan enable generation circuits A and B are provided respectively.

  In the partial circuit A, the selector provided in the input part of the flip-flop circuit constituting the logic stage and the scan chain is controlled by the scan enable signal formed by the scan enable generation circuit A, and the scan chain and the logic stage are controlled. Perform switching control. Similarly, in the partial circuit B, the selector provided in the input part of the flip-flop circuit constituting the logic stage and the scan chain is controlled by the scan enable signal formed by the scan enable generation circuit B, and the scan chain and Perform logic stage switching control. In other words, the scan enable generation circuits A and B form the scan enable signal corresponding to the clocks input to the partial circuits A and B that are responsible for the scan enable generation circuits A and B due to the difference in the clock propagation path of the system clock CLK. Even if the phases are slightly different, they do not hinder the detection of the delay fault.

  FIG. 2 is a block diagram showing an embodiment of the flip-flop circuit (hereinafter referred to as FF) in FIG. The FF includes a master flip-flop circuit MFF and a slave flip-flop circuit SFF. The master flip-flop circuit MFF takes in and outputs the first input signal when the internal clock clk is at a low level. At this time, the slave flip-flop circuit SFF holds the input signal captured before the first input signal. When the internal clock clk changes to a high level, the master flip-flop circuit MFF holds the first input signal, and the slave flip-flop circuit SFF takes in the first input signal and outputs it. As a result, the input signal is transmitted from the slave flip-flop circuit SFF to the scan output SO or the subsequent logic stage as indicated by the dotted line.

  When the internal clock clk changes to a low level, the master flip-flop circuit MFF takes in the second input signal, but the slave flip-flop circuit SFF holds the fetched first input signal. When the internal clock clk changes to a high level, the master flip-flop circuit MFF holds the second input signal, and the slave flip-flop circuit SFF takes in the second input signal and outputs it. As a result, the input signal is transmitted from the slave flip-flop circuit SFF to the scan output SO or the subsequent logic stage as indicated by the dotted line. That is, the input signal is sequentially transmitted for each cycle of the internal clock clk.

  A selector MUX is provided at the input portion of the master flip-flop circuit MFF, and a scan-in terminal that receives the scan-out SO of the preceding flip-flop circuit so as to be chain-connected in a scan operation by a selection signal (scan enable signal) SEN. SI is selected. In the normal operation or test operation, the input terminal Din that receives the output signal of the combinational circuit is selected. As a result, the scan enable signal SEN switches between a scan operation for acquiring a test input signal and outputting a test result, a test operation for detecting the delay fault, and a normal operation.

  When the selector MUX selects the scan-in terminal SI by the scan enable signal SEN, since the FFs are chain-connected as described above, the serial input of the test pattern and the serial of the test result are synchronized with the clock clk. Output is done. When the selector MUX selects the input terminal Din by the scan enable signal SEN, a signal that has passed through the combinational circuit, which is the previous logic stage, is captured at the high level timing of the clock clk and before the previous cycle is captured. The logic stage signal is output to the next logic stage to perform the sequence operation. In this sequence operation, if the delay in the logic stage is longer than one cycle of the clock clk, the input signal cannot be captured and malfunctions. This is a delay fault.

  The detection of such a delay fault is based on the premise that the selector MUX is switched in synchronization with the change of the clock clk. If the scan enable signal is delayed with respect to the clock clk, even though the signal is correctly transmitted from the logic stage to the input part of the FF, the capture fails and apparently a delay fault It will be judged. On the contrary, if the scan enable signal changes quickly with respect to the clock clk, the final test pattern cannot be transmitted with a single clock pattern as will be described later, and as a result, the test with the correct single clock pattern cannot be performed. . In other words, most of the output will not match the expected value.

  FIG. 3 is a block diagram showing an embodiment of the internally generated clock control circuit shown in FIG. This internally generated clock control circuit is selected according to the shift clock SCLK supplied from the outside during the scan operation and the system clock (actual speed) CLK formed by the built-in PLL (clock generation circuit) during the scan test operation. Thus, the internal clock clk is formed. That is, in the scan operation, the test pattern is scanned in corresponding to the slow-speed shift clock SCLK, and the circuit test including the above-described delay fault detection by the test pattern corresponds to the high-speed system clock CLK. Scan test operation.

  The internally generated clock control circuit switches between the high-speed system clock CLK and the asynchronous shift clock SCLK. In the internally generated clock control circuit, when the scan test mode signal SCTM is at a high level (logic 1), the gate circuit G4 opens the gate, and the shift clock SCLK is transmitted as the internal clock clk through the OR gate circuit G5. Accordingly, the test signal is input in synchronization with the shift clock SCLK, and is transmitted to the flip-flop circuit FF through the scan chain.

  When the internal clock clk corresponding to the system clock CLK is formed, the input of the shift clock SCLK is stopped by external control. Then, the high level of the capture enable signal CPEN is captured in the opposite phase of the clock CLK, and the internally generated clock clk having the same cycle as the system clock is output for two cycles. That is, when two opposite phases of the internally generated clock CLK are input, the capture enable signal CPEN passes through the two FFs, and controls the gate circuit G1 to stop the internally generated clock.

  FIG. 4 shows a block diagram of an embodiment of the scan enable generation circuit of FIG. In this embodiment, the scan enable control corresponding to the single clock and the double clock is switched. The internal clock clk is supplied to the clock terminal of the flip-flop circuit FF4. An OR gate circuit G6 is provided at the data input of the flip-flop circuit FF4. The chip scan enable signal CSEN is input to one input of the OR gate circuit G6.

  The output signal of the flip-flop circuit FF4 is fed back to the other input of the gate circuit G6 through the inverter circuit NV3. The output of the flip-flop circuit FF4 is supplied to the AND gate circuit G7. The AND gate circuit G7 is supplied with a switching signal S / W between a single clock mode and a double clock mode. The output signal of the gate circuit G7 and the chip scan enable signal CSEN are output as the module scan enable signal MSEN through the OR gate circuit G8. That is, the module scan enable signal MSEN means that the partial circuit A and the partial circuit B are modules and are generated corresponding to the modules.

  FIG. 5 is a waveform diagram for explaining the operation of the scan enable generation circuit of FIG. In the single clock mode, the signal S / W is set to the high level. As shown in FIG. 5A, even if the chip scan enable signal CSEN is set to the low level, the flip-flop circuit FF4 outputs a high level (logic 1) until the first pulse of the clock clk arrives. . Therefore, the module scan enable signal MSEN that has passed through the gate circuits G6 and G8 is maintained at a high level. That is, the selector MUX provided in the input part of the scan flip-flop circuit FF in FIG. 2 selects the scan-in SI side. When the first clock clk arrives, the output of the flip-flop circuit FF changes to low level, and the module scan enable signal MSEN is correspondingly changed to low level. When the second clock clk arrives, the low level output is inverted and fed back by the inverter circuit NV3, so that the output of the flip-flop circuit FF changes to the high level again, and correspondingly, the module scan enable signal MSEN Is also made high.

  As a result, the final shift operation of the test signal is performed by the FF of the scan chain in synchronization with the first clock clk, and the test signal is transmitted to the logic stage (combination circuit), the memory, and the like. The signal transmitted through the logic stage, the memory, etc. is taken into the FF on the rear stage side in synchronization with the second clock clk. Since the module scan enable signal MSEN is set to the high level, the captured rear stage signal is output serially by supplying the high level of the shift clock SCLK again.

  In the double clock mode, the signal S / W is set to the low level. In this state, the gate of the gate circuit G7 is closed, and the module scan enable signal MSEN is set to low level by the chip scan enable signal CSEN being low level. The module scan enable signal MSEN is also set to high level by the high level of the chip scan enable signal CSEN. In this configuration, two pulses clk are output corresponding to the capture enable signal CPEN of FIG. In the double clock mode, the final shift operation of the test signal is also performed by the FF of the scan chain.

  In the double clock mode, the chip scan enable signal CSEN is set to the capture mode side before the first clock application, and then the test is performed by applying the clock twice. In this double clock mode, the module scan enable signal MSEN does not need to be switched within the test cycle, so the timing problem can be alleviated. However, in the double clock mode, since the clock is applied twice in the capture mode, it is handled as a two-stage sequential circuit in the test. For this reason, since it is not possible to directly recognize which of the two logic stages is a failure, the failure detection rate is less likely to be higher than in the single clock mode, and the test pattern is long.

  In this embodiment, by providing both the single clock mode and the double clock mode, the delay fault detection is performed in the single clock mode, and the auxiliary fault detection that cannot be performed in the single clock mode is performed in the double clock mode. By doing so, it is possible to detect a delayed failure with high reliability while preventing the test pattern from becoming longer.

  FIG. 6 shows a waveform diagram of the test operation in the single clock mode. In the scan-in operation, a test pattern is input from outside the LSI at a low speed in synchronization with the shift clock SCLK. This scan-in operation is stopped immediately before the final shift by the low level of the chip scan enable signal CSEN. Then, the capture enable signal CPEN is set to the high level by the capture enable generation circuit, so that two pulses of the high-speed clock clk corresponding to the system clock CLK are output. The final shift operation is performed by the first pulse of the clock clk, and the module scan enable signal MSEN is formed corresponding to each of the partial circuits A, B and the like in synchronization with the pulse clk. A delay fault test is performed at an actual speed corresponding to the clock CLK. [In this embodiment, although not particularly limited, the shift clock SCLK is formed using the reference clock RCLK. By adopting such a configuration, the external terminal for the shift clock SCLK can be omitted in FIG. ]

  FIG. 7 shows a waveform diagram of the test operation in the double clock mode. In the scan-in operation, a test pattern is input from the outside of the semiconductor integrated circuit device at a low speed in synchronization with the shift clock SCLK. [In this skin-in operation, the shift clock SCLK is stopped by the low level of the chip scan enable signal CSEN, and the test is performed until the final shift operation, and serial input of all test patterns is performed. In response to the low level of the chip scan enable signal CSEN, the module scan enable signal MMEM is also set to low level, and the selector MUX is switched from the scan side (SI) to the logic stage side (Din).

  In this state, the capture enable signal CPEN is set to the high level by the capture enable generation circuit, whereby two pulses of the high-speed clock corresponding to the system clock CLK are output. In synchronization with the pulse clk, a two-stage sequential circuit operates during the test. Thus, in the double clock mode, there is a sufficient timing margin between the high-speed system clock CLK and the module scan enable signal MSEN because it is only necessary to form the capture enable signal CPEN under the above conditions. . Also in this embodiment, the shift clock SCLK is formed using the reference clock RCLK as in FIG.

  In this embodiment, as described above, the internally generated clock control circuit releases the reset of the FF at the rising edge of the capture enable signal CPEN and outputs the internally generated clock clk for only two clocks of the system clock CLK. In the scan enable generation circuit, the module scan enable MSEN is controlled by the internally generated clock clk output from the internally generated clock control circuit, thereby enabling high-speed single clock operation. As a circuit configuration, both single clock and double clock pattern generation can be selected by the control signal S / W.

  A high-speed scan pattern generation with a small number of patterns is realized by performing an actual speed scan test mainly using a single clock method. The double clock method is also used as an auxiliary to detect delay faults that are difficult to detect with the single clock method described above, and the number of patterns is also suppressed. By using both methods, the fault detection rate of the delay fault test is improved. However, the number of patterns used for it is also suppressed. Since the actual speed test is performed using the LSI internally generated clock, the tester clock need not be high speed. For this reason, it is possible to test with an inexpensive tester and to suppress an increase in test cost.

  FIG. 8 shows a schematic overall configuration diagram of another embodiment of an LSI according to the present invention. The PLL circuit constituting the internal clock generation circuit of this embodiment forms two clocks having different frequencies such as a high-frequency clock CLK and a low-frequency clock NCLK obtained by dividing it by n. Therefore, an internally generated clock control circuit 1 is provided corresponding to the clock CLK, and an internally generated clock control circuit N is provided corresponding to the clock NCLK.

  The shift clock SCLK, the scan test mode signal SCTM, the reset signal RSET, and the chip scan enable signal CSEN as described above are supplied to the two internally generated clock control circuits 1 and N, and the capture enable generation circuit captures enable. A signal is supplied. Each of the above signals SCLK, SCTM, RSET and CSEN is formed by a test control circuit which decodes a test command inputted through a test interface circuit such as JTAG in addition to those supplied from the external terminals as shown in FIG. It may be done. The capture enable generation circuit can also be included in the test control circuit.

  The partial circuits A and B are circuit blocks similar to those described above. Although not particularly limited, the partial circuit A operates by the clocks clk and nclk corresponding to the two clocks CLK and NCLK, respectively, and the partial circuit B operates only by the clock nclk. In this case, the partial circuit A is provided with a scan enable generation circuit A1 corresponding to the clock clk and a scan enable generation circuit AN corresponding to the clock nclk. In the partial circuit B, a scan enable generation circuit BN is provided corresponding to the clock nclk.

  In the partial circuit A, the scan enable signal formed by the scan enable generation circuit A1 or AN is the same as each clock tree (not shown) in which the clocks clk and nclk in the partial circuit A are transmitted to the clock terminal of the FF in FIG. A scan enable signal is transmitted to the selector MUX of each FF by a scan enable tree of a simple signal transmission path. Also in the partial circuit B, the scan enable signal formed by the scan enable generation circuit BN has a signal transmission path similar to that of a clock tree (not shown) in which the clock nclk in the partial circuit B is transmitted to the clock terminal of the FF in FIG. A scan enable signal is transmitted to the selector MUX of each FF by the scan enable tree. Thus, by making the transmission path of the clock and the transmission path of the scan enable signal corresponding to the clock transmission path similar to each other, the propagation delay amount of the clock and the scan enable signal in the FF becomes equal and both due to the difference in delay amount. The timing difference between them can be minimized, and a scan test with a higher-speed clock can be performed with high reliability.

  FIG. 9 shows a schematic overall configuration diagram of another embodiment of an LSI according to the present invention. The PLL circuit constituting the internal clock generation circuit of this embodiment forms two clocks having different frequencies such as a high-frequency clock CLK and a low-frequency clock NCLK obtained by dividing it by n as in FIG. To do. Therefore, an internally generated clock control circuit 1 is provided corresponding to the clock CLK, and an internally generated clock control circuit N is provided corresponding to the clock NCLK.

  The shift clock SCLK, the scan test mode signal SCTM, the reset signal RSET, and the chip scan enable signal CSEN as described above are supplied to the two internally generated clock control circuits 1 and N, and the capture enable generation circuit captures enable. A signal is supplied. Although not particularly limited, the shift clock SCLK, the scan test mode signal SCTM, the reset signal RSET, and the chip scan enable signal CSEN are supplied from a test control circuit (not shown). The capture enable generation circuit can also be included in the test control circuit.

  The partial circuits A and B are circuit blocks similar to those described above. Although not particularly limited, the partial circuits A and B operate by clocks clk and nclk corresponding to the two clocks CLK and NCLK, respectively. In this case, for the partial circuits A and B, a scan enable generation circuit 1 corresponding to the clock clk and a scan enable generation circuit N corresponding to the clock nclk are provided in common. That is, the scan enable generation circuit 1 and the scan enable generation circuit N are not incorporated in the partial circuits A and B, but are adjacent to or in close proximity to both the partial circuits A and B. Similarly to the embodiment of FIG. 8, the transmission path of the scan enable signal from there to the FFs of the partial circuits A and B and the transmission paths of the clocks clk and nclk are arranged in correspondence with each other.

  Thus, by sharing the scan enable generation circuits 1 and N with the two partial circuits A and B, the circuit can be simplified. By making the transmission path of the clock and the scan enable signal similar, the timing difference due to the difference in the delay amount of the high-speed clock and the scan enable signal can be reduced by considering that the propagation delay amount of both is equal. It can be made small, and a highly reliable test result can be obtained.

  FIG. 10 is a schematic overall configuration diagram of still another embodiment of the LSI according to the present invention. This embodiment is a modification of the embodiment of FIG. 1, and the partial circuits A and B are each divided into two groups, and a scan enable generation circuit is provided corresponding to each of them. That is, in the partial circuit A, the scan enable generation circuits A1 and A2 are provided, and the combinational circuit and FF of the partial circuit A are divided into two, and the scan enable generation circuits A1 and A2 scan the corresponding FFs. An enable signal is transmitted. Correspondingly, the clock clk is also divided into two systems, and the propagation delay amount is combined with the scan enable signal. Similarly, in the partial circuit B, scan enable generation circuits B1 and B2 are provided, and the combinational circuit of the partial circuit B and the FF are divided into two, and the scan enable generation circuits B1 and B2 scan the corresponding FFs. An enable signal is transmitted. 9 and 10, the scan test mode signal SCTM and the reset signal RSET are omitted, but are supplied in the same manner as described above from an appropriate control circuit or terminal.

  FIG. 11 is a circuit diagram for explaining a test operation in a single clock system. In this single clock method, after the data is transferred to the FF in the shift mode, the scan enable is switched and the test is performed in the capture mode. In this method, the clock in the capture mode is one time, and when the failure assumption point to which the test pattern “1” is transmitted from the FF becomes “0” as shown in FIG. Changes from normal “1” to failure “0”. The failure assumption point “0” includes a case where the signal does not change to “1” during one cycle of the clock clk due to the signal propagation delay time of the test pattern “1”. As described above, since the inside of the LSI can be considered as a combinational circuit by the shift operation, the failure detection rate is likely to increase. However, in the actual speed scan test, it is necessary to operate the scan enable switching with high speed and high accuracy within one cycle of the clock clk.

  FIG. 12 is a circuit diagram for explaining the test operation in the double clock method. In this double clock method, the scan enable is set to the capture mode side before the first clock application, and then the test is performed by applying the clock twice. Since scan enable does not need to be switched in the test cycle, timing problems can be alleviated. However, in the double clock method, since the clock is applied twice in the capture mode, it is handled as a two-stage sequential circuit in the test. For this reason, there is a problem that the failure detection rate is less likely to increase and the test pattern becomes longer than in the single clock method. That is, the failure assumption point cannot be found directly.

  In the test method of this embodiment, when a delay fault is detected, there are faults that cannot be detected by a single clock and faults that cannot be detected by a double clock method, so that the fault detection rate is maximized by performing tests using both methods. At this time, a single clock is used as the main test to detect most failures with the above-mentioned few test patterns, and [take] both types of combined tests are performed to focus on failures that cannot be detected with a single clock and to detect failures with the double clock method. By switching between the single clock method and the double clock method during the test, it is possible to perform both types of tests, and create test patterns with a high detection rate and a small number of patterns.

  Although the invention made by the inventor has been specifically described based on the above embodiment, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. The specific configuration of the internal generation clock control circuit and the scan enable generation circuit may be anything as long as it performs the above operation. The present invention can be widely used as a semiconductor integrated circuit device such as a system LSI and a test method thereof.

1 is a schematic overall configuration diagram showing one embodiment of a semiconductor integrated circuit device according to the present invention. FIG. 2 is a block diagram of an example of a flip-flop circuit to be scan chained in FIG. 1. FIG. 2 is a configuration diagram illustrating an embodiment of an internally generated clock control circuit of FIG. 1. FIG. 2 is a configuration diagram illustrating an example of a scan enable generation circuit of FIG. 1. FIG. 5 is a waveform diagram for explaining the operation of the scan enable generation circuit of FIG. 4. It is a wave form diagram for demonstrating the test operation in a single clock mode. It is a wave form diagram for demonstrating the test operation in double clock mode. It is a schematic whole block diagram which shows another Example of LSI based on this invention. It is a schematic whole block diagram which shows another Example of LSI based on this invention. It is a schematic whole block diagram which shows another one Example of LSI based on this invention. It is a circuit diagram for demonstrating the test operation by a single clock system. It is a circuit diagram for demonstrating the test operation by a double clock system.

Explanation of symbols

MUX, selector, MFF, master flip-flop circuit, SFF, slave flip-flop circuit, G1 to G8, gate circuit, FF, FF1-FF4, flip-flop circuit, NV1-NV3, inverter circuit.

Claims (8)

A plurality of circuit blocks;
An internal clock generation circuit for forming a clock of the plurality of circuit blocks;
A scan test circuit for performing an operation test of the plurality of circuit blocks,
The scan test circuit
A first circuit that selectively transmits a scan clock supplied from the outside in response to a first control signal according to an instruction from the outside or a clock formed by the internal clock generation circuit;
A selector provided at the input portion of the flip-flop circuit constituting the scan chain of the circuit block is received from the scan chain side in response to a clock selectively provided by the first circuit provided in each circuit block. And a second circuit for forming an internal control signal to be switched to the preceding logic side. In claim 1,
The internal clock generation circuit is a PLL circuit,
The first circuit is disposed adjacent to the PLL circuit,
The semiconductor integrated circuit device, wherein the second circuit is incorporated in each circuit block. In claim 2,
The first circuit selects the scan clock according to one level of the first control signal, selects the clock according to the other level of the first control signal, and the first control signal is at one level. The pulse for the two cycles of the clock is selected by a predetermined timing signal in a state where the supply of the scan clock is stopped,
The second circuit forms the internal control signal such that the selector selects the preceding logic side in the first cycle of the clock and the selector selects the scan chain side in the second cycle. Semiconductor integrated circuit device. In claim 3,
The second circuit forms the internal control signal in synchronization with a two-cycle clock formed by the first circuit when the second control signal according to an instruction from the outside is at one level, and the second circuit Forming the internal control signal so that pulses corresponding to two cycles of the clock formed by the first circuit are transmitted to each circuit block in response to the second control signal when the control signal is at the other level; A semiconductor integrated circuit device. In claim 4,
The circuit block is divided into a first part and a second part,
The semiconductor integrated circuit device, wherein the second circuit includes a 2-1 circuit corresponding to the first part and a 2-2 circuit corresponding to the second part. In claim 4,
The PLL circuit generates a first clock and a second clock having a frequency different from the first clock,
The first part of the circuit block operates with the first clock, the second part operates with the second clock,
The 2-1 circuit forms a first internal control signal corresponding to the first clock,
The semiconductor integrated circuit device according to claim 2, wherein the 2-2 circuit forms a second internal control signal corresponding to the second clock. Logic circuit;
An internal clock generation circuit for forming a clock of the logic circuit;
A test method of a semiconductor integrated circuit device comprising a scan test circuit for performing an operation test of the logic circuit with both a single clock pattern and a double clock pattern,
A test method for a semiconductor integrated circuit device, wherein a test is supplementarily performed with the double clock pattern after the test with the single clock pattern. In claim 7,
The scan test circuit
A first circuit that selectively transmits a scan clock supplied from the outside in response to a first control signal according to an instruction from the outside or a clock formed by the internal clock generation circuit;
Each of the circuit blocks is provided with a selector provided at an input portion of a flip-flop circuit that constitutes a scan chain of the corresponding circuit block in response to the clock formed by the first circuit. A second circuit for forming an internal control signal for switching to the logic side,
The first circuit selects the scan external clock according to one level of the first control signal, selects the clock according to the other level of the first control signal, and the first control signal is set to one level. In the state where the supply of the external clock for scanning is stopped, a pulse corresponding to two cycles of the clock is selected by a predetermined timing signal,
The second circuit forms the internal control signal such that the selector selects the preceding logic side by the first cycle of the clock, and the selector selects the scan chain side by the second cycle,
When the second control signal according to an instruction from the outside is at one level, the internal control signal synchronized with the two-cycle clock formed by the first circuit is formed and the test with the single clock pattern is performed. ,
When the second control signal is at the other level, the internal control signal is set so that pulses corresponding to two cycles of the clock formed by the first circuit are transmitted to each circuit block corresponding to the second control signal. A test method for a semiconductor integrated circuit device, comprising: forming and testing with the double clock pattern.

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