JP2006319927A - AFC circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve signal processing accuracy without using an expensive oscillator with high frequency resolution.
An N frequency divider that divides a signal output from a VCO by a fraction is included, and a frequency conversion of a frequency according to a reference signal that is a given periodic signal and a divided value of the fractional frequency division is performed. A PLL 22 for outputting a signal for use to the VCO 32, a mixer 14 for converting the frequency of the received signal based on the frequency conversion signal outputted from the VCO 32, and outputting the converted frequency signal, and the quality of the outputted converted frequency signal A baseband unit 16 that obtains signal quality information and changes a frequency division value of the N frequency divider 26 according to the quality of the converted frequency signal indicated by the obtained signal quality information. AFC circuit 34.
[Selection] Figure 1

Description

  The present invention relates to an AFC circuit.

  In a conventional communication apparatus, a frequency error may occur in a received signal due to the Doppler effect or fading. For this reason, some communication devices use an AFC (Automatic Frequency Control) circuit for correcting this frequency error.

  FIG. 6 is an example of a communication device using an AFC circuit. As shown in the figure, a communication device 100 according to the background art of the present invention includes an antenna 110, an amplifier 112, a mixer 114, a baseband unit 116, a DAC (Digital to Analog Converter) 118, an LPF ( (LooP Filter, loop filter) 119, oscillator 120, PLL (Phase Locked Loop) 122, LPF 130, VCO (Voltage Controlled Oscillator, Voltage Controlled Oscillator) 132, and PLL 122 further includes R A frequency divider 124, an N frequency divider 126, and a phase comparator 128 are included. The mixer 114, the baseband unit 116, the DAC 118, the LPF 119, the oscillator 120, the PLL 122, the LPF 130, and the VCO 132 constitute an AFC circuit 134.

  A communication signal (radio frequency signal) received by the antenna 110 is amplified by the amplifier 112 and input to the mixer 114. The mixer 114 mixes the communication signal with the frequency conversion signal output from the VCO 132, thereby converting the frequency of the communication signal into a conversion frequency and outputs the converted frequency to the baseband unit 116. The baseband unit 116 performs predetermined signal processing on the input communication signal. Note that the baseband unit 116 and the PLL 122 operate using the reference signal that is the output of the oscillator 120 as a reference clock.

  The AFC circuit 134 is a circuit that allows the baseband unit 116 to appropriately process an input communication signal by appropriately changing the frequency of the frequency conversion signal. Hereinafter, processing of the AFC circuit 134 will be described.

  The baseband unit 116 determines whether the communication signal can be appropriately processed. When it is determined that the signal processing is not properly performed, the frequency of the reference signal oscillated by the oscillator 120 is adjusted via the DAC 118. The reference signal whose frequency is adjusted in this way is output from the VCO 132 as a frequency conversion signal whose frequency is multiplied by N / R. Since the mixer 114 mixes the communication signal with the frequency conversion signal output from the VCO 132 as described above, the frequency of the communication signal input to the baseband unit 116 is adjusted by doing so. It becomes.

  Further, since the frequency of the reference signal is adjusted, the reference clock for signal processing in the baseband unit 116 is also adjusted (for example, the sampling period is adjusted).

  If the baseband unit 116 cannot properly perform signal processing due to a frequency error in the input communication signal, the frequency of the communication signal input to the baseband unit 116 by the above processing, By adjusting the signal processing reference clock to an appropriate value, the baseband unit 116 can appropriately perform the signal processing. Therefore, the baseband unit 116 gradually changes the frequency of the reference signal and determines the frequency and base of the communication signal input to the baseband unit 116 until it determines that the input communication signal has been appropriately processed. The reference clock for signal processing in the band unit 116 is adjusted. In this way, the AFC circuit 134 allows the baseband unit 116 to appropriately process the communication signal.

Patent Document 1 describes an invention relating to adjusting an oscillation frequency of an oscillator so that a digital value of a received signal is appropriate.
JP-A-10-75160

  However, in the above conventional technique, in order to increase the signal processing accuracy of the converted frequency signal in the baseband part, an expensive oscillator with high frequency resolution must be used in order to increase the resolution of the adjustment of the frequency of the reference signal. Therefore, a method that can increase the signal processing accuracy at a lower cost has been demanded.

  The present invention has been made in view of the above problems, and one of its purposes is to provide an AFC circuit that can improve signal processing accuracy without using an expensive oscillator with high frequency resolution. is there.

  In order to solve the above problems, an AFC circuit according to the present invention includes a frequency divider that divides a signal output from a VCO, a reference signal that is a given periodic signal, and a divided value of the fractional frequency division. A frequency including a PLL that includes a VCO control unit that outputs a frequency conversion signal having a frequency corresponding to the VCO, and a frequency at which the received signal is converted based on the frequency conversion signal output from the VCO, and a converted frequency signal is output. Conversion means, signal quality information acquisition means for acquiring signal quality information indicating the quality of the output converted frequency signal, and the frequency division according to the quality of the conversion frequency signal indicated by the acquired signal quality information Frequency division value changing means for changing the frequency division value of the device.

  According to the present invention, the frequency of the frequency conversion signal can be changed by changing the division value of the frequency divider that performs fractional frequency division, and the conversion frequency signal can be used without using an expensive oscillator with high frequency resolution. Signal processing accuracy can be increased.

  Further, in the AFC circuit, the frequency division value changing means may calculate the frequency division value of the frequency divider when the acquired signal quality information indicates that the quality of the converted frequency signal is worse than a predetermined value. It may be changed.

  In the AFC circuit, the dividing value changing unit may change the dividing value of the divider until the acquired signal quality information indicates that the quality of the converted frequency signal is better than a predetermined value. May be repeated.

  By doing so, the frequency of the frequency conversion signal can be finely adjusted by changing the frequency division value of the frequency divider, and the signal processing accuracy of the converted frequency signal can be further improved. Become.

  The AFC circuit further includes frequency control means for controlling the frequency of the reference signal, and determination means for determining to perform frequency control with a resolution higher than the frequency resolution of the reference signal. , When it is determined that the frequency control is performed with a resolution higher than the frequency resolution of the reference signal, the frequency dividing value changing unit is configured to change the frequency according to the quality of the converted frequency signal indicated by the acquired signal quality information. The frequency division value of the frequency divider may be changed.

  In this way, the frequency of the frequency conversion signal is roughly adjusted by adjusting the frequency of the reference signal, and then the frequency of the frequency conversion signal is changed by changing the frequency division value of the frequency divider. Fine adjustments can be made.

  Furthermore, in the AFC circuit, the PLL may be a ΣΔ modulation type PLL.

  Since the ΣΔ modulation type PLL can increase the denominator of the fractional division compared to other types of PLLs, the frequency conversion signal frequency can be made finer by setting the denominator of the fractional division as large as possible. Thus, the signal processing accuracy of the converted frequency signal can be further increased.

  Embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a system configuration diagram of a communication apparatus 1 according to the present embodiment. As shown in the figure, the communication apparatus 1 includes an antenna 10, an amplifier 12, a mixer 14, a baseband unit 16, an oscillator 20, a PLL (Phase Locked Loop) 22, an LPF 30, a VCO (Voltage Controlled Oscillator, The PLL 22 includes a R divider 24, an N divider 26, an N modulator 27, and a phase comparator 28. Further, the PLL 22 includes a fractional-N PLL. It is. The mixer 14, the baseband unit 16, the oscillator 20, the PLL 22, the LPF 30, and the VCO 32 constitute an AFC (Automatic Frequency Control) circuit 34.

  In the present embodiment, the baseband unit 16 performs signal processing of a communication signal received by the antenna 10 and acquires the reception quality. Then, the N modulation unit 27 is controlled based on the acquired reception quality, and the frequency division value of the N frequency divider 26 is changed, thereby fixing the frequency division value of the N frequency divider 26 with a good value of reception quality. Like to do. Hereinafter, the configuration and processing for this will be described in detail.

  First, the communication device 1 receives a communication signal with the antenna 10. Then, the communication device 1 amplifies the received communication signal with the amplifier 12 and inputs it to the mixer 14.

  The oscillator 20 outputs a reference signal that is a periodic signal having a given frequency. The PLL 22 divides the reference signal output from the oscillator 20 by the R divider 24. Then, the divided reference signal is input to the phase comparator 28. The phase comparator 28 compares the phase of the frequency-divided reference signal input from the R frequency divider 24 and a signal (described later) input from the N frequency divider 26, and a voltage signal corresponding to the result. Is output to the LPF 30. The LPF 30 removes the noise component of the voltage signal output from the phase comparator 28 and outputs it to the VCO 32. The VCO 32 outputs a signal (frequency conversion signal) having a frequency corresponding to the voltage signal input from the LPF 30 and inputs the signal to the mixer 14 and the N frequency divider 26. That is, the PLL 22 controls the VCO 32 to output a frequency conversion signal having a frequency corresponding to the reference signal and the frequency division values of the R frequency divider 24 and the N frequency divider 26.

  The mixer 14 performs frequency conversion of the input communication signal based on the frequency conversion signal input from the VCO 32. More specifically, the mixer 14 converts the frequency of the communication signal by mixing the input communication signal and the frequency conversion signal input from the VCO 32. Then, the communication signal after frequency conversion is output to the baseband unit 16.

  The N divider 26 divides the frequency conversion signal input from the VCO 32 by a fraction and outputs it to the phase comparator 28. Thus, the PLL 22 that performs fractional frequency division in the N frequency divider 26 is called a fractional-N type PLL. The frequency division value of the N frequency divider 26 is a frequency division value according to the control signal from the baseband unit 16. The phase comparator 28 performs phase comparison between the frequency conversion signal input from the N frequency divider 26 and the frequency-divided reference signal input from the R frequency divider 24. In this way, the PLL 22 functions as a frequency control circuit including a frequency conversion signal feedback circuit. As compared with the case where no feedback circuit is included, the frequency control of the frequency conversion signal can be performed more precisely.

The N modulation unit 27 ΣΔ modulates the frequency division value of the N frequency divider 26 (that is, generates a random number and changes the frequency division value according to the random number). In the fractional-N type PLL, since fractional frequency division is performed, spurious called fractional spurious is generated. This fractional spurious is collected in the vicinity of the frequency of the reference signal after being frequency-divided by the R frequency divider 24 as the N modulation unit 27 ΣΔ modulates the frequency division value of the N frequency divider 26.

  The baseband unit 16 acquires signal quality information indicating the reception quality of the communication signal after frequency conversion input from the mixer 14. As the signal quality information, it is preferable to use an error rate after the communication signal is converted into a digital signal. In addition, for example, the carrier / noise ratio may be used as the signal quality information.

  The baseband unit 16 compares the acquired signal quality information with a predetermined threshold value, and controls the oscillator 20 and the N divider 26 so that the signal quality information exceeds the predetermined threshold value.

  First, control of the oscillator 20 based on the signal quality information will be described. The oscillator 20 outputs a reference signal having a given frequency as described above. The baseband unit 16 controls the frequency of this reference signal according to the signal quality information. Specifically, based on the signal quality information, the frequency of the reference signal is changed so that the signal quality information exceeds a predetermined threshold.

  When the frequency of the reference signal input to the PLL 22 is changed in this way, the frequency of the signal input to the phase comparator 28 is also changed. Further, the frequency of the frequency conversion signal output from the VCO 32 to the mixer 14 is also changed. For this reason, the frequency of the communication signal output from the mixer 14 is also changed.

  On the other hand, the frequency of the reference signal output from the oscillator 20 is used as a reference clock for determining the sampling period in sampling when the communication signal in the baseband unit 16 is converted into a digital signal.

  That is, the baseband unit 16 adjusts the frequency of the communication signal output from the mixer 14 and the sampling period in the baseband unit 16 by controlling the frequency of the reference signal output from the oscillator 20. It becomes. For this reason, the baseband unit 16 can control the reception quality of the communication signal by controlling the frequency of the reference signal output from the oscillator 20.

  Next, control of the N frequency divider 26 based on the signal quality information will be described. The baseband unit 16 generates a control signal for changing the frequency division value of the N frequency divider 26 according to the signal quality information, and outputs the control signal to the N frequency divider 26. Specifically, when the signal quality information is worse than a predetermined threshold, the baseband unit 16 sets the frequency division value of the N divider 26 so that the signal quality information exceeds the predetermined threshold according to the signal quality information. change.

  When the frequency division value of the N frequency divider 26 is changed in this way, the frequency of the signal input to the phase comparator 28 is changed. Further, the frequency of the frequency conversion signal output from the VCO 32 to the mixer 14 is also changed. For this reason, the frequency of the communication signal output from the mixer 14 is also changed.

  That is, the baseband unit 16 adjusts the frequency of the communication signal output from the mixer 14 by controlling to change the frequency division value of the N frequency divider 26. The baseband unit 16 repeats this control while changing the frequency division value of the N frequency divider 26 until the signal quality information exceeds a predetermined threshold value. In this way, the baseband unit 16 controls the reception quality of the communication signal under the control of the N modulation unit 27.

  As described above, the baseband unit 16 controls the oscillator 20 and the N divider 26 to improve the reception quality of the communication signal. The baseband unit 16 roughly determines the frequency and sampling period of the communication signal by controlling the oscillator 20, and determines the frequency of the communication signal more precisely by controlling the N divider 26. Is preferred.

  Hereinafter, the processing (communication signal frequency correction processing) performed by the baseband unit 16 will be described in more detail with reference to a processing flowchart.

  First, the baseband unit 16 acquires the error rate of the communication signal (S100). Here, the error rate indicates that the smaller the value, the better the reception quality.

  The baseband unit 16 determines whether or not the error rate is smaller than the stored threshold value Err (S101). That is, it is determined whether or not the reception quality indicated by the error rate is better than the reception quality indicated by the stored threshold value Err. When it is determined that the error rate is smaller than the threshold value Err, the baseband unit 16 ends the process. On the other hand, when it is determined that the error rate is equal to or higher than the threshold value Err, the polarity (polarity) of the frequency of the communication signal is acquired and substituted into the variable PA (S102). The polarity of the frequency is information for identifying whether the frequency of the communication signal is higher or lower than the frequency that should be received. When the polarity PA indicates that the frequency of the communication signal is higher than the frequency to be originally received, changing the frequency in the direction of lowering the frequency of the communication signal improves the reception quality of the communication signal. The frequency changes in the direction. On the other hand, if the polarity PA indicates that the frequency of the communication signal is lower than the frequency to be originally received, changing the frequency in the direction of increasing the frequency of the communication signal may result in the reception quality of the communication signal. The frequency will change in the direction of improvement.

  The oscillator 20 (here, VCTCXO (voltage control / temperature compensation crystal oscillator)) changes the frequency of the reference signal to be output in accordance with the value of the stored control bit. This control bit is composed of an ascending control bit and a descending control bit. When 1 is set in the ascending control bit, the oscillator 20 performs one step when the frequency of the reference signal is determined in advance. At the same time, the value of the ascending control bit is returned to zero. Similarly, when 1 is set in the lowering control bit, the oscillator 20 lowers the frequency of the reference signal by one step at a predetermined stage and returns the value of the lowering control bit to 0.

  Therefore, the baseband unit 16 performs a process of setting 1 to one of the control bits of the oscillator 20 so that the frequency is changed in the improvement direction according to the polarity PA (S103). Then, the error rate of the communication signal is acquired again, and it is determined whether or not the error rate is smaller than the stored threshold value Err (S104). When it is determined that the error rate is smaller than the threshold value Err, the baseband unit 16 ends the process. On the other hand, when it is determined that the error rate is equal to or higher than the threshold value Err, the polarity (polarity) of the frequency of the communication signal is acquired again and substituted into the variable PB (S105). If the variable PA and the variable PB are equal, that is, if the polarity has not changed, the variable PB is substituted for the variable PA, and the process returns to S103 to set 1 to one of the control bits of the oscillator 20 again. I do.

  If the variable PA and the variable PB are not equal, that is, if the polarity has changed, the baseband unit 16 determines that the limit of the communication signal frequency correction control by the control of the oscillator 20 has been exceeded, and the N divider 26 Processing is shifted to communication signal frequency correction control by control.

  Similarly to the oscillator 20, the N divider 26 also changes the divided value according to the stored value of the control bit. This control bit is composed of an ascending control bit and a descending control bit. When 1 is set in the ascending control bit, the N divider 26 divides the divided value at a predetermined stage. Is raised by one step and the value of the ascending control bit is returned to zero. Similarly, when 1 is set in the lowering control bit, the N modulation unit 27 lowers the frequency division value by one step at a predetermined stage and returns the value of the lowering control bit to 0.

  Therefore, the baseband unit 16 performs a process of setting 1 to one of the control bits of the N frequency divider 26 so that the frequency is changed in the improvement direction according to the polarity PB (S107). A control signal is output to the N frequency divider 26. Then, the error rate of the communication signal is acquired again, and it is determined whether or not the error rate is smaller than the stored threshold value Err (S108). When it is determined that the error rate is smaller than the threshold value Err, the baseband unit 16 ends the process. On the other hand, when it is determined that the error rate is equal to or higher than the threshold value Err, the process returns to S107, and processing for setting 1 to one of the control bits of the N modulation unit 27 is performed again. This process is repeated until it is determined in S108 that the error rate is smaller than the threshold value Err. Of course, it is desirable to include a timeout process so as not to cause an infinite loop.

  As described above, the baseband unit 16 performs communication signal frequency correction processing using the AFC circuit 34 so as to obtain better reception quality.

  As described above, the frequency of the frequency conversion signal can be adjusted by changing the frequency division value of the N frequency divider 26 that performs fractional frequency division, and an expensive oscillator with high frequency resolution is used as the oscillator 20. Therefore, it is possible to improve the signal processing accuracy of the converted frequency signal.

  The frequency conversion signal is roughly adjusted by adjusting the frequency of the reference signal output from the oscillator 20, and the frequency conversion signal is changed by changing the frequency division value of the N frequency divider 26 that performs fractional frequency division. The frequency can be finely adjusted.

  Further, if a ΣΔ modulation type PLL is used as the PLL 22, the denominator of the fractional frequency division can be made larger than that of other types of PLLs. Therefore, by setting the denominator of the fractional frequency division as large as possible, The frequency of the frequency conversion signal can be finely adjusted, and the signal processing accuracy of the converted frequency signal can be further increased.

  In addition, this invention is not limited to the said embodiment, There are various modifications in the said embodiment. Hereinafter, some of such modifications will be described.

  FIG. 3 is a flowchart of processing of the communication apparatus according to the first modification. In the first modification, the process (S103 to S106) for controlling the frequency of the reference signal of the oscillator 20 is omitted from the process described with reference to FIG. In a communication apparatus used in an environment where the frequency error is not so large, sufficient frequency correction control can be realized even if the processing for controlling the frequency of the reference signal of the oscillator 20 is omitted.

  FIG. 4 is a flowchart of processing of the communication apparatus according to the second modification. In the above embodiment, the process of controlling the frequency of the reference signal of the oscillator 20 based on the error rate and the process of controlling the frequency division value of the N frequency divider 26 are performed. The band unit 16 acquires the frequency error itself.

  As shown in FIG. 4, in the second modification, first, the baseband unit 16 acquires a frequency error and substitutes it for a variable @ (S201). Then, it is determined whether or not the value of the variable @ is smaller than the stored threshold value fpll (S202). If the value of the variable @ is smaller than the threshold value fpll, the baseband unit 16 ends the process. On the other hand, if it is determined that the value of the variable @ is greater than or equal to the stored threshold value fpll, it is further determined whether or not the value of the variable @ is greater than the stored threshold value ftcxo (S203). When the value of the variable @ is larger than the threshold value ftcxo, the baseband unit 16 performs the process of correcting the frequency of the communication signal by the process of controlling the frequency of the reference signal of the oscillator 20 (S205). This process is repeated until the value of the variable @ is equal to or less than the threshold value ftcxo.

  When the value of the variable @ is equal to or less than the threshold value ftcxo, the baseband unit 16 performs a frequency correction process for the communication signal by a process for controlling the frequency division value of the N frequency divider 26 (S204).

  In the second modification, the frequency correction control of the communication signal is efficiently performed by changing the processing step by step in this way.

  FIG. 5 is a flowchart of processing of the communication apparatus according to the third modification. In the third modification, the process (S203 and S205) for controlling the frequency of the reference signal of the oscillator 20 is omitted from the process described with reference to FIG. In a communication apparatus used in an environment where the frequency error is not so large, sufficient frequency correction control can be realized even if the processing for controlling the frequency of the reference signal of the oscillator 20 is omitted.

  In the above embodiments and modifications, the description has been made on the assumption that the present invention is applied to a communication apparatus. However, the present invention can be applied to any apparatus using an AFC circuit. It is.

1 is a system configuration diagram of a communication apparatus according to an embodiment of the present invention. It is a flowchart of the process which concerns on embodiment of this invention. It is a flowchart of the process which concerns on embodiment of this invention. It is a flowchart of the process which concerns on embodiment of this invention. It is a flowchart of the process which concerns on embodiment of this invention. It is a system block diagram of the communication apparatus which concerns on the background art of this invention.

Explanation of symbols

  1,100 communication device 10,110 antenna, 12,112 amplifier, 14,114 mixer, 16,116 baseband unit, 20,120 oscillator, 22 PLL, 24,124 N divider, 26,126 R divider 27, N modulator, 28, 128 phase comparator, 30, 119, 130 LPF, 32, 132 VCO, 34, 134 AFC circuit, 118 DAC.

Claims (5)

A frequency divider that divides the signal output from the VCO by a fraction, and a VCO that causes the VCO to output a frequency conversion signal having a frequency corresponding to a reference signal that is a given periodic signal and the divided value of the fractional frequency division Control means,
A PLL including:
Frequency conversion means for frequency-converting a received signal based on a frequency conversion signal output from the VCO and outputting a converted frequency signal;
Signal quality information acquisition means for acquiring signal quality information indicating the quality of the output converted frequency signal;
According to the quality of the converted frequency signal indicated by the acquired signal quality information, a frequency division value changing means for changing the frequency division value of the frequency divider,
AFC circuit characterized by including. The AFC circuit according to claim 1,
The frequency dividing value changing means changes the frequency dividing value of the frequency divider when the acquired signal quality information indicates that the quality of the converted frequency signal is worse than a predetermined value.
An AFC circuit characterized by that. The AFC circuit according to claim 2,
The frequency dividing value changing means repeats changing the frequency dividing value of the frequency divider until the acquired signal quality information indicates that the quality of the converted frequency signal is better than a predetermined value.
An AFC circuit characterized by that. In the AFC circuit according to any one of claims 1 to 3,
Frequency control means for controlling the frequency of the reference signal;
Determining means for determining to perform frequency control at a resolution exceeding the frequency resolution of the reference signal;
Further including
When it is determined by the determining means that the frequency control is performed with a resolution higher than the frequency resolution of the reference signal, the frequency dividing value changing means adjusts the quality of the converted frequency signal indicated by the acquired signal quality information. In response, the dividing value of the divider is changed.
An AFC circuit characterized by that. The AFC circuit according to any one of claims 1 to 4,
The PLL is a ΣΔ modulation type PLL,
An AFC circuit characterized by that.

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