JP2006319640A - Solid-state imaging device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state imaging device that realizes high-quality monitor display by suppressing charge transfer failure in a monitor mode without degrading a frame rate.
SOLUTION: A plurality of two-dimensionally arranged photoelectric conversion elements, a vertical transfer unit that reads out signal charges from the photoelectric conversion elements and transfers them in the vertical direction, and receives signal charges from the vertical transfer units and transfers them in the horizontal direction. A monitor mode for reading out signal charges by thinning out the photoelectric conversion elements in the vertical direction and transferring the read signal charges in a plurality of stages from the vertical transfer unit to the horizontal transfer unit in a horizontal blanking period, The present invention relates to a solid-state imaging device having an operation mode. In the monitor mode, the time interval from the time when the first stage signal charge transfer is completed by the vertical transfer unit (T2) to the time when the next stage signal charge transfer is started (T3) is set as one step of the vertical transfer. The time is longer than the required time (Vstep).
[Selection] Figure 1

Description

  The present invention relates to a solid-state imaging device, and more particularly to a solid-state imaging device having a monitor mode as an operation mode.

  In recent years, imaging devices such as home video cameras and digital still cameras have become popular. Some of these imaging devices use a solid-state imaging device that reads out charges from photoelectric conversion elements arranged in a matrix, and sequentially transfers and outputs them using a plurality of vertical CCDs and one or more horizontal CCDs.

  As operation modes of the conventional solid-state imaging device, there are a still mode for outputting a still image and a monitor mode for outputting a moving image or a monitor image. In the still mode, in order to output a high-resolution still image, the charges of all the photoelectric conversion elements are read to the vertical CCD and transferred and output. However, according to the driving method for transferring and outputting the charges of all the photoelectric conversion elements as described above, the frame rate is lowered, so that the same driving method as the still mode cannot be applied to the monitor mode. Therefore, in the monitor mode, the frame rate is improved by thinning out photoelectric conversion elements from which charges are read out in the vertical direction.

  FIG. 7 is a schematic diagram illustrating an operation example of a monitor mode in a conventional solid-state imaging device. The conventional solid-state imaging device shown in FIG. 7 is a 6-phase CCD having 6-phase transfer electrodes (V1 to V6) per stage. In addition, this solid-state imaging device includes a so-called Bayer array color filter on the photoelectric conversion element, and reads out charges from one pixel in one stage (three pixels in the vertical direction). The solid-state imaging device shown in FIG. 7 is configured to read out charges of two pixels of the same color among six pixels in the vertical direction and then mix the charges in the horizontal CCD, and charge the two stages of charges in one horizontal blanking period. It works to send in. In FIG. 7, pixels in which the color name (R, G, B) of the color filter is circled are pixels from which charges are read out at each stage. In the configuration shown in FIG. 7, as shown in FIG. 8, charges are transferred in the vertical direction while signal charges are accumulated in four to five transfer electrodes. FIG. 7 shows a state after the charges read to the vertical CCD are appropriately transferred in the vertical direction, and the arrows in FIG. 7 indicate which transfer the charges read from each pixel are in the vertical CCD. Indicates whether it is accumulated on the electrode.

  FIG. 8 is a waveform diagram showing drive signals applied to the transfer electrodes V1 to V6 of the vertical CCD during the horizontal blanking period in the conventional solid-state imaging device. As shown in FIG. 8, in the conventional solid-state imaging device, charges of two stages are sent to the horizontal CCD in the horizontal blanking period, but the first-stage transfer and the second-stage transfer are not spaced from each other. It is done continuously. That is, the transfer of the second stage is started immediately after the transfer of the first stage is completed (time t2).

An example of a solid-state imaging device that sends two or more stages of charges to the horizontal CCD in one horizontal blanking period in the monitor mode is also disclosed in, for example, Patent Document 1. In the solid-state imaging device disclosed in Patent Document 1, the length of the horizontal blanking period in the line thinning mode is made longer than that in the field readout mode that requires high resolution, thereby overlapping the vertical transfer clocks. To improve the transfer efficiency.
JP 2002-152598 A (page 6, paragraph 0049)

  However, in the conventional solid-state imaging device driven as shown in FIG. 8, in the monitor mode, a local charge transfer failure occurs in the vertical CCD, and a colored vertical line is generated when imaging monochromatic light. The phenomenon was seen. This is because, as shown in FIG. 9, “color mixing” in which signal charges in a plurality of stages are mixed due to charge transfer failure in the vertical CCD, and the color ratio shows an abnormal value in a specific line. . The graph of FIG. 9 is a result of obtaining a color ratio (R / G) in the picked-up signal by irradiating the solid-state image pickup device with green light and picking it up.

  This phenomenon is improved to some extent by increasing the overlap period of the vertical transfer clocks, as in the method disclosed in Patent Document 1. However, the method disclosed in Patent Document 1 causes another problem that the horizontal synchronization period becomes long and the frame rate deteriorates.

  In view of the above problems, an object of the present invention is to provide a solid-state imaging device that realizes high-quality monitor display by suppressing charge transfer defects in the monitor mode without degrading the frame rate. .

  In order to achieve the above object, a solid-state imaging device according to the present invention includes a photoelectric conversion element arranged in a matrix and storing photoelectrically converted signal charges, and a signal charge stored from the photoelectric conversion elements. A solid-state imaging device comprising: a vertical transfer unit that transfers in a direction; and a horizontal transfer unit that receives a signal charge from the vertical transfer unit and transfers the signal charge in a horizontal direction. A monitor mode for transferring a plurality of stages of readout and readout signal charges from the vertical transfer unit to the horizontal transfer unit in a horizontal blanking period is provided as an operation mode. In the monitor mode, a single-stage signal is transmitted by the vertical transfer unit. After the charge transfer is completed, the vertical charge clock signal is transferred so that the time from the start of the next stage signal charge transfer becomes longer than the period of the vertical transfer clock. Characterized by comprising a driving unit for supplying a driving signal to the feed unit.

  According to the above configuration, in the monitor mode, the time required for starting one stage of signal charge transfer after the completion of one stage of signal charge transfer during vertical transfer is the time required for one step of vertical transfer. By supplying a drive signal to the vertical transfer unit so as to be longer than the period, the potential fluctuation of the p-well arranged under the vertical transfer unit is suppressed. As a result, it is possible to effectively prevent a signal charge transfer failure without degrading the frame rate, as compared with the method of extending the horizontal blanking period as disclosed in Patent Document 1 above. Become. As a result, it is possible to provide a solid-state imaging device that realizes high-quality monitor display.

  In the above configuration, the time from the completion of one stage of signal charge transfer by the vertical transfer unit to the start of the next stage of signal charge transfer is more than three times the time required for one step of vertical transfer. Preferably there is.

  The drive signal supplied to the vertical transfer unit during the period from the completion of one-stage signal charge transfer by the vertical transfer unit to the start of the next-stage signal charge transfer is the vertical transfer unit during the horizontal transfer period. Preferably, the drive signal is the same as the drive signal supplied to. This is because the potential fluctuation of the p-well arranged under the vertical transfer portion can be more effectively suppressed.

  ADVANTAGE OF THE INVENTION According to this invention, the solid-state imaging device which implement | achieves a high-quality monitor display can be provided by suppressing the charge transfer defect at the time of monitor mode, without degrading a frame rate.

  Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a block diagram illustrating a schematic configuration example of the solid-state imaging device of the present embodiment. In FIG. 2, the output of the solid-state imaging device 1 is subjected to CDS (correlated double sampling) and ADC (analog / digital conversion) processing by a preprocessing circuit 20. The output of the preprocessing circuit 20 is subjected to pixel interpolation, luminance / color difference processing, and the like by a digital signal processing (DSP) circuit 30 and is output as a video signal. The timing generator (TG) 40 generates timing pulses P _H1 , P _H2 , and P _{V1 to} P _V6 that are used for driving the solid-state imaging device 1. The clock driver 50 (drive unit) generates drive signals φV1 to φV6 based on the timing pulse generated by the timing generator 40 and supplies the drive signals φV1 to φV6 to the solid-state imaging device 1.

  The timing generator 40 receives the pulses of the horizontal synchronizing signal HD, the vertical synchronizing signal VD, and the clock signal from the digital signal processing circuit 30, generates the timing pulse, and generates the signal processing pulse PROC from the preprocessing circuit 20 and the digital signal. The signal is supplied to the signal processing circuit 30. However, the timing generator 40 may be configured to generate the horizontal synchronization signal and the vertical synchronization signal.

  FIG. 3 shows a schematic configuration of the solid-state imaging device 1 according to the present embodiment. The solid-state imaging device 1 of the present embodiment includes photoelectric conversion elements 2 arranged in a matrix, a vertical transfer unit 3, a horizontal transfer unit 4, and a charge detection unit 5. Each of the vertical transfer unit 3 and the horizontal transfer unit 4 is configured by a CCD (Charge Coupled Device). In the example shown in FIG. 3, the vertical transfer unit 3 has six-phase transfer electrodes V1 to V6, and the horizontal transfer unit 4 has two-phase transfer electrodes H1 and H2. It is not limited only to the configuration. In FIG. 3, only the vertical transfer unit 3 in the imaging region (the region where the photoelectric conversion element 2 is provided) is illustrated, but an accumulation region is provided between the vertical transfer unit 3 and the horizontal transfer unit 4. It is good also as a structure.

  For example, a photodiode is used as the photoelectric conversion element 2. In each of the photoelectric conversion elements 2, three color filters of red (R), green (G), and blue (B) are regularly arranged as shown in FIG. 3. In the present embodiment, the RGB filters constitute a so-called Bayer array every two pixels in the vertical and horizontal directions. That is, as shown in FIG. 3, if a total of 4 pixels of 2 vertical pixels × 2 horizontal pixels is used as a unit, the lower left pixel is R, the lower right pixel and the upper left pixel are G, and the upper right pixel is B. As shown, color filters are arranged.

  In the solid-state imaging device 1, two transfer electrodes of the vertical transfer unit 3 are connected to each of the photoelectric conversion devices 2. One of the two transfer electrodes connected to each photoelectric conversion element 2 is a shift gate for reading the signal charge accumulated in the photodiode. For example, in FIG. 3, it is assumed that among the six transfer electrodes V1 to V6, the odd-numbered transfer electrode is a shift gate. In FIG. 3, transfer electrodes of the same type are wired so as to be electrically connected in common, and are driven independently of other transfer electrodes. For example, the transfer electrodes labeled V1 are all wired in common, and are driven independently of the transfer electrodes V2 to V6. However, in order to thin out pixels in the vertical direction in the monitor mode, V3A and V3B and V5A and V5B are wired separately from each other and are driven independently of each other. That is, in the monitor mode, by applying a read voltage to V3A and V5A, signal charges are read only from the photodiodes to which V3A and V5A are connected. In FIG. 3, the photoelectric conversion element 2 from which signal charges are read out in the monitor mode is hatched.

  Accordingly, for example, as shown in the lower left of FIG. 3, in the monitor mode, in the transfer electrode group 31a composed of the six-phase transfer electrodes V1 to V6, a signal is output from the R photoelectric conversion element 2 to which V5A is connected. The charge is read out. Similarly, in the transfer electrode group 31b composed of six-phase transfer electrodes V1 to V6, signal charges are read from the R photoelectric conversion element 2 to which V3A is connected. Then, within one horizontal blanking period, the signal charge for one pixel (R signal charge) read by the transfer electrode group 31a is transferred as the first stage, and one pixel read by the transfer electrode group 31b. Minute signal charge (R signal charge) is transferred as the second stage. The two-stage signal charges of the same color are mixed by the horizontal transfer unit 4. Similarly, the two-stage signal charges read in the transfer electrode group 31 shown in FIG.

FIG. 1 is a waveform diagram showing drive signals (φV1 to φV6) applied to the transfer electrodes V1 to V6 in the horizontal blanking period in the solid-state imaging device 1 according to the present embodiment. As shown in FIG. 1, in the solid-state imaging device 1 according to the present embodiment, a middle level voltage (V _M ) is applied to the transfer electrodes V1, V2, V3, and V4 during the horizontal transfer period, and the transfer electrodes V5 and V6 are transferred. Although the low level voltage (V _L ) is applied to the vertical voltage, the vertical transfer is performed by the voltage applied to the transfer electrode V5 rising to the middle level (V _M ) at time T1 after the horizontal blanking period starts. Is started. The middle level voltage (V _M ) is lower than the high level voltage (V _H ) applied to the transfer electrodes V3A and V5A when the signal charge is read from the photoelectric conversion element 2.

Immediately after time T1, the middle level voltage (V _M ) is applied to the transfer electrodes V1, V2, V3, V4, and V5, and the low level voltage (V _L ) is applied to the transfer electrode V6. Signal charges are accumulated on the five electrodes V1, V2, V3, V4 and V5. Then, the voltage applied to the transfer electrode V1 is switched from the middle level (V _M ) to the low level (V _L ) by the next vertical transfer clock at time T1. As a result, signal charges are accumulated on the four transfer electrodes V2, V3, V4, and V5. Further, the voltage applied to the transfer electrode V6 is switched from the low level (V _L ) to the middle level (V _M ) by the next vertical transfer clock. As a result, signal charges are accumulated on the five transfer electrodes V2, V3, V4, V5, and V6.

  As described above, the signal charges accumulated in the four to five transfer electrodes are transferred in the vertical direction for each vertical transfer clock. Then, the signal charge of the first stage is sent to the horizontal transfer unit 4 at time T2 shown in FIG.

When the transfer of the first stage signal charge is completed at time T2, the solid-state imaging device 1 stops the vertical transfer until time T3. In the example of FIG. 1, the time from time T2 to T3 corresponds to three times the time required for one step of vertical transfer (Vstep shown in FIG. 1). Note that the voltage applied to each transfer electrode of the vertical transfer unit 3 from time T2 to T3 is the middle level (V _M ) with respect to the transfer electrodes V1, V2, V3, and V4 as in the horizontal transfer period. The transfer electrodes V5 and V6 are at a low level (V _L ). At time T3, as in time T1, the voltage applied to the transfer electrode V5 rises to the middle level (V _M ), whereby vertical transfer of the second stage signal charge is started. Thereafter, similarly to the first-stage transfer, the signal charges accumulated in the four to five transfer electrodes are sequentially transferred in the vertical direction, so that the second-stage signal charges are transferred to the horizontal transfer section 4 at time T4. It is sent to.

  As described above, in the solid-state imaging device 1 according to the present embodiment, when a plurality of stages of charge transfer are performed in the horizontal blanking period, after one stage of charge transfer is completed, the next stage of charge transfer is started. Is secured longer than the time required for one step of vertical transfer (Vstep). This prevents the occurrence of local transfer failures. As a result, as shown in FIG. 4, a high-quality monitor image can be obtained in which the color ratio is constant and no vertical lines are generated.

  As described above, the reason why the local transfer failure can be suppressed in the solid-state imaging device 1 according to the present embodiment is as follows.

  FIG. 5 is a cross-sectional view taken along the transfer direction of the vertical transfer unit 3. As shown in FIG. 5, in the vertical transfer unit 3, a p-well 12 and an n-type buried channel 13 are formed on an n-type semiconductor substrate 11, and transfer electrodes V1 to V6 are provided on the surface thereof. It is a configuration. Although the p-well 12 is GND-connected, it is easily affected by pulses applied to the transfer electrodes V1 to V6 because it is connected to the GND wiring around the pixel region and has high resistance. For this reason, in the case where a plurality of stages of vertical transfer are continuously performed during the horizontal blanking period, if the second stage transfer is performed immediately after the completion of the first stage transfer as in the prior art, as shown in FIG. Thus, it is considered that the potential of the p-well 12 fluctuates due to the pulse applied to the transfer electrodes V1 to V6, and the amplitude of the fluctuation gradually increases. When the potential of the p-well 12 fluctuates in this way, part of the signal charge that should be transferred in the vertical direction in the vertical transfer unit 3 remains, and color mixing occurs.

  On the other hand, in the solid-state imaging device 1 according to the present embodiment, after the charge transfer of one stage is completed, the time until the charge transfer of the next stage is started is secured longer than the period of the vertical transfer clock, As shown in FIG. 6B, the fluctuation of the potential of the p-well 12 generated by the first-stage transfer converges by the start of the second-stage transfer. Thereby, color mixing due to poor transfer of signal charges can be effectively prevented.

  According to the experiments by the inventors, the time from the completion of one-stage charge transfer to the start of the next-stage charge transfer is set to at least three times the period of the vertical transfer clock in the monitor mode. It was found to be effective in eliminating local transfer failures. The upper limit of the time from the completion of one-stage charge transfer to the start of the next-stage charge transfer is determined on condition that the horizontal blanking period in the monitor mode is not longer than that in the still mode. Just do it. This is because as the horizontal blanking period becomes longer, the frame rate deteriorates as described above.

  In this embodiment, an example is shown in which three pixels in the vertical direction are set to one stage in one horizontal blanking period and two-stage transfer is performed. However, even when three or more stages are transferred in one horizontal blanking period. The present invention can be applied. In this case, the time interval from the completion of the first stage charge transfer to the start of the next stage charge transfer may or may not be constant. For example, the time interval from the completion of the previous transfer may be increased as the later transfer is performed.

  In the above embodiment, a solid-state imaging device having a Bayer array color filter is illustrated. However, this is merely an example, and the present invention can be applied to a solid-state imaging device having an arbitrary color filter.

  The present invention can be used as a solid-state imaging device applicable to a video camera, a digital still camera, or the like.

In the solid-state imaging device according to an embodiment of the present invention, it is a waveform diagram showing a drive signal applied to the transfer electrode of the vertical transfer unit in the horizontal blanking period. 1 is a block diagram illustrating a schematic configuration example of a solid-state imaging device according to an embodiment of the present invention. It is a figure which shows schematic structure of the solid-state image sensor with which the solid-state imaging device concerning one Embodiment of this invention is provided. It is a graph which shows the color ratio distribution of the imaging signal in the solid-state imaging device concerning one Embodiment of this invention. It is sectional drawing along the transfer direction of a vertical transfer part. It is a conceptual diagram which shows transition of p well electric potential in a horizontal blanking period, (a) is p well electric potential in the conventional solid-state imaging device, (b) is p well in the solid-state imaging device concerning one Embodiment of this invention. Indicates potential. It is a schematic diagram which shows the operation example of the monitor mode in the conventional solid-state imaging device. In the conventional solid-state imaging device, it is a wave form diagram which shows the drive signal given to the transfer electrode of a vertical transfer part in a horizontal blanking period. It is a graph which shows the color ratio distribution of the imaging signal in the conventional solid-state imaging device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Solid-state image sensor 2 Photoelectric conversion element 3 Vertical transfer part 4 Horizontal transfer part 5 Charge detection part 11 n-type semiconductor substrate 12 p well 13 n-type buried channel 20 Pre-processing circuit 30 Digital signal processing circuit 40 Timing generator 50 Clock driver

Claims (3)

A photoelectric conversion element that stores signal charges photoelectrically converted arranged in a matrix, a vertical transfer unit that reads the signal charges stored from the photoelectric conversion element and transfers them in the vertical direction, and receives a signal charge from the vertical transfer unit A solid-state imaging device including a horizontal transfer unit for transferring in a horizontal direction,
A monitor mode for thinning out the photoelectric conversion element in the vertical direction to read out signal charges and transferring the read signal charges in a plurality of stages from the vertical transfer unit to the horizontal transfer unit in a horizontal blanking period is provided as an operation mode.
In the monitor mode, the vertical transfer unit completes the vertical transfer clock so that the time from the completion of one stage of signal charge transfer to the start of the next stage of signal charge transfer is longer than the period of the vertical transfer clock. A solid-state imaging device comprising a drive unit that supplies a drive signal to a transfer unit.   2. The time from the completion of one stage of signal charge transfer by the vertical transfer section to the start of signal charge transfer of the next stage is at least three times the time required for one step of vertical transfer. The solid-state imaging device described in 1. The drive signal supplied to the vertical transfer unit is supplied to the vertical transfer unit during the horizontal transfer period after the signal transfer of one stage is completed by the vertical transfer unit until the signal charge transfer of the next stage is started. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is the same as a drive signal to be transmitted.

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