JP2006319184A - Solid-state imaging device and camera - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging device and a camera which are capable of reducing the read-out voltage. <P>SOLUTION: The solid-state imaging device is provided with a plurality of photoelectric converting units 5 formed on a substrate horizontally and vertically, a transfer channel 14 formed in a substrate region between the photoelectric conversion units 5 so as to be extended vertically, a read-out gate unit 6 formed between the transfer channel 14 and the photoelectric conversion unit 5 of one side, a pixel-separating unit 8 formed between the transfer channel 14 and the photoelectric conversion unit 5 of the other side, and a first transfer electrode 21, as well as a second transfer electrode 21 formed on the transfer channel 14 and the read-out gate unit 6. The vertical length of the first transfer electrode 21 on the side of read-out gate unit 6 is longer than the vertical length at the side of the pixel-isolating unit 8. The vertical length of the second transfer electrode 22 at the side of pixel-isolating unit 8 is longer than the vertical length on the side of read-out gate unit 6. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to, for example, a CCD (Charge Coupled Device) type solid-state imaging device and a camera including the solid-state imaging device.

  Conventionally, as a transfer electrode of a CCD type solid-state imaging device, a multi-layer structure in which a part of adjacent transfer electrodes is arranged in a superimposed state and a single layer structure in which adjacent transfer electrodes are arranged in a non-overlapped state. Things are in practical use. A transfer electrode having a single-layer electrode structure is disclosed in, for example, Patent Document 1.

  FIG. 9 is a plan view showing a transfer electrode of a solid-state imaging device having a single-layer electrode structure. 10 is a cross-sectional view taken along line B-B ′ of FIG. 9.

The solid-state imaging device includes a plurality of photoelectric conversion units 105, a reading gate unit 106, and a vertical transfer unit 107 that are arranged in the horizontal and vertical directions. The photoelectric conversion unit 105 includes an n-type signal charge accumulation region 112 formed in the p-type well 111 of the n-type substrate 110 and a hole accumulation region 113 composed of a p ⁺ region.

An n-type transfer channel 114 is formed at a predetermined interval with respect to the photoelectric conversion unit 105. A p ⁺ region 115 is formed under the transfer channel 114.

Between the transfer channel 114 and the photoelectric conversion unit 105 on one side (right side in the figure) to be read, a read gate unit 106 made of a p ⁻ region is formed. Between the transfer channel 114 and the photoelectric conversion unit 105 on the other side (the left side in the figure) that is not a readout target, a pixel separation unit 108 made of a p ⁺ region is formed.

  A first transfer electrode 121 and a second transfer electrode 122 are formed on the read gate portion 106 and the transfer channel 114 with an insulating film 120 interposed therebetween. The vertical transfer unit 107 includes a transfer channel 114, a first transfer electrode 121, and a second transfer electrode 122.

  As shown in FIG. 9, the first transfer electrode 121 and the second transfer electrode 122 are formed in a rectangular shape when viewed from above, and the horizontal first transfer electrodes 121 and the second transfer electrodes 122 are connected to each other. Has been. The first transfer electrode 121 and the second transfer electrode 122 adjacent in the vertical direction are separated.

  A light shielding film 124 that covers the transfer electrodes 121 and 122 is formed on the transfer electrodes 121 and 122 with an insulating film 120 interposed therebetween. An opening 124 a that exposes the photoelectric conversion unit 105 is formed in the light shielding film 124.

  In the above-described solid-state imaging device, when the signal charge photoelectrically converted by the photoelectric conversion unit 105 is read to the transfer channel 114, a positive read voltage is applied to the first transfer electrode 121 having a long side in contact with the photoelectric conversion unit 105. Applied.

  FIG. 11 is a diagram illustrating a potential distribution during charge reading. In FIG. 11, P0 is a potential distribution before the read voltage is applied, and P1 is a potential distribution after the read voltage is applied.

  As shown in FIG. 11, a potential barrier due to the read gate unit 106 exists between the transfer channel 114 and the signal charge storage region 112 before the read voltage is applied, and the signal charge is stored in the signal charge storage region 112. Stay inside.

When the read voltage is applied, the potential barrier by the read gate unit 106 is lowered, and the signal charge accumulated in the signal charge accumulation region 112 is read out to the transfer channel 114 (see the arrow in the figure).
JP 2003-7997 A

  By the way, with the recent reduction in pixel size, the width W of the read gate portion 106 whose potential is controlled by the first transfer electrode 121 is narrowed (see FIG. 9).

  When the width W of the read gate portion 106 is narrowed, the charge read efficiency is deteriorated. In order to prevent the deterioration of the charge readout efficiency, it is necessary to increase the readout voltage, which leads to an increase in power consumption of the solid-state imaging device.

  In addition, in order to prevent a decrease in signal charge that can be accumulated in the signal charge accumulation region 112 by reducing the pixel size, it is necessary to deepen the potential well of the signal charge accumulation region 112. When the potential well of the signal charge storage region 112 is deepened, the read voltage is increased.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a solid-state imaging device and a camera capable of reducing a readout voltage.

  In order to achieve the above object, a solid-state imaging device of the present invention includes a plurality of photoelectric conversion units formed in a horizontal direction and a vertical direction on a substrate, and a vertical direction formed in a substrate region between the photoelectric conversion units. An extending transfer channel; a read gate portion formed in a substrate region between the transfer channel and the one photoelectric conversion portion; and a substrate region formed between the transfer channel and the other photoelectric conversion portion. A pixel separation unit; and a first transfer electrode and a second transfer electrode which are disposed adjacent to each photoelectric conversion unit and formed on the transfer channel and the readout gate unit, and the first transfer electrode includes: The length in the vertical direction on the readout gate portion side is longer than the length in the vertical direction on the pixel separation portion side, and the second transfer electrode has a length in the vertical direction on the pixel separation portion side. Longer than the length of the vertical direction in the reading gate portion.

  In the above-described solid-state imaging device of the present invention, the first transfer electrode is formed such that the length in the vertical direction on the readout gate portion side is longer than the length in the vertical direction on the pixel separation portion side. The vertical length of the separation part is formed longer than the vertical length of the read gate part. For this reason, the length in the vertical direction of the readout gate portion whose potential is controlled by the first transfer electrode, that is, the readout gate width is increased.

  In order to achieve the above object, a camera of the present invention includes a solid-state imaging device, an optical system that focuses light on the imaging surface of the solid-state imaging device, and a predetermined signal with respect to an output signal from the solid-state imaging device. A signal processing circuit that performs processing, and the solid-state imaging device includes a plurality of photoelectric conversion units formed in a horizontal direction and a vertical direction on a substrate, and a vertical direction formed in a substrate region between the photoelectric conversion units. Formed in a substrate region between the transfer channel and the photoelectric conversion unit on the other side, a transfer gate extending to the transfer channel, a readout gate unit formed in a substrate region between the transfer channel and the photoelectric conversion unit on one side, A pixel separation unit, and a first transfer electrode and a second transfer electrode that are disposed adjacent to each photoelectric conversion unit and formed on the transfer channel and the readout gate unit, wherein the first transfer electrode is Read out The vertical length on the side of the pixel separation portion is longer than the length of the vertical direction on the side of the pixel separation portion, and the second transfer electrode has a length in the vertical direction on the side of the pixel separation portion. It is longer than the length in the vertical direction on the gate side.

  In the camera of the present invention described above, the first transfer electrode of the solid-state imaging device constituting the camera is formed such that the vertical length on the readout gate portion side is longer than the vertical length on the pixel separation portion side, The second transfer electrode is formed such that the vertical length of the pixel separation portion is longer than the vertical length of the readout gate portion. For this reason, the length in the vertical direction of the readout gate portion whose potential is controlled by the first transfer electrode, that is, the readout gate width is increased.

  According to the present invention, it is possible to realize a solid-state imaging device and a camera with a reduced readout voltage.

  Embodiments of the present invention will be described below with reference to the drawings. In the present embodiment, an example in which the present invention is applied to an interline transfer type CCD (Charge Coupled Device) type solid-state imaging device will be described. However, there is no particular limitation on the transfer method.

  FIG. 1 is a schematic configuration diagram of a solid-state imaging apparatus according to the present embodiment.

  The solid-state imaging device 1 according to the present embodiment includes an imaging unit 2, a horizontal transfer unit 3, and an output unit 4.

  The imaging unit 2 includes a plurality of photoelectric conversion units 5 arranged in a matrix for each pixel, a plurality of vertical transfer units 7 arranged for each vertical column of the photoelectric conversion unit 5, and the photoelectric conversion unit 5. It has a read gate unit 6 arranged between the transfer unit 7.

  The photoelectric conversion unit 5 includes, for example, a photodiode, and photoelectrically converts image light (incident light) incident from a subject into signal charges having a charge amount corresponding to the light amount and accumulates the signal light. The signal charge accumulated in the photoelectric conversion unit 5 is read to the vertical transfer unit 7 via the read gate unit 6.

  The vertical transfer unit 7 is driven by the four-phase clock signals φV1, φV2, φV3, and φV4, and transfers the signal charges read from the photoelectric conversion unit 5 in the vertical direction (downward in the figure). The clock signal is not limited to four phases.

  The horizontal transfer unit 3 is driven by the two-phase clock signals φH1 and φH2, and transfers the signal charges vertically transferred from the vertical transfer unit 7 in the horizontal direction (left direction in the figure).

  The vertical transfer unit 7 and the horizontal transfer unit 3 include a transfer channel formed in the transfer direction formed on the substrate, and a plurality of transfer electrodes formed side by side in the transfer direction with an insulating film interposed on the transfer channel. Have.

  The output unit 4 includes, for example, a charge-voltage conversion unit 4a configured by floating diffusion, converts the signal charge horizontally transferred by the horizontal transfer unit 3 into an electric signal, and outputs the signal as an analog image signal.

  FIG. 2 is a plan view of the transfer electrode arranged in the imaging unit 2.

  A plurality of photoelectric conversion units 5 are arranged in the horizontal direction and the vertical direction. The dimension L in the vertical direction of one photoelectric conversion unit 5 is 1.5 μm, for example, and the dimension H in the horizontal direction is 1.0 μm, for example.

  Transfer channels 14 extending in the transfer direction (vertical direction) are formed on both sides of the photoelectric conversion unit 5. A read gate section 6 is formed between the transfer channel 14 and the photoelectric conversion section 5 on one side (right side in the figure) to be read. The dimension d in the horizontal direction of the read gate unit 6 is, for example, 0.1 to 0.5 μm. A pixel separation unit 8 is formed between the transfer channel 14 and the photoelectric conversion unit 5 on the other side (the left side in the figure) that is not a readout target.

  On the transfer channel 14 and the read gate unit 6, the first transfer electrode 21 and the second transfer electrode 22 are alternately and repeatedly arranged in the transfer direction. The transfer channel 14, the first transfer electrode 21 and the second transfer electrode 22 constitute the vertical transfer unit 7.

  The first transfer electrode 21 and the second transfer electrode 22 are arranged at a predetermined interval from each other. That is, the first transfer electrode 21 and the second transfer electrode 22 have a single-layer electrode structure. The first transfer electrode 21 and the second transfer electrode 22 in the horizontal direction are connected to each other. The first transfer electrode 21 and the second transfer electrode 22 are formed by patterning the same polysilicon layer.

  End portions of the first transfer electrode 21 and the second transfer electrode 22 are formed to be inclined with respect to the horizontal direction in a region adjacent to the photoelectric conversion unit 5. As a result, the first transfer electrode 21 is formed such that the vertical length (corresponding to the read gate width W) on the read gate portion 6 side is longer than the vertical length on the pixel separation portion 8 side. The second transfer electrode 22 is formed such that the vertical length on the pixel separation unit 8 side is longer than the vertical length on the readout gate unit 6 side.

  FIG. 3 is a cross-sectional view taken along the line A-A ′ of FIG. 2.

  For example, a p-type well 11 is formed on an n-type silicon substrate (hereinafter referred to as substrate 10). The p-type well 11 forms an overflow barrier.

In the photoelectric conversion unit 5, an n-type signal charge accumulation region 12 and a hole accumulation region 13 including a p ⁺ region formed on the surface layer of the signal charge accumulation region 12 are formed. A photodiode is formed by a pn junction between the n-type signal charge storage region 12 and the p-type well 11. Since the hole accumulation region 13 is formed on the surface layer of the signal charge accumulation region 12, a buried photodiode with suppressed dark current is obtained.

  In the photoelectric conversion unit 5, an npn structure is formed by the signal charge accumulation region 12, the p-type well 11 and the substrate 10. This npn structure is a vertical type that discharges signal charges to the substrate 10 side when signal charges generated excessively due to strong light incident on the photoelectric conversion unit 5 exceed the overflow barrier formed by the p-type well 11. An overflow drain structure is formed.

The transfer channel 14 disposed on both sides of the photoelectric conversion unit 5 is formed of an n-type region, and a p ⁺ region 15 is formed under the transfer channel 14. The p ⁺ region 15 is provided to prevent the occurrence of smear.

The read gate unit 6 between the transfer channel 14 and the photoelectric conversion unit 5 on one side is formed by a p ⁻ region. The pixel separation unit 8 between the transfer channel 14 and the photoelectric conversion unit 5 on the other side is formed by a p ⁺ region having a high p-type impurity concentration.

  A first transfer electrode 21 and a second transfer electrode 22 are formed on the transfer channel 14 and the read gate portion 6 with an insulating film 20 interposed therebetween. On the transfer channel 14, the first transfer electrode 21 is formed on the read gate unit 6 side, and the second transfer electrode 22 is formed on the pixel separation unit 8 side. The transfer channel 14, the first transfer electrode 21 and the second transfer electrode 22 constitute the vertical transfer unit 7.

  A light shielding film 24 made of aluminum or the like is formed on the first transfer electrode 21 and the second transfer electrode 22 with the insulating film 20 interposed therebetween. An opening 24 a that exposes the photoelectric conversion unit 5 is formed in the light shielding film 24.

  Although not shown, an interlayer insulating film is formed on the light shielding film 24, and a color filter and an on-chip lens are formed on the interlayer insulating film as necessary.

  FIG. 4 is a diagram illustrating a potential distribution at the time of reading signal charges in the solid-state imaging device according to the present embodiment. In the figure, P0 is a potential distribution before the read voltage is applied, and P1 is a potential distribution after the read voltage is applied.

  Before the read voltage is applied, a potential barrier formed by the read gate unit 6 is formed between the signal charge storage region 12 and the transfer channel 14. For this reason, the signal charge is in a state of being accumulated in the signal charge accumulation region 12.

  At the time of reading signal charges, a positive voltage is applied to the first transfer electrode 21 and a negative voltage is applied to the second transfer electrode 22. The positive voltage applied to the first transfer electrode 21 is, for example, 0V to 20V (excluding 0V). The negative voltage applied to the second transfer electrode 22 is, for example, 0 V to −20 V (excluding 0 V).

  By applying a positive voltage to the first transfer electrode 21, the potential of the p-type read gate unit 6 is increased (the potential barrier is lowered), and the signal charge accumulated in the signal charge accumulation region 12 is transferred to the transfer channel. 14 (see arrow in the figure).

  Further, since a negative voltage is applied to the second transfer electrode 22 on the side close to the signal charge storage region 12 (right side), the potential on the side opposite to the read side in the signal charge storage region 12 decreases (potential). Well becomes shallower). For this reason, a potential gradient (electric field) is generated in the signal charge storage region 12, and charges are easily moved in the reading direction.

  After the signal charges are read out to the vertical transfer unit 7, the clock signals φV 1, V 2, V 3, V 4 are applied to the transfer electrodes 21, 22 arranged in the transfer direction with a phase shift ( 2), the distribution of the potential well of the transfer channel 14 extending in the vertical direction changes sequentially, and the charge in the potential well is transferred along the transfer direction.

  The signal charge transferred to the horizontal transfer unit 3 is transferred in the horizontal direction by the horizontal transfer unit 3, and the signal charge transferred horizontally by the output unit 4 is converted into an electrical signal and output as an analog image signal.

  Next, effects of the solid-state imaging device according to the above-described embodiment will be described.

  In the present embodiment, the first transfer electrode 21 is formed such that the length in the vertical direction on the readout gate unit 6 side is longer than the length in the vertical direction on the pixel separation unit 8 side, and the second transfer electrode 22 is formed with pixel separation. The vertical length of the portion 8 is longer than the vertical length on the read gate portion 6 side.

  For this reason, the vertical length (read gate width W) of the read gate section 6 whose potential is controlled by the first transfer electrode 21 can be increased. Since the read efficiency can be improved by increasing the read gate width W, the read voltage can be reduced.

  Further, at the time of reading, a positive voltage is applied to the first transfer electrode 21 while a negative voltage is applied to the second transfer electrode 22, whereby the photoelectric conversion unit 5 has a portion opposite to the reading gate unit 6 side. , And a potential gradient is generated to facilitate the movement of charges toward the read gate portion 6. As a result, the read efficiency can be further improved, so that the read voltage can be further reduced.

  Conventionally, as shown in FIG. 10, when a positive voltage is applied to the first transfer electrode 121 on the transfer channel 114 at the time of reading, the pn between the n-type transfer channel 114 and the p-type pixel separation unit 108 is obtained. There is also a problem that a reverse bias is applied to the junction, the potential gradient in this portion becomes steep (the electric field becomes large), charge is generated due to avalanche breakdown, and noise is generated.

  On the other hand, in the present embodiment, the second transfer electrode 22 is formed on the transfer channel 14 in the vicinity of the pn junction with the p-type pixel separation unit 8, and the second transfer electrode 22 is formed at the time of reading. By applying a negative voltage, the potential gradient at the pn junction can be made gentler than before. As a result, avalanche breakdown can be suppressed and noise can be reduced.

  The solid-state imaging device is used by being incorporated in a camera such as a video camera, a digital still camera, or an electronic endoscope camera, for example.

  FIG. 5 is a schematic configuration diagram of a camera in which the above-described solid-state imaging device is used.

  The camera 30 includes a solid-state imaging device (CCD) 1, an optical system 32, a drive circuit 33, and a signal processing circuit 34.

  The optical system 32 forms image light (incident light) from the subject on the imaging surface of the solid-state imaging device 1. Thereby, in each photoelectric conversion unit 5 of the solid-state imaging device 1, incident light is converted into a signal charge corresponding to the amount of incident light, and the signal charge is accumulated in the signal charge accumulation region 12 of the photoelectric conversion unit 5 for a certain period. .

  The drive circuit 33 provides the solid-state imaging device 1 with various timing signals such as the four-phase clock signals φV1, φV2, φV3, φV4 and the two-phase clock signals φH1, φH2. As a result, various types of driving such as signal charge readout, vertical transfer, and horizontal transfer of the solid-state imaging device 1 are performed. Further, by this driving, an analog image signal is output from the output unit 4 of the solid-state imaging device 1.

  The signal processing circuit 34 performs various types of signal processing such as noise removal and conversion into a digital signal on the analog image signal output from the solid-state imaging device 1. After the signal processing by the signal processing circuit 34, it is stored in a storage medium such as a memory.

  As described above, in the camera 30 such as a video camera or a digital still camera, the camera 30 with low power consumption can be realized by using the solid-state imaging device 1 in which the readout voltage is reduced.

(Second Embodiment)
FIG. 6 is a plan view of the transfer electrode arranged in the imaging unit 2. In the present embodiment, the first transfer electrode 21 and the second transfer electrode 22 have a single-layer electrode structure, but the planar shapes of the first transfer electrode 21 and the second transfer electrode 22 are different from those in the first embodiment.

  The length of the first transfer electrode 21 in the vertical direction on the side of the read gate section 6 is enlarged until it becomes the same as the vertical dimension L of the photoelectric conversion section 5. As a result, the first transfer electrode 21 in the region adjacent to the photoelectric conversion unit 5 has a triangular shape.

  The vertical length of the second transfer electrode 22 on the pixel separation unit 8 side is enlarged until it becomes the same as the vertical dimension L of the photoelectric conversion unit 5. As a result, the second transfer electrode 22 in the region adjacent to the photoelectric conversion unit 5 has a triangular shape.

  In the solid-state imaging device according to the present embodiment, the read gate width W can be made larger than that in the first embodiment. As a result, the read efficiency can be further improved, and the read voltage can be lowered.

  In consideration of the balance between the read efficiency and the charge transfer efficiency, the first transfer electrode 21 and the second transfer electrode 21 each having an intermediate electrode shape between the transfer electrode shape of the first embodiment and the transfer electrode shape of the second embodiment. The transfer electrode 22 may be formed. Moreover, in the 1st transfer electrode 21 and the 2nd transfer electrode 22, the length of the side of a long side electrode does not need to be the same.

(Third embodiment)
FIG. 7 is a plan view of the transfer electrode arranged in the imaging unit 2. In the present embodiment, the first transfer electrode 21 and the second transfer electrode 22 have a single-layer electrode structure, but the planar shapes of the first transfer electrode 21 and the second transfer electrode 22 are different from those in the first embodiment.

  In the present embodiment, end portions of the first transfer electrode 21 and the second transfer electrode 22 are formed in a step shape in a region adjacent to the photoelectric conversion unit 5. As a result, the first transfer electrode 21 is formed such that the vertical length (corresponding to the read gate width W) on the read gate portion 6 side is longer than the vertical length on the pixel separation portion 8 side. The second transfer electrode 22 is formed such that the vertical length on the pixel separation unit 8 side is longer than the vertical length on the readout gate unit 6 side.

  Also by the solid-state imaging device according to the present embodiment, the same effects as those of the first embodiment can be obtained.

(Fourth embodiment)
FIG. 8 is a plan view of the transfer electrode arranged in the imaging unit 2. In the present embodiment, a case where the first transfer electrode 21 and the second transfer electrode 22 have a two-layer electrode structure will be described.

  The first transfer electrode 21 and the second transfer electrode 22 that are adjacent in the vertical direction are arranged so that their ends overlap each other. The first transfer electrode 21 and the second transfer electrode 22 in the horizontal direction are connected to each other.

  In this example, the first transfer electrode 21 is formed in the upper layer of the second transfer electrode 22, but the first transfer electrode 21 may be formed in the lower layer of the second transfer electrode 22. The second transfer electrode 22 is formed of, for example, a first polysilicon layer, and the first transfer electrode 21 is formed of, for example, a second polysilicon layer.

  The ends of the first transfer electrode 21 and the second transfer electrode 22 that are overlapped with each other are formed to be inclined with respect to the horizontal direction in a region adjacent to the photoelectric conversion unit 5. Note that the end portions of the first transfer electrode 21 and the second transfer electrode 22 may be formed stepwise as in the third embodiment.

  Also in the solid-state imaging device having the above two-layer electrode structure, the same effect as that of the first embodiment can be obtained by increasing the length of the first transfer electrode 21 to which the read voltage is applied on the read gate portion 6 side. Can do.

The present invention is not limited to the description of the above embodiment.
For example, in the present embodiment, a solid-state imaging device having a single-layer electrode structure or a two-layer electrode structure has been described. However, the present invention can also be applied to a solid-state imaging device having an electrode structure having three or more layers. In this embodiment, the interline transfer type CCD solid-state image pickup device has been described. However, another transfer type CCD solid-state image pickup device such as a frame interline transfer type may be used.

Alternatively, the second transfer electrode 22 may be formed such that the length in the vertical direction on the read gate unit 6 side is longer than the length in the vertical direction on the pixel separation unit 8 side. In this case, the first transfer electrode 21 in which the vertical length of the pixel separating unit 8 is longer than the vertical length of the readout gate unit 6 is formed. Further, the material of the first transfer electrode 21 and the second transfer electrode 22 is not limited.
In addition, various modifications can be made without departing from the scope of the present invention.

It is a schematic block diagram which shows an example of the solid-state imaging device which concerns on 1st Embodiment. It is a top view of the transfer electrode in the solid-state imaging device concerning a 1st embodiment. FIG. 3 is a cross-sectional view taken along line A-A ′ of FIG. 2. In a solid-state imaging device concerning this embodiment, it is a figure showing potential distribution at the time of reading of a signal charge. It is a block diagram which shows schematic structure of the camera which concerns on this embodiment. It is a top view of the transfer electrode in the solid-state imaging device concerning a 2nd embodiment. It is a top view of the transfer electrode in the solid-state imaging device concerning a 3rd embodiment. It is a top view of the transfer electrode in the solid-state imaging device concerning a 4th embodiment. It is a top view of the transfer electrode in the conventional solid-state imaging device. FIG. 10 is a cross-sectional view taken along line B-B ′ of FIG. 9. It is a figure which shows the electric potential distribution at the time of charge reading in the conventional solid-state imaging device.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Solid-state imaging device, 2 ... Imaging part, 3 ... Horizontal transfer part, 4 ... Output part, 4a ... Charge-voltage conversion part, 5 ... Photoelectric conversion part, 6 ... Read-out gate part, 7 ... Vertical transfer part, 8 ... Pixel separation unit, 10 ... substrate, 11 ... p-type well, 12 ... signal charge storage region, 13 ... hole storage region, 14 ... transfer channel, 15 ... p-type region, 20 ... insulating film, 21 ... first transfer electrode 22 ... second transfer electrode, 24 ... light-shielding film, 24a ... opening, 30 ... camera, 32 ... optical system, 33 ... drive circuit, 34 ... signal processing circuit, 105 ... photoelectric conversion unit, 106 ... reading gate unit, DESCRIPTION OF SYMBOLS 107 ... Vertical transfer part, 108 ... Pixel separation part, 110 ... Substrate, 111 ... p-type well, 112 ... Signal charge storage area, 113 ... Hole storage area, 114 ... Transfer channel, 115 ... P-type area, 120 ... Insulation Membrane 121 ... first transfer electrode 122 ... first Transfer electrodes, 124 ... light-shielding film, 124a ... opening

Claims (6)

A plurality of photoelectric conversion portions formed in the horizontal and vertical directions on the substrate;
A transfer channel extending in a vertical direction formed in a substrate region between the photoelectric conversion units;
A readout gate part formed in a substrate region between the transfer channel and the photoelectric conversion part on one side;
A pixel separation part formed in a substrate region between the transfer channel and the photoelectric conversion part on the other side;
A first transfer electrode and a second transfer electrode which are arranged adjacent to each photoelectric conversion unit and formed on the transfer channel and the read gate unit;
The first transfer electrode has a length in the vertical direction on the readout gate portion side that is longer than a length in the vertical direction on the pixel separation portion side,
The solid-state imaging device, wherein the second transfer electrode has a length in the vertical direction on the pixel separation portion side that is longer than a length in the vertical direction on the readout gate portion side. The solid-state imaging device according to claim 1, wherein end portions of the first transfer electrode and the second transfer electrode are formed to be inclined with respect to the horizontal direction in a region adjacent to the photoelectric conversion unit. The solid-state imaging device according to claim 1, wherein end portions of the first transfer electrode and the second transfer electrode are formed in a step shape in a region adjacent to the photoelectric conversion unit. The solid-state imaging device according to claim 1, wherein when a read voltage is applied to the first transfer electrode, a voltage having a polarity opposite to the read voltage is applied to the second transfer electrode. The solid-state imaging device according to claim 1, wherein the first transfer electrode and the second transfer electrode are formed of the same layer. A solid-state imaging device;
An optical system for imaging light on the imaging surface of the solid-state imaging device;
A signal processing circuit that performs predetermined signal processing on an output signal from the solid-state imaging device;
The solid-state imaging device
A plurality of photoelectric conversion portions formed in the horizontal and vertical directions on the substrate;
A transfer channel extending in a vertical direction formed in a substrate region between the photoelectric conversion units;
A readout gate part formed in a substrate region between the transfer channel and the photoelectric conversion part on one side;
A pixel separation part formed in a substrate region between the transfer channel and the photoelectric conversion part on the other side;
A first transfer electrode and a second transfer electrode which are arranged adjacent to each photoelectric conversion unit and formed on the transfer channel and the read gate unit;
The first transfer electrode has a length in the vertical direction on the readout gate portion side that is longer than a length in the vertical direction on the pixel separation portion side,
The second transfer electrode is a camera in which a length in the vertical direction on the pixel separation portion side is longer than a length in the vertical direction on the readout gate portion side.

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