JP2006313644A - Nonvolatile semiconductor memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To write data to a plurality of memory cells in a plurality of cell array blocks simultaneously. <P>SOLUTION: The memory is provided with; a memory core section comprising a plurality of cell array blocks equipped with a plurality of nonvolatile memory cells, a plurality of word lines, and a plurality of bit lines; and a means to erase data simultaneously in a plurality of memory cells in one cell array block and write data in the plurality of memory cells in the plurality of cell array blocks simultaneously. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory, and more particularly to an electrically erasable / rewritable semiconductor memory (EEPROM), for example, used for a NOR flash memory.

  An example of an EEPROM having a stacked gate structure of a floating gate and a control gate, and having an array of memory cells for storing “0” data and “1” data in a nonvolatile manner by changing the number of electrons accumulated in the floating gate There is a NOR flash memory that can be erased in a batch.

  24A to 24C schematically show a plane pattern and a cross-sectional structure of an example of a single memory cell of the NOR type flash memory. FIG. 24A is a plane pattern diagram, and FIG. FIG. 24 is a cross-sectional view taken along line BB ′ in FIG. 24A, and FIG. 24C is a cross-sectional view taken along line CC ′ in FIG.

  24A to 24C, 1a is a P-type semiconductor substrate, 1b is an N-type well formed on the P-type substrate, and 1c is a P for forming a cell region formed on the N-type well. A cell array is formed on the P-type well 1c.

  2 is an element isolation insulating film, 3 is a gate oxide film, 4 is a cell floating gate, 5 is a cell control gate, 6 is a floating gate-control gate insulating film, 7 is an interlayer insulating film, 8 is a bit line, 9 Denotes a cell drain region (n-type diffusion region), 10 denotes a cell source region (n-type diffusion region, source line), and 11 denotes a bit line contact portion.

  The cell having the above-described configuration includes the drain 9, the source 10, the floating gate 4, and the control gate 5, and stores data by varying the amount of charge stored in the floating gate 4.

  FIG. 25 shows an example of a memory cell array in which a plurality of the memory cells shown in FIGS. 24A to 24C are arranged in a matrix.

  Each of the memory cells MC00 to MCn0, MC01 to MCn1,..., MC0m to MCnm has a gate electrode connected to one word line of the plurality of word lines WL0 to WLn and a drain electrode connected to the plurality of bit lines BL0 to BLm. One of the bit lines is connected, and the source electrode is connected to the source line SL.

  The NOR type flash memory has a multi-bit configuration in which a plurality of bits of data are input / output simultaneously with the outside at the time of data writing / reading. As an example, a 16-bit configuration having a bit width of 16 It has been known.

  The NOR-type flash memory having a plurality of bits has the same cell array block divided into N units in units of multiple columns, and when reading / writing data, N-segment memory cells are selected by the same row selection signal, and N-segment memory cells are selected by the column selection signal. By selecting one memory cell from each memory cell, N memory cells are selected simultaneously.

  FIG. 26 shows a part of a peripheral circuit related to a part of a cell array block in a NOR flash memory having a multi-bit configuration.

  The bit lines are divided into groups BL1 to BL15,..., For example, and each one end of the column selection transistor CS is connected to each one end side of the four bit lines of each group BL1 to BL15,. The other ends of the four column selection transistors CS are connected together to form a common bit line. The common bit line is connected to a bit line load transistor LT, a sense amplifier SA, a write transistor WT, and the like via a bit line potential clamping transistor CT.

  In the NOR type flash memory having a plurality of bits, each bit line BL0 to BL15, BL16 to BLm in FIG. 25 is one of the four bit lines of each group BL1 to BL15,. Each one is shown.

  On the other hand, in the NOR flash memory, when data is rewritten in a certain memory cell, the other cell sharing the bit line or word line with the cell becomes half-selected and the data state changes. In order to prevent (disturbance during data rewriting), the word line / bit line is separated for each block unit to be erased.

  A block unit to be erased is generally 512K bits, and for example, a cell array block having a 1K word line × 512 bit line configuration or a 512 word line × 1K bit line configuration is employed.

  Next, data write / read / erase operations in the NOR flash memory will be described.

  (1) When memory cells MC00 to MC015 are selected at the time of data writing, Vpp (voltage of about 10 V) is applied to the selected word line WL0 shared by these memory cells MC00 to MC015, and other unselected word lines WL1 to WLn are set to 0V.

  The bit line voltage applied to the selected bit lines BL0 to BL15 connected to the selected memory cells MC00 to MC015 depends on the write data, and Vdp (about 5V) is applied to the bit line for writing "0" data. And 0V is applied to the bit line for writing “1” data. The source line SL is set to 0V.

  As a result, among the selected memory cells MC00 to MC015, the selected memory cell to which "0" data is written has a gate of Vpp and a drain of Vdp, and some of the electrons moving from the source to the drain have high energy. Some of them reach the floating gate by the electric field in the gate direction. Thus, the “1” data state with a relatively small number of electrons in the floating gate changes to a “0” data state with a relatively large number of electrons.

  In the memory cells (non-selected memory cells and selected memory cells to which “1” data is written) whose gate-drain voltage relationship is other than the above, the drain current does not flow and the data in the memory cells does not change.

  (2) When memory cells MC00 to MC015 are selected at the time of data reading, Vcc (voltage of about 5V) is applied to the selected word line WL0 shared by these memory cells, and the other unselected word lines WL1 to WLn Is set to 0V.

  The bit line voltage applied to the selected bit lines BL0 to BL15 connected to the selected memory cells MC00 to MC015 is set to Vd (a voltage of about 1 V) by the bit line potential clamping transistor, and the unselected bit line 0V is applied to. The source line SL is set to 0V.

  At this time, among the selected memory cells MC00 to MC015, the threshold voltage of the memory cell in the “1” data state is lower than Vcc, and the threshold voltage of the memory cell in the “0” data state is higher than Vcc. Current flows, but no current flows in the "0" cell. “0” data and “1” data can be read by sensing a voltage corresponding to this current with a sense amplifier.

  (3) When data is erased (a kind of data is written), the selected cell array blocks are collectively performed. In this case, there are a method of applying an erase voltage to the source line SL of the block to be erased and a method of applying an erase voltage to the cell well of the block to be erased.

  In the former erasing method, all word lines in the block to be erased are set to 0 V or lower, and a high erasing voltage is applied to the source line SL. As a result, in all the memory cells in the block to be erased, a high electric field is applied to the gate oxide film in the overlap portion of the source region and the floating gate, and electrons in the floating gate are released to the source region by tunneling. The data in the memory cell is “1”.

  In the non-selected cell array block, the word lines are all 0V and the source line SL is 0V, so the data in the memory cells is not erased.

  In the latter erasing method, all word lines in the block to be erased are set to 0 V, and a high erasing voltage is applied to the P-type well and the N-type well. As a result, in all the memory cells in the block to be erased, a high electric field is applied to the gate oxide film between the well and the floating gate, and the electrons in the floating gate escape to the well. 1 ".

  In the non-selected cell array block, all the word lines are 0V and the well is 0V, so the data in the memory cell is not erased.

  By the way, in order to realize a flash memory of a single power source by unifying the power source used for the flash memory that requires a higher programming voltage and erasing voltage than the power source voltage (about 5 V) as described above, A write voltage booster circuit and an erase voltage booster circuit are provided.

  The pattern area necessary for realizing these booster circuits to have a required current supply capability and the current consumed by the operation depend on the ratio of the write / erase voltage and the power supply voltage.

  When the voltage of the flash memory is required to be lowered, but the write / erase voltage cannot be lowered, the pattern area required for the booster circuit increases, and as a result, the current consumption also increases.

  However, in the conventional NOR type flash memory, the area of the write voltage booster circuit and the current consumption are increased, and the reason will be described below.

  FIG. 27 shows the write time vs. threshold voltage change characteristic of each memory cell MCi, and FIG. 28 shows the write time vs. write current (drain current) change characteristic.

  As can be seen from the characteristics of FIGS. 27 and 28, at the initial stage of writing, the threshold voltage of the memory cell is low, so the drain current is large (the initial value is 450 μA).

  The conventional writing method is to simultaneously write a write bit of a bit width to a plurality of memory cells in the same cell array block. When writing "0" data to all selected memory cells, a particularly large write current is required. Therefore, the area and current consumption required for the write voltage booster circuit to sufficiently supply this current are increased.

  As a method for reducing the write voltage booster circuit area and current consumption, for example, as shown in the write signal shown in FIG. 29, the write bit is divided into two and the write is simply performed in a time-sharing manner. A method of halving the circuit area and current consumption can be considered.

  That is, in the NOR flash memory having the bit width of 16 as described above, a method of reducing the number of bits written at a time to half (8) of the bit width and halving the current supply capability necessary for the write voltage booster circuit can be considered. However, there is a problem that the writing time is doubled.

  Further, in the conventional NOR type flash memory, the area of the erase voltage booster circuit and the current consumption are increased, and the reason will be described below.

  FIG. 30 shows the erase time vs. threshold voltage change characteristic of each memory cell MCi, and FIG. 31 shows the erase time vs. erase current (source current) change characteristic.

  As can be seen from the characteristics of FIGS. 30 and 31, in the initial stage of erasing, the threshold voltage of the memory cell is high and the electric field in the tunnel oxide film is high, so that the band-to-band tunnel current is large (maximum 4 mA).

  Conventionally, in order to sufficiently supply the band-to-band tunneling current, the boost voltage circuit for erase voltage is set so that the supply current of the boost circuit for erase voltage is a maximum of 4 mA corresponding to the initial value of the band-to-band tunnel current. Therefore, the area and current consumption required for the erase voltage booster circuit are increased.

  In this case, since the erase size is determined to be 512 K bits according to the specification, the necessary supply current cannot be reduced in the conventional batch erase method.

  On the other hand, in a conventional NOR flash memory, when a plurality of memory cells in the same cell array block are simultaneously selected and written at the same time when data is written, the drain current (write current) of the simultaneously written cells is set to each cell. When the number of bits to be simultaneously written is increased, the source line potential is increased by the parasitic resistance of the common source line SL, and the maximum number of bits that can be simultaneously written depends on the writable critical source voltage Vc. There is a problem that the number of bits that can be written at one time is limited, and this point will be described below.

  FIG. 32 schematically shows an example of a part of a cell array block and column gates (column selection transistors and block selection transistors) in a conventional NOR type flash memory.

  In the cell array block, a plurality of memory cells MC are arranged in a matrix (here, for simplification of illustration, only one row of cells is representatively shown). The word lines WLi are commonly connected to the control gates of the memory cells in the same row, and the bit lines BLi are commonly connected to one ends of the memory cells in the same column. In other words, the same row or the same column is connected. Any two of the memory cells share a word line or a bit line.

  A column selection transistor and a block selection transistor are connected in series to each bit line, and a data line DL is commonly connected to one end of each block selection transistor for each of a plurality of predetermined bit lines.

  In such a NOR flash memory, at the time of data reading / writing / erasing, one or a plurality of memory cells in the cell array block are simultaneously selected.

  The memory cells to be simultaneously written are in the same cell array block, and the column selection signal and the block selection signal corresponding to the selected column are set to “H”.

  In this case, since the drain currents (write currents) of simultaneously written cells are collected in the common source line SL at the time of data writing, if the number of bits to be simultaneously written in the same cell array block is increased, the parasitic resistance Rs of the common source line SL As the source line potential rises, the maximum number of bits that can be simultaneously written is determined by the writable critical source voltage Vc, and the number of bits that can be written at one time is limited.

  That is, if there are too many bits to be written at the same time, the source potential of the memory cell rises and it becomes difficult for the drain current to flow, and as a result, the write characteristics deteriorate.

  Further, the resistance of the P-type well in which the memory cell is formed makes it difficult for holes generated in the write operation to flow, and the potential of the P-type well rises to cause punch-through.

  Therefore, when performing a rewrite test, erasure is performed in a batch of cell array blocks, so the erase time per bit is short, but the write time per bit becomes longer due to restrictions on the number of bits that can be written simultaneously, and this increases the test time. Means an increase in test costs.

  As described above, the conventional nonvolatile semiconductor memory is particularly useful when writing “0” data to all of the selected memory cells when simultaneously writing the write bits corresponding to the bit width to a plurality of memory cells in the same cell array block. Since a large write current flows, there is a problem in that the area and current consumption required for the write voltage booster circuit to sufficiently supply this current are increased.

  In addition, the conventional batch erase method has a problem that a required supply current increases, and an area and current consumption required for the booster circuit for erase voltage increase.

  In addition, the test time becomes longer due to the restriction on the number of bits that can be written simultaneously, and as a result, the test cost increases.

  The present invention has been made to solve the above problems, and an object of the present invention is to provide a nonvolatile semiconductor memory capable of simultaneously writing data to a plurality of memory cells in a plurality of cell array blocks.

  The nonvolatile semiconductor memory according to the present invention includes a memory core unit having a plurality of cell array blocks each including a plurality of nonvolatile memory cells, a plurality of word lines, and a plurality of bit lines, and a plurality of memory cells in one cell array block. Means for simultaneously erasing data and simultaneously writing data to a plurality of memory cells in a plurality of cell array blocks.

  A nonvolatile semiconductor memory according to the present invention includes a memory core portion having a plurality of cell array blocks each including a plurality of nonvolatile memory cells, a plurality of word lines, and a plurality of bit lines, and a column address for designating a column address of the cell array block A decoder, a block address decoder for designating an address of the cell array block, a write load circuit for outputting a voltage according to write data at the time of data write, and a row decoder for selecting the word line, The column address and the block address are selected, and the plurality of cell array blocks are simultaneously selected by the block address decoder, and the voltage output from the write load circuit is supplied to the plurality of bit lines to write data. Characterized in that it is done

  According to the nonvolatile semiconductor memory of the present invention, data can be simultaneously written into a plurality of memory cells in a plurality of cell array blocks.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  First, features of the present invention relating to data writing in a NOR flash memory will be described.

  As can be seen from the write time vs. threshold voltage change characteristic of the memory cell shown in FIG. 27 and the write time vs. write current change characteristic of the memory cell shown in FIG. 28, the threshold voltage of the memory cell is low at the initial stage of writing. Although the current is large, the drain current decreases as writing progresses. The initial value of the drain current is 450 μA, the drain current 2 μs after the start of writing is 225 μA, and the threshold voltage 10 μs after the start of writing is 6.5 V (“0” data).

  Therefore, in the writing method of the present invention, when data is written, a plurality of memory cells selected at the same time are divided into N (≧ 2), and the first writing is performed serially for each first time in units of memory cells of each section. Write period (for example, the time until the write current of the memory cell is almost halved from the initial value) and a second write period (preferably the first write period) for each second time in units of two or more memory cells. The data is written separately in a time longer than one time).

  That is, the writing time is shortened by writing according to a sequence designed to increase the number of write bits as the write progresses.

<First embodiment>
The NOR-type flash memory having a 16-bit configuration according to the first embodiment has the same basic configuration as the NOR-type flash memory of the conventional example described above with reference to FIGS.

  That is, the cell array block (for one) has a basic configuration as shown in FIG. 25, and when writing data, an arbitrary one word line is selected from a plurality of word lines in the same cell array block and a plurality of word lines are selected. A cell selection circuit (word line selection circuit, column selection circuit) for simultaneously selecting one bit line of each of a plurality of groups of the bit lines is provided.

  As shown in FIG. 26, a bit potential clamping transistor CT and a load transistor at the time of reading are connected to a plurality of groups of bit lines in the cell array block (that is, a common bit line in which a plurality of bit lines of each group are commonly connected). LT, a write transistor WT, a sense amplifier SA, and the like are connected.

  In the present embodiment, the circuit for generating the write control pulse signal and the write control method (sequence) are different from those of the above-described NOR type flash memory, and this point will be mainly described below.

  FIG. 1 shows an example of operation waveforms for generating the write control pulse signals .phi.6 to .phi.9 of the NOR type flash memory according to the first embodiment.

  FIGS. 2A to 2D and FIGS. 3A to 3C show circuit examples for generating various signals shown in FIG.

  In the PGM generation circuit of FIG. 2A, a NAND circuit NA group and an inverter IV group constitute a predetermined logic circuit, and an enable control signal PGM having a pulse width of 26 .mu.s based on the clock signals .phi.1 to .phi.4 and the write signal WE. Is generated.

  The .phi.1 generation circuit of FIG. 2 (b) has a predetermined logic circuit constituted by the NAND gate NA and the inverter IV group, and generates a clock signal .phi.1 having a pulse width of 2 .mu.s based on the enable control signal PGM.

  In the φ5 generation circuit of FIG. 2 (c), a NAND gate NA group, a delay gate DL and an inverter IV group constitute a predetermined logic circuit, and a clock having a pulse width of 24 μs based on the clock signal φ1 and the enable control signal PGM. A signal φ5 is generated.

  In the binary counter circuit of FIG. 2 (d), a predetermined logic circuit is configured by the frequency divider DEV, NAND gate NA, and inverter IV group connected in three stages. Then, each frequency divider DEV is reset by the inverted signal of the enable control signal PGM, the complementary signal input of the NAND signal of the clock signals φ1 and φ5 is frequency-divided, and the clock signal having a pulse width of 4 μs is obtained by the first-stage frequency divider. φ2 is generated, a clock signal φ3 having a pulse width of 8 μs is generated by the next stage frequency divider, and the clock signal φ4 is taken out from the final frequency divider.

  In the circuit of FIG. 3A, a predetermined logic circuit is constituted by a NAND gate NA group and an inverter IV group, and a desired write control pulse signal as shown in FIG. 1 is based on the signals .phi.1, .phi.3 to .phi.5. Generate φ6.

  In the circuit of FIG. 3B, a predetermined logic circuit is constituted by the NOR gate NR group and the inverter IV group, and a desired write control pulse signal .phi.7 as shown in FIG. 1 is generated based on the signals .phi.1 to .phi.5. Generate.

  In the circuit of FIG. 3C, a NAND gate NA group, a NOR gate NR, and an inverter IV group constitute a predetermined logic circuit, and desired write control as shown in FIG. 1 is performed based on the signals .phi.1 to .phi.4. Pulse signals φ8 and φ9 are generated.

  In the writing operation of the NOR type flash memory of the first embodiment, the memory cell is divided into four when writing 16-bit width data. First, the first writing period (the initial writing current of the memory cell is in units of 4 bits). For example, the time from the value 450 μA to approximately half the time (in this example, 2 μs) is written serially, but after that, the second write is performed in units of 8 bits, for example, twice the 4-bit unit, which is longer than the first write period. Data is written serially by a period (time until the threshold voltage of the memory cell written during the first writing period reaches a predetermined value, in this example, 8 μs).

  Here, when a booster circuit with a supply current of 1.8 mA is used to reduce the area and current consumption of the booster circuit for write voltage, the total write time is 1.8 mA / 450 μA × 2 μs + 1.8 mA / 225 μA. × 8 μs = 24 μs is sufficient.

  On the other hand, according to the writing method as described above with reference to FIG. 29, when the write bits are divided into units of 4 bits and simply time-divisionally written, the total write time is 1.8 mA / 450 μA × It takes 10 μs = 40 μs.

  That is, according to the first embodiment, it is possible to reduce the area and current consumption of the write voltage booster circuit and to greatly shorten the write time.

  In the actual write operation, the write signal used to drive the write transistor WT in FIG. 26 includes the write control pulse signals φ6 to φ9 shown in FIG. Generated by ANDing the signal and write data ("0" data or "1" data).

  That is, according to the NOR type flash memory of the first embodiment, the number of write bits divided as the write progresses is decreased (the number of write bits is increased), thereby increasing the voltage from the booster circuit for the write voltage. Compared with the conventional method in which the limited supply current is efficiently distributed and the number of divisions is fixed, the writing time can be shortened.

  In general terms, the first embodiment is expanded to include a plurality of word lines, a plurality of bit lines, a source line, and a gate electrode, a drain electrode, and a source electrode, respectively. Of the plurality of bit lines, the drain electrode is connected to one bit line of the plurality of bit lines, and the source electrode is connected to the plurality of nonvolatile lines connected to the source line. Memory cell and cell selection circuit for selecting any one word line among the plurality of word lines and simultaneously selecting each one bit line of a plurality of groups among the plurality of bit lines at the time of data writing A plurality of transistors connected to the plurality of groups of bit lines, and a plurality of bits for a plurality of memory cells simultaneously selected by the cell selection circuit. Data when writing, characterized by comprising a writing means for gradually increasing the number of write bit progresses write.

  Next, features of the present invention relating to data erasure in a NOR flash memory will be described.

  30 and 31, the initial value of the band-to-band tunneling current is 4 mA. However, the band-to-band tunneling current decreases as erasing progresses, and the band-to-band tunneling current 2 ms after the start of erasing is 1 mA. The threshold voltage after 10 ms from the start of erasure is 3V ("1" data).

  The data erasing operation in the NOR flash memory of each embodiment relating to data erasing described below reduces the number of bits to be erased or immediately after the start of erasing compared to the conventional method in which the number of erasing bits is fixed to 512 Kbits. Is characterized by reducing the area and current consumption of the erase voltage booster circuit by decreasing the number of erase bits and increasing the number of erase bits as the erase progresses.

  Such control can be realized using means for simultaneously selecting a row decoder block by simultaneously selecting a plurality of row address predecode signals.

<Second embodiment>
In the second embodiment, when erasing data of a cell array block MCA having a bit capacity of 512 Kbits (64 Kbytes), the row decoder and a plurality of word lines are divided into N (≧ 2), and each division is selected serially. By erasing, the peak of the erasing current is dispersed, and the area necessary for the erasing voltage booster circuit is reduced.

  FIG. 4 shows an example of the configuration of one cell array block MCA sharing one source line and the corresponding row decoder array in the NOR type flash memory according to the second embodiment.

  The cell array block MCA in FIG. 4 includes ixj memory cells, i bit lines BL0 to BL (i-1), j word lines WL0 to WL (j-1), and one source line SL. It consists of.

  Here, i = 1024, j = 512, that is, the cell array block MCA has a 512 word line × 1K bit line configuration, and is composed of eight sub cell array blocks MCAB0 to MCAB7 each having a bit capacity of 8K bytes. Each of the sub-cell array blocks MCAB0 to MCAB7 shares 1024 bit lines BL0 to BL (i-1) and one source line SL.

  The row decoder array RDA is composed of eight row decoder blocks RDB0 to RDB7 provided corresponding to the eight sub cell array blocks MCAB0 to MCAB7.

  Each of the row decoder blocks RDB0 to RDB7 has 8 row decoders RD, and the row decoder array has 64 row decoders RD as a whole, and each row decoder RD has predecoder signals GAm, GBn, VCGl. (M = 0 to 7, n = 0 to 7, l = 0-7) is decoded.

  FIG. 5 representatively shows one of the row decoders RD in FIG. 4, a NAND gate NA to which predecoder signals GAm and GBn are input, a level shifter LS to which an output of the NAND gate NA is input, The level shifter LS has eight word line drivers WLD0 to WLD7 to which the output of the level shifter LS is inputted, and a signal VCGl (l = 0-7) is applied as a word line driver voltage source.

  In this row decoder RD, the first stage NMOS input type CMOS differential circuit of the level shifter LS is connected between a VSW node (for example, VSW = 3V) and a ground node, and the next stage PMOS input type CMOS differential circuit. The circuit is connected between a VSW node and a VBB node (negative voltage of VBB = −7.5V), and the word line drivers WLD0 to WLD7 are connected between the word line driver voltage source (VCGl) and the ground node. It is connected.

  This row decoder RD generates drive signals for the eight word lines WLmnl (l = 0-7) based on the predecoder signals GAm, GBn, VCGl. The entire row decoder array has m, n, l. Depending on the combination, it is possible to selectively generate drive signals for 512 word lines WLmnl.

  In this case, at the time of erasing, VBB is supplied as the word line driver voltage source signal VCGl as will be described later, and the output potential of each row decoder RD of the selected row decoder block selected by the predecoder signals GAm and GBn becomes VBB. The output potential of each row decoder RD of the unselected row decoder block that has not been selected is 0V.

  FIG. 6A shows an example of a VCGl predecoder circuit that generates the predecoder signal VCGl in FIG.

  This VCGl predecoder circuit includes a NAND gate NA to which RA0 to RA2, / RA0 to / RA2 which are part of complementary internal row address signals RA0 to RA8, / RA0 to / RA8 and an erase mode signal / ERA are input. The level shifter LS receives the output of the NAND gate NA and the CMOS inverter (driver) IV receives the output of the level shifter LS.

  In this VCGl predecoder circuit, the level shifter LS is the same as the level shifter LS in FIG. 6, and the CMOS inverter IV is connected between the VSW node and the VBB node.

  This VCGl predecoder circuit decodes RA0 to RA2 and / RA0 to / RA2 to decode the predecoder signal VCGl when the erase mode signal / ERA is inactive ("H" level) (during read / write). Output. In contrast, when the erase mode signal / ERA is in the active state ("L" level), VBB is output as the predecoder signal VCGl.

  FIG. 6B shows an example of a GAm predecoder circuit for generating the predecoder signal GAm in FIG.

  This GAm predecoder circuit includes a NAND gate NA1 to which complementary internal row address signals RA3 to RA5, / RA3 to / RA5 are input, a NAND gate NA2 to which an output of the NAND gate NA1 and an erase mode signal / ERA are input. Have

  This GAm predecoder circuit decodes RA3 to RA5 and / RA3 to / RA5 to decode the predecoder signal GAm when the erase mode signal / ERA is inactive ("H" level) (during read / write). Output. On the other hand, when the erase mode signal / ERA is in the active state ("L" level), the "H" level is output as the predecoder signal GAm.

  FIG. 6C shows an example of a GBn predecoder circuit for generating the predecoder signal GBn in FIG.

  This GBn predecoder circuit has a NAND gate NA3 to which complementary internal row address signals RA6 to RA8, / RA6 to / RA8 are input, and an inverter IV1 to which the output of this NAND gate NA3 is input.

  This GBn predecoder circuit decodes RA6 to RA8, / RA6 to / RA8 and outputs a predecoder signal GBn. In this case, at the time of erasure, since the 3-bit binary signal generated by the binary counter circuit in the chip is supplied as the signals RA6 to RA8 and / RA6 to / RA8 as described later, the predecoder signal GBn is It functions as a row decoder block selection signal for alternatively selecting eight row decoder blocks RDB0 to RDB7.

  FIG. 7A representatively shows one circuit for generating internal row address signals RA0 to RA5, / RA0 to / RA5 in FIGS. 6A and 6B.

  In this circuit, the address signal Ai (i = 0 to 5) is changed to RAi (i = 0 to 5) through the two-stage inverters IV2 and IV3, and is further inverted by the inverter IV4, / RAi (i = 0 to 5). )become.

  FIG. 7B representatively shows one circuit for generating internal row address signals RA6 to RA8 and / RA6 to / RA8 in FIG. 6C.

  This circuit includes a CMOS transfer gate TG1 to which an address signal Ai (i = 6, 7, 8) is input at one end, a CMOS transfer gate TG2 to which a clock signal ECLKi (i = 6, 7, 8) is input at one end, And an inverter IV5 connected to a collective connection node at each other end of the two transfer gates. The two transfer gates TG1 and TG2 are complementarily switched by complementary erase mode signals ERA and / ERA. Is done.

  In this circuit, when the complementary erase mode signals ERA, / ERA are inactive (read / write), one transfer gate TG1 is turned on, and Ai and its inverted signal are RAi, / RAi and Output.

  On the other hand, when the complementary erase mode signals ERA and / ERA are in the active state, the other transfer gate TG2 is turned on and the clock signal ECLKi and its inverted signal are output as RAi and / RAi.

  FIG. 7C shows a binary counter BC that supplies the clock signal ECLKi (i = 6, 7, 8) in FIG. 7B.

  The binary counter BC divides the clock signal ECLK6 to generate clock signals ECLK7 and ECLK8.

  FIG. 8 shows an example of signal waveforms related to the erase operation of the cell array block MCA in the NOR flash memory of the second embodiment shown in FIG.

  When the erase mode is entered, the GAm predecoder circuit of FIG. 6 (b) outputs the "H" level as the predecoder signal GAm, and the GBn predecoder circuits of FIG. 6 (c) have RA6 to RA8, / RA6 to / RA. A signal GBn (a scanning signal that alternatively becomes "H" level) is output by predecoding the 3-bit binary signal supplied as the RA8 input. Therefore, the eight row decoder blocks RDB0 to RDB7 are alternatively selected serially by the predecoder signal GAm and the predecoded signal GBn.

  In the erase mode, the VCGl predecoder circuit shown in FIG. 6A supplies VBB as the word line voltage source signal VCGl. Therefore, each row decoder of one selected row decoder block among the row decoder blocks RDB0 to RDB7. The output of RD becomes VBB, and the output of each row decoder RD of the remaining non-selected row decoder blocks becomes the non-selection potential (0 V).

  The source line voltage VSL supplied from the erase voltage booster circuit (not shown) is set to 6.5 V from the start to the end of the erase operation. As a result, the sub-cell array blocks MCABO to MCAB7 are erased serially.

  That is, first, all the word lines (first word line block) of the first sub-cell array block MCABO are set to -7.5V, and all the word lines of the other sub-cell array blocks MCAB1 to MCAB7 are set to 0V. . Such an operation is repeated serially up to the word line (eighth word line block) of the eighth sub-cell array block MCB7, and the erase operation is completed.

  In this case, as can be seen from the erasing characteristics shown in FIG. 31, when the time T1 for setting one word line block to -7.5 V is 10 ms, the total erasing time is 80 ms (10 ms × 8).

  Further, the waveform of the supply current ISL of the booster circuit for erasing voltage for biasing the source line SL can be dispersed into eight peaks corresponding to the serial erasing operation of the eight sub-cell array blocks MCAB0 to MCAB7. The area required for the circuit can be reduced.

  In general terms, the second embodiment is expanded, and when erasing data of a 512 Kbit cell array block, the row decoder and the plurality of word lines are respectively connected to the first to Nth (≧ 2) row decoder blocks and the first. Erasing means for dividing data into 1 to Nth word line blocks, selecting the first to Nth word line blocks individually, and erasing data by time division into first to Nth erase operations. The erasing unit outputs a predecode signal so as to select all the row decoders in the selected row decoder block corresponding to the selected word line block selected from the first to Nth word line blocks. The selection logic is set so that the potentials of all the word lines in the selected word line block are the first negative voltage with respect to the source line potential, and the selected row decoder block is The predecode signal is set to a non-selection logic so that all the row decoders in the non-selected row decoder block are in a non-selected state, and the potentials of all the word lines in the non-selected word line block except the selected word line block are set. The second voltage having an absolute value smaller than the first negative voltage with respect to the source line potential is set.

<Third embodiment>
The configuration of the third embodiment is substantially the same as that of the second embodiment shown in FIGS. 4 to 8, but the signal waveform application sequence related to the erase operation is different.

  FIG. 9 shows an example of signal waveforms related to the erase operation of the cell array block MCA according to the third embodiment.

  In the first half of the erasing operation, the sub-cell array blocks MCB0 to MCB7 are divided into four sections each having two blocks, and each section is selected serially according to the erasing operation shown in FIG. In this case, the time for setting the selected word line block to −10 V is controlled to be T2 (for example, 2 ms) shorter than T1 (= 10 ms) in FIG.

  Then, after the serial selection as described above proceeds to the word line block of the last section, the word line blocks of all sections are selected, that is, all word lines of the 512K bit cell array are set to -10V. In this case, as can be seen from the erase characteristic of FIG. 4, the time T3 for setting all the word lines to -10 V may be 8 ms.

  Therefore, the total erase time is 2 ms × 4 + 8 ms = 16 ms, which is significantly shorter than the total erase time of 80 ms required for the erase operation shown in FIG.

  Further, the waveform of the supply current ISL of the erase voltage booster circuit for biasing the source line is distributed in five peaks corresponding to the serial erase operation of the sub-cell array blocks in each section and the erase operation of the sub-cell array blocks in all sections. Therefore, it is possible to reduce the area necessary for the erase voltage booster circuit.

  In general terms, the third embodiment can be expanded to erase the row decoder and the plurality of word lines in the first to Nth (≧ 2) row decoder blocks and the first row decoder block when erasing data of the 512 Kbit cell array block. 1 to Nth word line blocks are divided into N, the first to Nth word line blocks are individually selected, and data are erased by time division into first to Nth erase operations, and then all Erasing means for simultaneously erasing the data of the word line blocks, wherein the erasing means erases data of selected word line blocks individually selected from the first to Nth word line blocks. The selected word with the predecode signal as the selection logic so as to select all the row decoders in the selected row decoder block corresponding to the selected word line block. The potentials of all the word lines in the block are set to the first negative voltage with respect to the source line potential, and all the row decoders in the non-selected row decoder block except the selected row decoder block are set in a non-selected state. The predecode signal is set to the non-selection logic, and the potentials of all the word lines in the non-selected word line block except the selected word line block are set to the second voltage having an absolute value smaller than the first negative voltage with respect to the source line potential. When setting and erasing data for all the word line blocks at the same time, all the word lines are set with the predecode signal as a selection logic so as to select all the row decoders in all the row decoder blocks. The potential of all word lines in the block is set to a first negative voltage with respect to the source line potential.

<Fourth embodiment>
FIG. 10 shows a cell array block MCA and a corresponding row decoder array of the NOR type flash memory according to the fourth embodiment.

  In this NOR type flash memory, a cell array block MCA having a bit capacity of 512 Kbits (64 Kbytes) is divided into two sub-cell array blocks MCAB1 and MCAB2 each having a bit capacity of 32 Kbytes.

  Each of the sub-cell array blocks MCAB1 and MCAB2 shares 1024 bit lines BL0 to BL (i-1), and the sub-cell array block MCAB1 is connected to 256 word lines WL0 to WL (j-1) in the word line direction. The sub cell array block MCAB2 has 256 word lines WLj to WL (2j-1) and one source line SL2 provided along the word line direction. Have

  The row decoder blocks RDB1 and RDB2 are divided into two row decoder blocks RDB1 and RDB2 corresponding to the two sub-cell array blocks MCAB1 and MCAB2, and each of the row decoder blocks RDB1 and RDB2 has 32 row decoders RD. The entire array has 64 row decoders RD.

  FIG. 11 shows an example of signal waveforms related to the erase operation of the cell array block MCA in FIG.

  When the erase mode is entered, the sub-cell array blocks MCAB1 and MCAB2 are serially selected, and a bias (for example, 6.5 V) is applied to the source lines SL1 and SL2 by T1 (= 10 ms) time, and all words from the erase start to the end Apply -10V to the wire. As a result, the sub-cell array blocks MCAB1 and MCAB2 are erased serially.

  Therefore, the total erase time required for the erase operation is 20 ms, and the waveform of the supply current ISL of the booster circuit for erase voltage for biasing the source lines SL1 and SL2 can be distributed into two peaks, so that the maximum supply current is 2 mA. The booster circuit can be used, and the area required for the erase voltage booster circuit can be reduced.

  FIG. 12 is a circuit showing an example of a source decoder for selecting the two source lines SL1 and SL2 in FIG.

  Complementary internal row address signals RA8 and / RA8 generated from the most significant bit signal of the row address signals respectively correspond to one input of two-input NAND gates NA11 and NA12, and block address signal BLKADD. Is the other input of the NAND gates NA11 and NA12.

  The output of the NAND gate NA11 is inverted by the inverters IV11 and IV12 and input to the source line driver SD1 as a complementary signal. The output of the NAND gate NA12 is inverted by the inverters IV13 and IV14 and input to the source line driver SD2 as a complementary signal. The source line drivers SD1 and SD2 are each composed of a CMOS latch circuit connected between a source line voltage VSW node and a Vss node.

  The operation of the source decoder is as follows. At the time of erasing, the block address signal BLKADD becomes “H” level, and the source line of the sub-cell array block MCAB1 is driven by the “H” level of one of the complementary internal row address signals RA8 and / RA8. Either SL1 or the source line SL2 of the sub-cell array block MCB2 becomes the source line voltage VSW. During one erase operation, the signals RA8 and / RA8 are inverted, and the source lines SL1 and SL2 are serially selected to become the source line voltage VSW.

  Note that the block address signal BLKADD becomes “L” level during non-selection or during operations other than erasing, and the two source lines SL1 and SL2 become 0V.

  In general terms, the fourth embodiment is expanded to divide a source line into first to Nth (≧ 2) source lines and erase a row decoder when erasing data of a 512 Kbit cell array block. The plurality of word lines are divided into first to Nth row decoder blocks and first to Nth word line blocks, respectively, and data is erased by time division into a first erase operation to an Nth erase operation. An erasing unit is provided, wherein the erasing unit sets all word lines to a predetermined potential, and selects a potential of a selected source line individually selected from the first to Nth source lines as a potential of the word line. And the potential of the non-selected source lines excluding the selected source line is set to a second voltage having an absolute value smaller than the first positive voltage with respect to the potential of the word line. Special It is an.

<Fifth embodiment>
FIG. 13 shows a cell array block MCA and a corresponding row decoder RDA of the NOR type flash memory according to the fifth embodiment.

  In this NOR type flash memory, a cell array block having a bit capacity of 512 Kbits (64 Kbytes) is divided into two sub-cell array blocks MCAB1 and MCAB2 each having a bit capacity of 32 Kbytes.

  Each of the sub-cell array blocks MCAB1 and MCAB2 shares 512 word lines WL0 to WL (j-1), and the sub-cell array block MCAB1 extends along the bit line direction with 256 bit lines BL0 to BL (i-1). The sub cell array block MCAB2 includes 256 bit lines BLi to BL (2i-1) and one source line SL2 provided along the bit line direction. Have.

  FIG. 14 shows an example of signal waveforms related to the erase operation of the cell array block MCA in FIG.

  When the erase mode is entered, the sub-cell array blocks MCAB1 and MCAB2 are first selected serially, and a bias (for example, 6.5 V) is applied to the source lines SL1 and SL2 by T2 (<T1) time, thereby reducing the interband current. After that, a bias is simultaneously applied to the source lines SL1 and SL2 for T3 time, and -10V is applied to all word lines from the start to the end of erasing.

  In this case, when an erasing voltage boosting circuit with a maximum supply current of 2 mA is provided, as can be seen from the characteristics shown in FIG. 31, T2 = 2 ms and T3 = 8 ms can be obtained.

  As a result, the total erase time of the sub-cell array blocks MCAB1 and MCAB2 is 2 ms × 2 + 8 ms = 12 ms, which is significantly shorter than the total erase time 20 ms required for the erase operation shown in FIG.

  The waveform of the supply current ISL of the erase voltage booster circuit for biasing the source lines SL1 and SL2 has three waveforms corresponding to the serial erase operation of the sub-cell array blocks in each section and the erase operation of the sub-cell array blocks in all sections. Since it can be dispersed in the peak, it is possible to reduce the area required for the boosting circuit for erasing voltage.

  FIG. 15 is a circuit showing an example of a source decoder for selecting the two source lines SL1 and SL2 in FIG.

  Complementary internal column address signals CA9 and / CA9 generated from the most significant bit signal of the column address signals respectively correspond to one input of two-input NAND gates NA1 and NA2, and block address signal BLKADD. Is the other input of the NAND gates NA11 and NA12. The output of the NAND gate NA11 is inverted by the inverters IV11 and IV12 and input to the source line driver SD1 as a complementary signal. The output of the NAND gate NA12 is inverted by the inverters IV13 and IV14 and input to the source line driver SD2 as a complementary signal. The source line drivers SD1 and SD2 are each composed of a CMOS latch circuit connected between a source line voltage VSW node and a Vss node.

  In the operation of the source decoder, at the time of erasing, the block address signal BLKADD becomes “H” level, and the source line SL1 of the sub-cell array block MCAB1 is driven by the “H” level of one of the complementary column address signals CA9 and / CA9. One of the source lines SL2 of the sub-cell array block MCAB2 becomes the source line voltage VSW. During one erase operation, the signals RA8 and / RA8 are inverted, and the source lines SL1 and SL2 are serially selected to become the source line voltage VSW.

  Note that the block address signal BLKADD becomes “L” level during non-selection or during operations other than erasing, and the two source lines SL1 and SL2 become 0V.

  When the fifth embodiment is expanded and generally expressed, when erasing data of a 512 Kbit cell array block, the source line is divided into first to Nth (≧ 2) multiple source lines. Erasing means for individually erasing data in all the memory cells after individually erasing data by time-sharing the first to Nth erasing operations by individually selecting the Nth to Nth source lines, The erasing means selects all the word lines using the predecode signal as a selection logic so that all row decoders are selected when erasing data by individually selecting from the first to Nth source lines. The line is set to a predetermined potential, the potential of the selected source line individually selected from the first to Nth source lines is set to a first positive voltage with respect to the potential of the word line, and the selected source Unselected source lines excluding lines When the potential is set to a second voltage whose absolute value is smaller than the first positive voltage with respect to the potential of the word line, and all the memory cells are erased simultaneously, all the word lines are set to a predetermined voltage. The potentials of all the source lines are set to the first positive voltage with respect to the potentials of the word lines while being set to the potentials.

  In the fourth embodiment, the erase operation using the signal waveforms shown in FIG. 14 is also possible in the cell array block and row decoder array shown in FIG.

  In the fifth embodiment, the erase operation using the signal waveforms shown in FIG. 11 is also possible in the cell array block and row decoder array shown in FIG.

<Sixth embodiment>
FIG. 16 shows a cell array block MCA of a NOR flash memory according to the sixth embodiment and a corresponding row decoder array.

  In this NOR type flash memory, a cell array block having a bit capacity of 512 Kbits (64 Kbytes) is divided into four sub-cell array blocks MCAB1, MCAB2, MCAB3, and MCAB4 each having a bit capacity of 16 Kbytes.

  The two sub cell array blocks MCAB1 and MCAB2 arranged in the direction of the first column share 256 bit lines BL0 to BL (i-1) and one source line SL1, and are arranged in the direction of the second column. The sub cell array blocks MCA B3 and MCA B4 share 256 bit lines BLi to BL (2i-1) and one source line SL2.

  The two sub cell array blocks MCAB1 and MCAB3 arranged in the direction of the first row share 256 word lines WL0 to WL (j-1) and are arranged in the direction of the second row. MCAB2 and MCAB4 share 256 word lines WLj to WL (2j-1).

  The row decoder array is divided into two row decoder blocks RDB1, RDB2 corresponding to the sub-cell array blocks (MCAB1, MCAB3), (MCAB2, MCAB4) of the two rows, and each row decoder block RDB1, Each RDB2 has 256 row decoders RD, and is selected or not selected by block selection signals R0 and R1 at the time of erasing.

  FIG. 17 shows an example of signal waveforms related to the erase operation of the cell array block MCA in FIG.

  When the erase mode is entered, first, the sub-cell array block (MCAB1, MCAB3) in the first row is selected and -10V is applied to the word lines WL0-WL (j-1). In this state, the source lines SL1, SL2 are applied. Are serially selected every T1 time, a bias (for example, 6.5 V) is applied to the selected source line, and 0 V is applied to the non-selected source line. During this time, 0 V is applied to the unselected word lines WLj to WL (2j-1).

  Next, the sub-cell array block (MCAB2, MCAB4) in the second row is selected and -10V is applied to the word lines WLj to WL (2j-1). In this state, the source lines SL1 and SL2 are serially connected to the T1 time. Each is selected, a bias (for example, 6.5 V) is applied to the selected source line, and 0 V is applied to the unselected source line. During this time, 0 V is applied to the unselected word lines WL0 to WL (j-1).

  As a result, the sub-cell array blocks MCAB1, MCAB3, MCAB2, and MCAB4 are serially erased.

  Therefore, the total erase time required for the erase operation is 40 ms, and the waveform of the supply current ISL of the booster circuit for erase voltage for biasing the source lines SL1 and SL2 can be dispersed into four peaks. The booster circuit can be used, and the area required for the erase voltage booster circuit can be reduced.

  In general terms, the sixth embodiment is expanded to divide a word line into a plurality of first to Mth (≧ 2) word line blocks and a source line when erasing data of a 512 Kbit cell array block. Is divided into a plurality of first to Nth (≧ 2) source lines and depends on a combination of individual selection of the first to Mth word line blocks and individual selection of the first to Nth source lines. Erasing means for individually selecting the (1, 1) to (M, N) blocks and erasing data in a time-sharing manner in the (1, 1) to (M, N) erasing operations. The erasing unit sets all word lines of the selected word line block to the first voltage by using the predecode signal as a selection logic so as to select all the row decoders corresponding to the selected word line block. All unselected word line blocks Is set to a second voltage higher than the first voltage, the selected source line is set to a third voltage higher than the first voltage, and the potential of the unselected source line is set to the third voltage. A lower fourth voltage is set.

<Seventh embodiment>
The seventh embodiment has substantially the same configuration as the sixth embodiment shown in FIGS. 16 and 17, but the signal waveform application sequence related to the erase operation is different.

  FIG. 18 shows an example of signal waveforms related to the erase operation of the cell array block MCA according to the seventh embodiment.

  When the erase mode is entered, first, the source line bias is applied for each time T2 (<T1) in the same sequence as the erase operation of FIG. 17, and after the interband current is reduced, all the time is T3 until the end. -10V is applied to WL0 to WL (j-1) and WLj to WL (2j-1), and a source line bias is applied to all SL1 and SL2.

  In this case, when an erasing voltage boosting circuit having a maximum supply current of 1 mA is provided, as can be seen from the characteristics shown in FIG. 31, T2 = 2 ms and T3 = 8 ms can be obtained.

  As a result, the total erase time of the sub-cell array blocks MCAB1 and MCAB2 is 2 ms × 4 + 8 ms = 16 ms, which is significantly shorter than the total erase time 40 ms required for the erase operation shown in FIG.

  The waveform of the supply current ISL of the erase voltage booster circuit for biasing the source lines SL1 and SL2 has five waveforms corresponding to the serial erase operation of each sub-cell array block and the erase operation of all sub-cell array blocks. Since it can be dispersed in the peak, it is possible to reduce the area required for the boosting circuit for erasing voltage.

  In general terms, the seventh embodiment is expanded to divide a word line into a plurality of first to Mth (≧ 2) word line blocks and source lines when erasing data of a 512 Kbit cell array block. Is divided into a plurality of first to Nth (≧ 2) source lines and depends on a combination of individual selection of the first to Mth word line blocks and individual selection of the first to Nth source lines. The first (1, 1) to (M, N) blocks to be individually selected and data erasing in a time-sharing manner into the (1, 1) to (M, N) erasing operations, Erasing means for erasing data from all memory cells at the same time is provided, and the erasing means erases data by individually selecting the (1, 1) to (M, N) blocks. Select all row decoders corresponding to the selected word line block. The predecode signal is set to the selection logic so as to be in the state, all the word lines of the selected word line block are set to the first voltage, and all the word lines of the unselected word line block are set to the first voltage higher than the first voltage. The selected source line is set to a third voltage higher than the first voltage, the non-selected source line is set to a fourth voltage lower than the third voltage, and all the memories are set. When simultaneously erasing data from a cell, all word lines are set to the first voltage, and all source lines are set to the third voltage.

  Next, features of the present invention relating to a data write test in a NOR flash memory will be described.

  In other words, here, a plurality of cell array blocks are provided, and during normal data writing, data is written into one of the memory cells, or data is simultaneously written into a plurality of memory cells in the same cell array block. Sometimes data is simultaneously written into the memory cells of a plurality of cell array blocks.

<Eighth embodiment>
FIG. 19 shows an example of a NOR type flash memory according to the eighth embodiment.

  The memory core section includes two cell array blocks MCAB0 and MCAB1 in which memory cells are arranged, and word line selection row decoders RD0 and RD1 provided corresponding to the cell array blocks MCA0 and MCA1, and the cell array blocks MCA0 and MCA1. Bit line selection column gates CG0 and CG1 provided corresponding to the above.

  The cell array block MCA0 representatively shows one word line WL0 and one bit line BL0 for simplicity of illustration, and the cell array block MCA1 has one word line WL1 and one bit line BL0. Bit line BL1 is representatively shown.

  The block address decoder BAD decodes the block address signal input from the address pin An and outputs block selection signals BA0 and BA1.

  The well drivers WD0 and WD1 are activated and controlled by the block selection signals BA0 and BA1, and apply required voltages to the P-type well wirings Well0 and Well1 of the cell array blocks MCAB0 and MCAB1.

  The row address decoder RAD decodes a row address signal input from the address pin An to control a row decoder selection signal for controlling the activation / deactivation state of the row decoders RD0 and RD1. RA0 and RA1 are output.

  When the row decoders RD0 and RD1 are activated, they drive specific word lines of the cell array blocks MCA0 and MCA1 in response to a row address signal.

  The row decoders RD0 and RD1 are controlled not only by the row decoder selection signals RA0 and RA1, but also by the block selection signals BA0 and BA1 to be activated / deactivated (disabled). It may be configured.

  The column address decoder CAD decodes a column address signal input from the address pin An and outputs a column selection signal CA for controlling selection / non-selection of a specific column of the column gates CG0 and CG1.

  The column gates CG0 and CG1 are correspondingly activated (enabled) and deactivated (disabled) by the block selection signals BA0 and BA1, and the cell array blocks MCAB0, CG1 and CG1 are controlled according to the column selection signal CA. A bit line of a specific column of MCAB1 is selected.

  The data line DL is commonly connected to the column gates CG0 and CG1, and is connected to the bit lines of the cell array blocks MCA0 and MCA1 through the column gates CG0 and CG1.

  The sense amplifier SA senses and amplifies a voltage depending on the cell data read from the memory cell selected at the time of data reading to the data line DL.

  The input / output buffer IOB outputs the output data of the sense amplifier SA from the input / output pin IO to the outside.

  The write load circuit PGML is controlled by the write data input from the input / output pin IO at the time of data writing, and biases the data line DL to 5V at the time of writing "0", and the data line DL to 0V at the time of writing "1". It is.

  The command control circuit CMD designates each operation mode such as write / erase / read by the input of the control pin CTL and the input / output pin IO pin, and outputs a mode control signal to the row address decoder RAD and the column address decoder CAD. To do.

  The write high voltage switching circuit SW selects the boost output of the write booster circuit WB during normal writing, and selects the write high voltage applied from the outside to the write test external terminal TEST during the write test, to the required internal circuit. To supply.

  FIG. 20 schematically shows an example of the two cell array blocks MCA0 and MCA1 and two column gates (column selection transistor and block selection transistor) in FIG.

  Here, for simplification of illustration, the cell array block MCA0 includes two cells in the same row, a word line WL0 that is commonly connected to each control gate of the cells in the same row, and a bit that is commonly connected to cells in the same column. A line is representatively shown, and a cell 0 is assigned to one cell in a column, and a bit line BL0 is assigned to a bit line.

  The column gate corresponding to the cell array block MCA0 representatively shows two columns selected by the column selection signals Y0 and Yn. Each column is in series with the bit line and includes a column selection transistor CS and a block selection signal. A block selection transistor BS selected by BA0 is connected.

  Similarly, the cell array block MCA1 representatively shows two cells in the same row, a word line WL1 commonly connected to each control gate of the cells in the same row, and a bit line commonly connected to cells in the same column. One cell of a column is labeled Cell1 and the bit line is labeled BL1.

  The column gate corresponding to the cell array block MCA1 representatively shows two columns selected by the column selection signals Y0 and Yn. Each column is in series with the bit line and includes a column selection transistor CS and a block selection signal. A block selection transistor BS selected by BA1 is connected.

  FIG. 21 shows a row main decoder RMD provided to select and control two row decoders RD0 and RD1 in the circuit of FIG. 19, two cell array blocks MCA0 and MCA1, and two column gates (column selection transistors and blocks). An example of select transistors CG0 and CG1 is schematically shown.

  Here, for simplification of illustration, the cell array block MCAB0 typically includes cells Cell0 for one row and column, one WL0 of word lines (sub-word lines), and one BL0 of bit lines. Show.

  The column gate CG0 representatively shows the column selection transistor CS and the block selection transistor BS connected in series to the bit line BL0.

  The row decoder RD0 is inserted and connected correspondingly to one block selection signal line (column gate selection signal line) BA0 and the block selection signal line BA0 and each sub word line of the cell array block MCA0. A CMOS transfer gate (typically only one) TG and a noise canceller NMOS transistor NT inserted correspondingly between each sub-word line of the cell array block MCA0 and the ground node. Have.

  Similarly, the cell array block MCAB1 representatively shows one row, one column of cells Cell1, one word line (subword line) WL1, and one bit line BL1.

  The column gate CG1 representatively shows the column selection transistor CS and the block selection transistor BS connected in series to the bit line BL1.

  The row decoder RD1 is inserted and connected correspondingly to one block selection signal line (column gate selection signal line) BA1 and the block selection signal line BA1 and each word line of the cell array block MCA1. A CMOS transfer gate (typically only one) TG, and a noise canceller NMOS transistor NT inserted correspondingly between each sub-word line of the cell array block MCABO and the ground node. Have.

  The row main decoder RMD decodes the 2-bit internal row address signals RAi and RAj, and outputs the corresponding sub word lines in the two cell array blocks MCA0 and MCA1 according to the decoded output (complementary row main decode signals Mij and / Mij). The CMOS transfer gate TG inserted and connected to the memory cell is selectively controlled, and a noise canceller NMOS transistor NT connected to each of the sub-word lines of the two cell array blocks MCA0 and MCA1 is selected by one row main decode signal / Mij. Drive control.

  In the NOR flash memory of the eighth embodiment, one or a plurality of cells in one cell array block MCA0 or MCA1 are simultaneously selected when reading / writing / erasing data, and the two Control is performed to simultaneously select one or more of the cells in the cell array blocks MCA0 and MCA1.

  FIG. 22 shows an example of a signal waveform related to a normal write operation / write test operation among the operations of the circuit of FIG.

  In the normal write operation of the NOR flash memory according to the eighth embodiment, one of the block address signals BA0 and BA1 is controlled and the other is controlled to be in a non-selected state. As a result, the cells in one block in the selected state are selected, and the cells in the other block in the non-selected state are all in the non-selected state.

  That is, during normal writing, for example, when the cell Cell0 of the cell array block MCA0 is a cell to be written, the block selection signal BA0 is activated ("H") to select the cell array block MCA0. The other block selection signal BA1 becomes inactive ("L").

  In order to select the gate of the cell Cell0, the signal M00 corresponding to the sub word lines WL0 and WL1 among the row main decode signals Mij is "H", but the other signals Mij are "L". . In this case, the sub word line WL0 is selected because the block selection signal BA0 is "H", but the sub word line WL1 is not selected because the block selection signal BA1 is "L".

  In order to select the drain of the cell Cell0, the signal Y0 corresponding to the bit line BL0 among the column selection signals is activated ("H"), but other signals are inactivated ("" L ").

  That is, among the bit lines (BL0, BL1 in this example) of the same column address of the two cell array blocks MCAB0, MCAB1, the bit line BL0 of the cell array block MCA0 is selected by the block selection signal BA0 and the column selection signal Y0. Although connected to DL, the bit line BL1 of the cell array block MCA1 is not selected.

  Therefore, since the drain of the selected cell Cell0 connected to the selected bit line BL0 in the cell array block MCA0 is biased by the write load circuit PGML and the gate (sub word line WL0) is selected, data can be written. .

  On the other hand, in the write test, the block selection signals BA0 and BA1 are selected, the row decoders RD0 and RD1 are activated by the row decoder selection signals RA0 and RA1, respectively, and the cell array blocks MCA0 and MCA1 corresponding to the row address signal. Are selected in the same row (in this example, WL0, WL1).

  The bit lines (BL0 and BL1 in this example) of the two cell array blocks MCA0 and MCA1 are selected by the block selection signal BA0 and the column selection signal Y0 and also by the block selection signal BA1 and the column selection signal Y0. Each is selected and connected to a data line DL.

  Therefore, the drains of the selected cells Cell0 and Cell1 connected to the selected bit lines BL0 and BL1 in the cell array blocks MCA0 and MCA1 are biased by the write load circuit PGML and the gates (sub-word lines WL0 and WL1) are selected. So you can write the test data at the same time.

  At this time, 0 V is supplied from the well drivers WD0 and WD1 to the well wiring Well0 and Well1 (source line and well line) for each array block MCAB0 and MCAB1, so that the source line potential floats and the well potential floats. There is no problem.

  As a result, the number of bits that can be simultaneously written can be increased as compared with the conventional case, so that the write test time can be reduced in inverse proportion to the number of blocks. Therefore, it is possible to suppress an increase in the write test time that becomes more noticeable in a large-capacity memory.

  FIG. 23 shows the relationship between the number of simultaneously written bits and the critical source line voltage Vc in the NOR type flash memory according to the eighth embodiment by a solid line. For comparison, the number of simultaneously written bits in the conventional NOR type flash memory is shown in FIG. The relationship with the critical source line voltage Vc is indicated by a dotted line.

  As can be seen from FIG. 23, according to the NOR type flash memory of the eighth embodiment, the number of cell array blocks of memory cells to be simultaneously written is increased by a plurality (N) times. The number of bits B can be increased to N times, and the write test time can be shortened.

  In addition to increasing the number of simultaneous write bits in a single block, a plurality of blocks are simultaneously selected (in this case, the block selection signals BA0 and BA1 are set to “H”), whereby the critical source line voltage Vc is set. The number of simultaneous write bits reached can be increased by a factor of the number of blocks.

  Although the eighth embodiment has been described by taking the NOR type flash memory as an example, it is also effective for a multi-value memory in which the test time becomes more important and a logic device in which these nonvolatile memories are mounted. Further, it is possible to perform simultaneous writing to a plurality of cell array blocks in a normal write operation without being limited to the write test operation.

The figure which shows an example of the waveform of the write-control pulse signal of the NOR type flash memory which concerns on 1st Example. FIG. 2 is a circuit diagram showing an example of a write control pulse generation circuit for generating a write control pulse signal in the sequence shown in FIG. 1. FIG. 2 is a circuit diagram showing an example of a write control pulse generation circuit for generating a write control pulse signal in the sequence shown in FIG. 1. The block diagram which shows an example of a structure of one cell array block and the row decoder corresponding to it in the NOR type flash memory which concerns on 2nd Example. The figure which shows an example for one of the row decoders which comprise the row decoder block in FIG. FIG. 6 is a diagram showing an example of a VCGl predecoder circuit, a GAm predecoder circuit, and a GBn predecoder circuit for supplying a predecode signal to the row decoder RD of FIG. 5. FIG. 7 is a diagram showing a binary counter circuit for supplying a clock signal related to one circuit for generating an internal row address signal, one circuit for generating an internal row address signal in FIG. FIG. 5 is a diagram showing an example of signal waveforms related to an erase operation of a cell array block in the NOR flash memory shown in FIG. 4. The figure which shows an example of the signal waveform which concerns on the erase operation of the cell array block concerning 3rd Example. The figure which shows the cell array block of the NOR type flash memory which concerns on 4th Example, and the row decoder array corresponding to it. FIG. 11 is a diagram showing an example of signal waveforms related to the erase operation of the cell array block in FIG. 10. FIG. 11 is a circuit diagram showing an example of a source decoder for selecting two source lines in FIG. 10. The figure which shows the cell array block of the NOR type flash memory which concerns on 5th Example, and the row decoder array corresponding to it. FIG. 14 is a diagram showing another example of signal waveforms related to the erase operation of the cell array block in FIG. 13. FIG. 14 is a circuit diagram showing an example of a source decoder for selecting two source lines in FIG. 13. The figure which shows the cell array block of the NOR type flash memory which concerns on 6th Example, and the row decoder array corresponding to it. FIG. 17 is a diagram showing an example of signal waveforms related to the erase operation of the cell array block in FIG. 16. The figure which shows an example of the signal waveform which concerns on the erase operation of the cell array block concerning 7th Example. The figure which shows an example of the NOR type flash memory which concerns on 8th Example. FIG. 20 is a circuit diagram schematically showing an example of two cell array blocks and two column gates in FIG. 19. FIG. 20 is a circuit diagram illustrating an example of a connection relationship among the row decoder, the cell array block, and the column gate in FIG. 19. FIG. 22 is a diagram showing an example of signal waveforms related to a normal write operation / write test operation among the operations of the circuit of FIG. 21. The figure which shows the relationship between the simultaneous write bit number and critical source line voltage in the NOR type flash memory which concerns on 8th Example. The figure which shows schematically a plane pattern and sectional structure about an example of the memory cell single-piece | unit of NOR type flash memory. FIG. 25 is a diagram showing an example of a memory cell array in which a plurality of memory cells shown in FIG. 24 are arranged in a matrix. 2 is a diagram showing a part of a peripheral circuit related to a part of a cell array block in a NOR type flash memory having a multi-bit configuration. FIG. The figure which shows the write time versus threshold voltage change characteristic of the memory cell in the NOR type flash memory. The figure which shows the write time vs. write current (drain current) change characteristic of the memory cell in a NOR type flash memory. The figure which shows an example of the write signal waveform considered as a method of reducing the area and current consumption of the booster circuit for write voltage. The figure which shows the erase time versus threshold voltage change characteristic of the memory cell in NOR type flash memory. The figure which shows the erase time versus erase current (source current) change characteristic of the memory cell in the NOR type flash memory. The figure which shows schematically an example of the circuit structure of the cell array block in the conventional NOR type flash memory.

Explanation of symbols

BLi ... bit line, CS ... column selection transistor, CT ... bit line potential clamping transistor, DL ... data line, LT ... bit line load transistor, SA ... sense amplifier, WT ... write transistor.

Claims (2)

A memory core unit having a plurality of cell array blocks each including a plurality of nonvolatile memory cells, a plurality of word lines, and a plurality of bit lines;
A nonvolatile semiconductor memory comprising: means for simultaneously erasing data from a plurality of memory cells in one cell array block and simultaneously writing data to the plurality of memory cells in the plurality of cell array blocks. A memory core unit having a plurality of cell array blocks each including a plurality of nonvolatile memory cells, a plurality of word lines, and a plurality of bit lines;
A column address decoder for designating a column address of the cell array block;
A block address decoder for designating an address of the cell array block;
A write load circuit that outputs a voltage corresponding to the write data when writing data; and
A row decoder for selecting the word line;
The bit line is selected by the column address and the block address,
The nonvolatile semiconductor memory, wherein the plurality of cell array blocks are simultaneously selected by the block address decoder, and data is written by supplying the voltage output from the write load circuit to the plurality of bit lines.

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