JP2006309179A - Display, array substrate, and method of driving display - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display which supplies a current signal as a video signal, in which reproducibility of a low gray level is enhanced. <P>SOLUTION: The display includes a driving control element DR including a control terminal, a first terminal connected to a power supply terminal ND1, and a second terminal outputting the current of a magnitude corresponding to a voltage therebetween, a display element OLED including a first electrode, a second electrode connected to a power supply terminal ND2, and an active layer interposed therebetween, a switch SWa connected between the second terminal and the first electrode, switch groups SWb, SWc capable of switching between a state that the second terminal, the controller terminal and a video signal line DL are interconnected, capacitors C1 to C3, and switches SWd1 and SWd3. The switch SWd1 and the capacitor C1, and the switch SWd2 and the capacitor C2 are connected in series in this order between the control element and a constant potential terminal. The switch SWd3 and the capacitor C3 are connected in series between the control terminal and the electrode to which the switch SWd2 of the capacitor is connected. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a display device, an array substrate, and a method for driving the display device.

  In a display device such as an organic electroluminescence (EL) display device in which the optical characteristics of a display element are controlled by a drive current applied to the display element, image quality defects such as luminance unevenness occur when the drive current varies between pixels. Therefore, when the active matrix driving method is adopted in such a display device, it is required that the characteristics of the drive control element for controlling the magnitude of the drive current are substantially the same among the pixels. However, in this display device, since the drive control element is usually formed on an insulator such as a glass substrate, the characteristics are likely to vary.

  Patent Document 1 describes an organic EL display device in which a pixel circuit includes a current mirror circuit.

  This pixel circuit includes an n-channel field effect transistor that is a drive control element, an organic EL element, and a capacitor. The source of the n-channel field effect transistor is connected to a low-potential power line, and the capacitor is connected between the gate of the n-channel field effect transistor and the previous power line. The anode of the organic EL element is connected to a higher potential power line.

This pixel circuit is driven by the following method.
First, the drain and gate of the n-channel field effect transistor are connected, and in this state, a current _Isig having a magnitude corresponding to the video signal is passed between the drain and source of the n-channel field effect transistor. By this operation, the voltage between both electrodes of the capacitor is set to the gate-source voltage necessary for flowing the current _Isig through the channel of the n-channel field effect transistor.

Next, the connection between the drain and gate of the n-channel field effect transistor is disconnected, and the voltage between both electrodes of the capacitor is maintained. Subsequently, the drain of the n-channel field effect transistor is connected to the cathode of the organic EL element. As a result, a drive current I _drv having a magnitude substantially equal to the previous current I _sig flows through the organic EL element. The organic EL element emits light with a luminance corresponding to the magnitude of the drive current I _drv .

As described above, when the above configuration is adopted, the driving current I _drv having a magnitude almost equal to the current I _sig supplied as the video signal in the writing period is applied to the n-channel field effect transistor in the holding period following the writing period. It can flow between the drain and source. Therefore, not only the threshold value V _th of the n-channel field effect transistor but also the influence of mobility and size on the drive current I _drv can be eliminated.

However, the above display device has a problem that it is difficult to write the video signal I _sig corresponding to the small drive current I _drv . Therefore, with this display device, it is difficult to display each gradation in the low gradation range with high reproducibility.
US Pat. No. 6,373,454

  An object of the present invention is to improve reproducibility of low gradation in a display device that supplies a current signal as a video signal to a pixel.

  According to a first aspect of the present invention, a display device includes a plurality of pixels arranged in a matrix and a plurality of video signal lines arranged corresponding to a plurality of columns formed by the plurality of pixels. Each of the plurality of pixels outputs a control terminal, a first terminal connected to the first power supply terminal, and a current having a magnitude corresponding to a voltage between the control terminal and the first terminal. A display element including a drive control element including two terminals, a first electrode, a second electrode connected to a second power supply terminal, and an active layer interposed between the first and second electrodes; An output control switch connected between the second terminal and the first electrode; a first state in which the second terminal, the control terminal and the video signal line are connected to each other; and the second terminal; Switch between the control terminal and the second state where the video signal line is disconnected from each other A possible switch group, first to third capacitors, and first to third switches, wherein the first switch, the first capacitor, the second switch, and the second capacitor are connected to the control terminal; The third switch and the third capacitor are connected in series between the constant potential terminal in this order, and the third switch and the third capacitor are connected in series between the control terminal and the electrode connected to the second switch of the second capacitor. What is being provided.

  According to a second aspect of the present invention, there are provided an array substrate, a plurality of pixel circuits arranged in a matrix, and a plurality of video signal lines arranged corresponding to a plurality of columns formed by the plurality of pixel circuits. And each of the plurality of pixel circuits outputs a control terminal, a first terminal connected to a power supply terminal, and a current having a magnitude corresponding to a voltage between the control terminal and the first terminal. A drive control element including a second terminal; a pixel electrode; an output control switch connected between the second terminal and the pixel electrode; the second terminal; the control terminal; and the video signal line; A switch group that can be switched between a first state in which the second terminal, the control terminal, and the video signal line are disconnected from each other; and first to third capacitors And first to third switches, the first switch The switch, the first capacitor, the second switch, and the second capacitor are connected in series between the control terminal and the constant potential terminal in this order, and the third switch and the third capacitor are the control terminal. And the electrode connected to the second switch of the second capacitor are provided in series.

  According to a third aspect of the present invention, there is provided a method for driving a display device according to the first aspect, wherein a plurality of rows formed by the plurality of pixels are sequentially selected, and a plurality of pixels included in the selected row are selected. A method is provided that includes performing a first and second write operation on each and performing a display operation on each of a plurality of pixels included in a non-selected row.

  According to the present invention, it is possible to improve reproducibility of low gradation in a display device that supplies a current signal as a video signal to a pixel.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, in each figure, the same referential mark is attached | subjected to the component which exhibits the same or similar function, and the overlapping description is abbreviate | omitted.

  FIG. 1 is a plan view schematically showing a display device according to a first aspect of the present invention. FIG. 2 is a cross-sectional view schematically showing an example of a structure that can be employed in the display device of FIG. FIG. 3 is an equivalent circuit diagram of a pixel included in the display device of FIG. In FIG. 2, the display device is drawn such that its display surface, that is, the front surface or the light emitting surface faces downward, and the back surface faces upward.

  This display device is a bottom emission type organic EL display device adopting an active matrix driving method. This organic EL display device includes, for example, an insulating substrate SUB such as a glass substrate.

On the substrate SUB, as shown in FIG. 2, for example, a SiN _x layer and a SiO _x layer are sequentially stacked as the undercoat layer UC.

  On the undercoat layer UC, a plurality of semiconductor layers SC, for example, polysilicon layers are arranged. A source and a drain are formed in each semiconductor layer SC.

  The undercoat layer UC and the semiconductor layer SC are covered with the gate insulating film GI. The gate insulating film GI can be formed using, for example, TEOS (tetraethyl orthosilicate).

  On the gate insulating film GI, the gates G are arranged. The gate G is made of, for example, MoW.

  The semiconductor layer SC, the gate insulating film GI, and the gate G form a top gate type thin film transistor. In this embodiment, these thin film transistors are p-channel thin film transistors, and are used as the drive control element DR and the switches SWa to SWc and SWd1 to SWd5 included in the pixel PX of FIGS.

  On the gate insulating film GI, the lower electrodes of the capacitors C1 to C4 and the scanning signal lines SL1 to SL6 shown in FIGS. 1 and 3 are further arranged. These can be formed in the same process as the gate G.

  As shown in FIG. 1, each of the scanning signal lines SL1 to SL6 extends along the row of the pixels PX, that is, in the X direction, and is arranged in the Y direction along the column direction of the pixels PX. These scanning signal lines SL1 to SL6 are connected to the scanning signal line driver YDR.

The gate insulating film GI, the gate G, the scanning signal lines SL1 to SL6, and the lower electrodes of the capacitors C1 to C4 are covered with an interlayer insulating film II shown in FIG. The interlayer insulating film II is, for example, a SiO _x film formed by a plasma CVD method or the like. A part of the interlayer insulating film II is used as a dielectric layer of the capacitors C1 to C4.

  On the interlayer insulating film II, the upper electrodes of the capacitors C1 to C4 shown in FIGS. 1 and 3, the source electrode SE and the drain electrode DE shown in FIG. 2, the video signal line DL and the power source shown in FIGS. Lines PSL are arranged. These can be formed in the same process and have, for example, a three-layer structure of Mo / Al / Mo.

  The source electrode SE and drain electrode DE are electrically connected to the source and drain of the thin film transistor through contact holes provided in the interlayer insulating film II.

As shown in FIG. 1, each video signal line DL extends in the Y direction and is arranged in the X direction. These video signal lines DL are connected to a video signal line driver XDR.
In the present embodiment, each of the power supply lines PSL extends in the Y direction and is arranged in the X direction.

The source electrode SE, the drain electrode DE, the video signal line DL, the power supply line PSL, and the upper electrodes of the capacitors C1 to C4 are covered with the passivation film PS shown in FIG. The passivation film PS is made of, for example, SiN _x .

  On the passivation film PS, as shown in FIG. 2, the first electrodes PE which are pixel electrodes are arranged. In this aspect, each first electrode PE is a light-transmissive front electrode. Each first electrode is connected to the drain electrode DE through a through hole provided in the passivation film PS, and the drain electrode DE is connected to the drain of the switch SWa.

  The first electrode PE is an anode in this embodiment. As a material of the first electrode PE, for example, a transparent conductive oxide such as ITO (indium tin oxide) can be used.

  A partition insulating layer PI shown in FIG. 2 is further disposed on the passivation film PS. In the partition insulating layer PI, a through hole is provided at a position corresponding to the first electrode PE, or a slit is provided at a position corresponding to a column or row formed by the first electrode PE. Here, as an example, the partition insulating layer PI is provided with a through hole at a position corresponding to the first electrode PE.

  The partition insulating layer PI is, for example, an organic insulating layer. The partition insulating layer PI can be formed using, for example, a photolithography technique.

  On the first electrode PE, an organic layer ORG including a light emitting layer is disposed as an active layer. The light emitting layer is, for example, a thin film containing a luminescent organic compound whose emission color is red, green, or blue. The organic layer ORG can further include a hole injection layer, a hole transport layer, a hole blocking layer, an electron transport layer, an electron injection layer, and the like in addition to the light emitting layer.

  The partition insulating layer PI and the organic layer ORG are covered with a second electrode CE that is a counter electrode. The second electrode CE is a common electrode shared by all the pixels PX. In this embodiment, the second electrode CE is a light-reflective cathode that is a back electrode. The second electrode CE is, for example, an electrode wiring (not shown) formed on the same layer as the video signal line DL is formed through a contact hole provided in the passivation film PS and the partition insulating layer PI. )). Each organic EL element OLED includes a first electrode PE, an organic layer ORG, and a second electrode CE.

  Each pixel PX includes an organic EL element OLED and a pixel circuit. In this aspect, as shown in FIGS. 1 and 3, the pixel circuit includes a drive control element DR, an output control switch SWa, a selection switch SWb, a diode connection switch SWc, switches SWd1 to SWd5, and a capacitor C1. To C4. As described above, in this embodiment, the drive control element DR and the switches SWa to SWc and SWd1 to SWd5 are p-channel thin film transistors. The switches SWa to SWc and SWd1 to SWd5 constitute a switch group, and the capacitors C1 to C4 constitute a capacitor group.

  The drive control element DR, the output control switch SWa, and the organic EL element OLED are connected in series in this order between the first power supply terminal ND1 and the second power supply terminal ND2. In this aspect, the first power supply terminal ND1 is a high potential power supply terminal, and the second power supply terminal ND2 is a low potential power supply terminal. In this aspect, the source, drain, and gate of the drive control element DR correspond to the first terminal, the second terminal, and the control terminal, respectively.

  The gate of the output control switch SWa is connected to the scanning signal line SL1. The selection switch SWb is connected between the video signal line DL and the drain of the drive control element DR, and its gate is connected to the scanning signal line SL2. The diode connection switch SWc is connected between the drain and gate of the drive control element DR, and the gate is connected to the scanning signal line SL3. The selection switch SWb and the diode connection switch SWc are between a first state in which the drain and gate of the drive control element DR and the video signal line DL are connected to each other, and a second state in which they are disconnected from each other. The switch group which can be switched is comprised.

  The switch SWd1 and the capacitor C1 are connected in series in this order between the gate of the drive control element DR and the node ND3 that is the third terminal. The gate of the switch SWd1 is connected to the scanning signal line SL4.

  The switch SWd2 and the capacitor C2 are connected in series between the first power supply terminal ND1 that is a constant potential terminal and the node ND3. Here, as an example, the switch SWd2 and the capacitor C2 are connected in series in this order between the first power supply terminal ND1 and the node ND3. The gate of the switch SWd2 is connected to the scanning signal line SL5.

  The switch SWd3 and the capacitor C3 are connected in series between the gate of the drive control element DR and the node ND4 that is the fourth terminal. Here, as an example, the switch SWd3 and the capacitor C3 are connected in series in this order between the gate of the drive control element DR and the node ND4. The gate of the switch SWd3 is connected to the scanning signal line SL2.

  The switch SWd4 and the capacitor C4 are connected in series between the first power supply terminal ND1 and the node ND4. Here, as an example, the switch SWd4 and the capacitor C4 are connected in series in this order between the first power supply terminal ND1 and the node ND4. The gate of the switch SWd4 is connected to the scanning signal line SL6.

  The switch SWd5 is connected between the nodes ND3 and ND4. The gate of the switch SWd5 is connected to the scanning signal line SL1.

This organic EL display device is driven by the following method, for example.
FIG. 4 is a timing chart schematically showing an example of a method for driving the display device shown in FIG.

In FIG. 4, the horizontal axis indicates time, and the vertical axis indicates potential. In FIG. 4, among the “XDR output”, a period expressed as “I _sig (m + M)” indicates a period during which the video signal line driver XDR outputs the video signal I _sig (m + M) to the video signal line DL. Yes. Further, in FIG. 4, waveforms indicated by “SL1 potential” to “SL6 potential” indicate the potentials of the scanning signal lines SL1 to SL6, respectively.

  In the method of FIG. 4, the display device of FIG. 1 is driven by the following method. Here, for simplification, it is assumed that the capacitors C1 and C3 have the same capacitance, and the capacitors C2 and C4 have the same capacitance.

  In this driving method, the rows formed by the pixels PX are sequentially selected. The first and second writing operations are performed on the pixel PX included in the selected row. A display operation is performed on the pixels PX included in the non-selected rows.

  When a certain gradation is displayed by the pixel PX in the m-th row, the output control switch SWa is first opened (non-conducting state) in the period for selecting the pixel PX in the m-th row, that is, the m-th row selection period. . The following writing operation is performed within the first and second writing periods in which the output control switch SWa is open.

  In the first writing period, the first writing operation is performed. That is, the switches SWc and SWd2 are closed (conductive state), and the switch SWd4 is opened (non-conductive state). At this time, SWd1 is kept closed, and switches SWa, SWb, SWd3 and SWd5 are kept open. After a certain time elapses, the switches SWd1 and SWd2 are opened. As a result, the first writing period ends.

When the first write operation is performed, the gate-source voltage of the drive control element DR becomes equal to the threshold voltage _Vth . Therefore, potential V _dd of the first power supply terminal ND1, the capacitance C _a of the capacitor C1 and C3, when the capacitance of the capacitor C2 and C4 and C _b, the potential V ₅ in the potential V ₃ and node ND5 of the node ND3 is Each can be represented by the following equations (1) and (2). Therefore, the voltage between the node ND3 and the node ND5, that is, the voltage between the electrodes of the capacitor C1, V _C1 can be expressed by the following equation (3).

In the second writing period, the second writing operation is performed. That is, the switches SWb, SWd3, and SWd4 are closed. At this time, the switch SWc is kept closed, and the switches SWa, SWd1, SWd2, and SWd5 are kept open. In this state, a video signal is output from the video signal line driver XDR to the video signal line DL. That is, the video signal line driver XDR causes the write current I _sig (m) to flow from the first power supply terminal ND1 to the video signal line DL. After a certain time has elapsed, the switches SWb, SWc and SWd3 are opened. This ends the second writing period.

When the second write operation is performed, the difference between the potential V ₅ of the node ND5 and the potential V _dd of the first power supply terminal ND1 is the gate-source when the drive control element DR passes the write current I _sig (m). It becomes equal to the voltage between. Therefore, when the potential V ₅ of the node ND5 at this time is V _g (m), the potential V _{4 of the} node ND4 can be expressed by the following equation (4).

When the channel width of the drive control element DR is W, the channel length is L, the carrier mobility is μ, and the gate oxide film capacitance is C _ox , the drain current I _d of the drive control element DR in the saturation region is as follows: It can be expressed by equation (5). The write current I _sig (m) can be expressed by the following equation (6).

  In the effective display period following the second writing period, the switches SWa and SWd5 are closed. Further, the switches SWb, SWc, SWd2 and SWd3 are kept open, and the switches SWd1 and SWd4 are kept closed.

When the switch SWd5 is closed, the potential V _{3 of the} node ND3 becomes equal to the potential V _{4 of the} node ND4 expressed by equation (4). Since the capacitor C1 holds the interelectrode voltage V _C1 represented by the equation (3), the potential V _{5 of the} node ND5 is equal to the potential V ₄ represented by the equation (4) and the equation (3). Is equal to the sum of the interelectrode voltage V _C1 represented by That is, the potential V _{5 of the} node ND5 can be expressed by the following equation (7). Therefore, during the effective display period, the driving current I _drv (m) represented by the following equation (8) flows through the organic EL element OLED. The organic EL element OLED emits light with a luminance corresponding to the magnitude of the drive current I _drv (m).

By the way, the gradation in the low gradation range is displayed by flowing a small drive current I _drv through the organic EL element OLED. Therefore, when the magnitude of the write current I _sig is substantially equal to the magnitude of the drive current I _drv , the write current I _sig must be significantly reduced in order to display a gradation in the low gradation range. If the write current I _sig is small, it is difficult to set the gate-source voltage of the drive control element DR to a value corresponding to the write current I _sig in a short time due to the influence of the wiring capacity of the video signal line DL. .

On the other hand, according to the driving method described with reference to FIG. 4, the magnitude of the driving current I _drv is _equal to the write current _Ivv , as is apparent from the comparison between the equations (6) and (8). _sig size of the _{[C b / (C a +} C b)] ^twice. Therefore, if the capacitances C _a and C _b are set as appropriate, the gradation in the low gradation range can be displayed without significantly reducing the write current I _sig . Therefore, according to this aspect, each gradation within the low gradation range can be displayed with high reproducibility.

The capacitances of the capacitors C1 and C3 may be different from each other. Further, the capacitances of the capacitors C2 and C4 may be different from each other. In this case, the magnitude of the drive current I _{drv and} the magnitude of the write current I _sig deviate from the proportional relationship, but substantially the same effect as described above can be obtained.

  Further, a reset period may be provided before the writing period. For example, the following first and / or second reset operations may be performed prior to the first write operation.

In the first reset operation, the switches SWc and SWd2 are closed and the switches SWd4 and SWd5 are opened. At this time, the switches SWa and SWd1 are kept closed, and the switches SWb and SWd3 are kept open. The potential V _{5 of the} node N5 set by the first reset operation reflects the characteristics of the drive control element DR and the organic EL element OLED.

In the second reset operation, the switches SWd1 and SWd2 are opened, and the switches SWd3 and SWd4 are closed. At this time, the switches SWa and SWc are kept closed, and the switches SWb and SWd5 are kept open. The potential V ₅ of the node N5 is set by the second reset operation reflects the characteristics of the drive control element DR and the organic EL element OLED.

  In the first reset operation described here, the switching operation of the switch SWa and the switching operation of the switch SWd5 are individually controlled. In the second reset operation, in addition to individually controlling the switching operation of the switch SWa and the switching operation of the switch SWd5, the switching operation of the switch SWb and the switching operation of the switch SWd3 are individually controlled. When such control is performed, more scanning signal lines are laid.

Next, the second aspect of the present invention will be described.
FIG. 5 is a plan view schematically showing a display device according to the second aspect of the present invention. FIG. 6 is an equivalent circuit diagram of a pixel included in the display device of FIG.

  This display device is a bottom emission type organic EL display device adopting an active matrix driving method. This organic EL display device has the same structure as the organic EL display device according to the first aspect except for the following points.

  That is, in this organic EL display device, the scanning signal lines SL5 and SL6 are omitted. Each pixel PX includes an organic EL element OLED, a drive control element DR, an output control switch SWa, a selection switch SWb, a diode connection switch SWc, switches SWd1 to SWd3, and capacitors C1 to C3. It is out.

  The drive control element DR, the output control switch SWa, and the organic EL element OLED are connected in series in this order between the first power supply terminal ND1 and the second power supply terminal ND2. The gate of the output control switch SWa is connected to the scanning signal line SL1.

  The selection switch SWb is connected between the video signal line DL and the drain of the drive control element DR, and its gate is connected to the scanning signal line SL2. The diode connection switch SWc is connected between the drain and gate of the drive control element DR, and the gate is connected to the scanning signal line SL2.

  The switch SWd1, the capacitor C1, and the switch SWd2 are connected in series in this order between the gate of the drive control element DR and the node ND3 that is the third terminal. The gates of the switches SWd1 and SWd2 are connected to the scanning signal line SL3.

  The capacitor C2 is connected between the first power supply terminal ND1 that is a constant potential terminal and the node ND3.

  Capacitor C3 and switch SWd3 are connected in series between the gate of drive control element DR and node ND3. Here, as an example, the capacitor C3 and the switch SWd3 are connected in series in this order between the gate of the drive control element DR and the node ND3. The gate of the switch SWd3 is connected to the scanning signal line SL4.

This organic EL display device is driven by the following method, for example.
FIG. 7 is a timing chart schematically showing an example of a method of driving the display device shown in FIG.

In FIG. 7, the horizontal axis represents time, and the vertical axis represents potential. In FIG. 7, among “XDR output”, a period indicated as “I _sig (m + M)” indicates a period during which the video signal line driver XDR outputs the video signal I _sig (m + M) to the video signal line DL. Yes. Further, in FIG. 7, waveforms indicated by “SL1 potential” to “SL4 potential” indicate potentials of the scanning signal lines SL1 to SL4, respectively.

  In the method of FIG. 7, the display device of FIG. 5 is driven by the following method. Here, for the sake of simplicity, the capacitances of the capacitors C1 and C3 are assumed to be equal to each other.

  In this driving method, the rows formed by the pixels PX are sequentially selected. The first and second writing operations are performed on the pixel PX included in the selected row. A display operation is performed on the pixels PX included in the non-selected rows.

  When displaying a certain gradation with the pixel PX in the m-th row, first, the output control switch SWa is opened in the period for selecting the pixel PX in the m-th row, that is, the m-th row selection period. The following writing operation is performed within the first and second writing periods in which the output control switch SWa is open.

  In the first writing period, the first writing operation is performed. That is, the switch SWc is closed. At this time, the switches SWd1 and SWd2 are kept closed, and the switches SWb and SWd3 are kept open. After a certain time elapses, the switches SWd1 and SWd2 are opened. As a result, the first writing period ends.

When the first write operation is performed, the gate-source voltage of the drive control element DR becomes equal to the threshold voltage _Vth . Therefore, potential V _dd of the first power supply terminal ND1, the capacitance C _a of the capacitor C1 and C3, when the capacitance of the capacitor C2 and C _b, the potential V ₅ in the potential V ₃ and node ND5 of the node ND3, respectively, It can be represented by the above equations (1) and (2). Therefore, the voltage between the node ND3 and the node ND5, that is, the voltage between the electrodes of the capacitor C1, V _C1 can be expressed by the above equation (3).

In the second writing period, the second writing operation is performed. That is, the switches SWb and SWd3 are closed. At this time, the switch SWc is kept closed, and the switches SWa, SWd1, and SWd2 are kept open. In this state, a video signal is output from the video signal line driver XDR to the video signal line DL. That is, the video signal line driver XDR causes the write current I _sig (m) to flow from the first power supply terminal ND1 to the video signal line DL. After a certain time has elapsed, the switches SWb, SWc and SWd3 are opened. This ends the second writing period.

When the second write operation is performed, the difference between the potential V ₅ of the node ND5 and the potential V _dd of the first power supply terminal ND1 is the gate-source when the drive control element DR passes the write current I _sig (m). It becomes equal to the voltage between. Therefore, when the potential V ₅ of the node ND5 at this time is V _g (m), the potential V _{3 of the} node ND3 is equal to the potential V ₄ expressed by the above equation (4).

  In the effective display period following the second writing period, the switches SWa, SWd1, and SWd2 are closed. Further, the switches SWb, SWc, and SWd3 are left open.

When the switches SWd1 and SWd2 are closed, the potential V ₅ of the node ND5 becomes equal to the sum of the potential V _{3 of the} node ND3 and the interelectrode voltage V _C1 represented by equation (3). As described above, since the potential V ₃ is equal to the potential V ₄ expressed by the equation (4), the potential V _{5 of the} node ND5 can be expressed by the above equation (7). Therefore, during the effective display period, the driving current I _drv (m) represented by equation (8) flows through the organic EL element OLED. The organic EL element OLED emits light with a luminance corresponding to the magnitude of the drive current I _drv (m).

As is clear from this explanation, in this embodiment, the magnitude of the drive current I _drv is also [C _b / (C _a + C _b )] ² times the magnitude of the write current I _sig as in the first embodiment. can do. Therefore, if the capacitances C _a and C _b are set as appropriate, the gradation in the low gradation range can be displayed without significantly reducing the write current I _sig . Therefore, according to this aspect, each gradation within the low gradation range can be displayed with high reproducibility.

The capacitances of the capacitors C1 and C3 may be different from each other. In this case, the magnitude of the drive current I _{drv and} the magnitude of the write current I _sig deviate from the proportional relationship, but substantially the same effect as described above can be obtained.

  Further, a reset period may be provided before the writing period. For example, the following reset operation may be performed prior to the first write operation.

In the reset operation, the switch SWc is closed. At this time, the switches SWa, SWd1, and SWd2 are kept closed, and the switches SWb and SWd3 are kept open. The potential V _{5 of the} node N5 set by this reset operation reflects the characteristics of the drive control element DR and the organic EL element OLED.

  In the reset operation described here, the switching operation of the switch SWb and the switching operation of the switch SWd3 are individually controlled. When such control is performed, more scanning signal lines are laid.

  Further benefits and variations are readily apparent to those skilled in the art. Therefore, the invention in its broader aspects should not be limited to the specific descriptions and representative embodiments described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the generic concept of the invention as defined by the appended claims and their equivalents.

1 is a plan view schematically showing a display device according to a first aspect of the present invention. FIG. 2 is a cross-sectional view schematically illustrating an example of a structure that can be employed in the display device of FIG. 1. FIG. 2 is an equivalent circuit diagram of a pixel included in the display device of FIG. 1. 2 is a timing chart schematically showing an example of a method for driving the display device shown in FIG. 1. The top view which shows roughly the display apparatus which concerns on the 2nd aspect of this invention. FIG. 6 is an equivalent circuit diagram of a pixel included in the display device of FIG. 5. 6 is a timing chart schematically showing an example of a method for driving the display device shown in FIG. 5.

Explanation of symbols

  C1 ... Capacitor, C2 ... Capacitor, C3 ... Capacitor, C4 ... Capacitor, CE ... Second electrode, DE ... Drain electrode, DL ... Video signal line, DR ... Drive control element, G ... Gate, GI ... Gate insulating film, II ... Interlayer insulating film, ND1 ... first power supply terminal, ND2 ... second power supply terminal, ND3 ... node, ND4 ... node, ND5 ... node, OLED ... organic EL element, ORG ... organic layer, PE ... first electrode, PI ... Partition insulating layer, PS ... passivation film, PSL ... power supply line, PX ... pixel, SC ... semiconductor layer, SE ... source electrode, SL1 ... scan signal line, SL2 ... scan signal line, SL3 ... scan signal line, SL4 ... scan signal Line SL5 Scan signal line SL6 Scan signal line SUB Insulating substrate SWa Output control switch SWb Video signal supply control switch SWc Diode Connection switch, SWd1 ... switch, SWd2 ... switch, SWD3 ... switch, SWD4 ... switch, SWD5 ... switch, UC ... undercoat layer, XDR ... video signal line driver, YDR ... scanning signal line driver.

Claims (20)

A plurality of pixels arranged in a matrix, and a plurality of video signal lines arranged corresponding to a plurality of columns formed by the plurality of pixels, and each of the plurality of pixels includes:
A drive control element including a control terminal, a first terminal connected to the first power supply terminal, and a second terminal that outputs a current having a magnitude corresponding to a voltage between the control terminal and the first terminal When,
A display element including a first electrode, a second electrode connected to a second power supply terminal, and an active layer interposed between the first and second electrodes;
An output control switch connected between the second terminal and the first electrode;
Between a first state in which the second terminal, the control terminal, and the video signal line are connected to each other, and a second state in which the second terminal, the control terminal, and the video signal line are disconnected from each other. Switches that can be switched with
First to third capacitors;
Comprising first to third switches, wherein the first switch, the first capacitor, the second switch, and the second capacitor are connected in series between the control terminal and the constant potential terminal in this order, The display device, wherein the third switch and the third capacitor are connected in series between the control terminal and an electrode to which the second switch of the second capacitor is connected.   The display device of claim 1, wherein capacitances of the first and third capacitors are equal to each other. A plurality of first to fourth scanning signal lines arranged corresponding to a plurality of rows formed by the plurality of pixels;
The output control switch includes a field effect transistor having a gate connected to the first scanning signal line,
The switch group includes a selection switch including a field effect transistor connected between the second terminal and the video signal line and having a gate connected to the fourth scanning signal line, and the second terminal. A diode connection switch including a field effect transistor connected between the control terminal and having a gate connected to the second scanning signal line;
The first switch includes a field effect transistor having a gate connected to the third scanning signal line,
The second switch includes a field effect transistor having a gate connected to the third scanning signal line,
The display device according to claim 1, wherein the third switch includes a field effect transistor having a gate connected to the fourth scanning signal line. Each of the plurality of pixels is
A fourth capacitor;
The fourth capacitor and the fourth switch are further connected in series between the constant potential terminal and an electrode to which the second switch of the first capacitor is connected. The display device according to claim 1, wherein the second capacitor is connected to the constant potential terminal through the fifth switch.   The display device of claim 4, wherein the first and third capacitors have the same capacitance, and the second and fourth capacitors have the same capacitance. A plurality of first to sixth scanning signal lines arranged corresponding to a plurality of rows formed by the plurality of pixels;
The output control switch includes a field effect transistor having a gate connected to the first scanning signal line,
The switch group includes a selection switch including a field effect transistor connected between the second terminal and the video signal line and having a gate connected to the second scanning signal line, and the second terminal. A diode connection switch including a field effect transistor connected between the control terminal and having a gate connected to the third scanning signal line;
The first switch includes a field effect transistor having a gate connected to the fourth scanning signal line,
The second switch includes a field effect transistor having a gate connected to the first scanning signal line,
The third switch includes a field effect transistor having a gate connected to the second scanning signal line,
The fourth switch includes a field effect transistor having a gate connected to the fifth scanning signal line,
5. The display device according to claim 4, wherein the fifth switch includes a field effect transistor having a gate connected to the sixth scanning signal line.   The display device according to claim 1, wherein the constant potential terminal is connected to the first power supply terminal.   The display device according to claim 1, wherein the display element is an organic EL element. A plurality of pixel circuits arranged in a matrix, and a plurality of video signal lines arranged corresponding to a plurality of columns formed by the plurality of pixel circuits, and each of the plurality of pixel circuits includes:
A drive control element including a control terminal, a first terminal connected to a power supply terminal, and a second terminal that outputs a current having a magnitude corresponding to a voltage between the control terminal and the first terminal;
A pixel electrode;
An output control switch connected between the second terminal and the pixel electrode;
Between a first state in which the second terminal, the control terminal, and the video signal line are connected to each other, and a second state in which the second terminal, the control terminal, and the video signal line are disconnected from each other. Switches that can be switched with
First to third capacitors;
Comprising first to third switches, wherein the first switch, the first capacitor, the second switch, and the second capacitor are connected in series between the control terminal and the constant potential terminal in this order, The array substrate, wherein the third switch and the third capacitor are connected in series between the control terminal and an electrode to which the second switch of the second capacitor is connected.   The array substrate of claim 9, wherein the capacitances of the first and third capacitors are equal to each other. A plurality of first to fourth scanning signal lines arranged corresponding to a plurality of rows formed by the plurality of pixels;
The output control switch includes a field effect transistor having a gate connected to the first scanning signal line,
The switch group includes a selection switch including a field effect transistor connected between the second terminal and the video signal line and having a gate connected to the fourth scanning signal line, and the second terminal. A diode connection switch including a field effect transistor connected between the control terminal and having a gate connected to the second scanning signal line;
The first switch includes a field effect transistor having a gate connected to the third scanning signal line,
The second switch includes a field effect transistor having a gate connected to the third scanning signal line,
The array substrate of claim 9, wherein the third switch includes a field effect transistor having a gate connected to the fourth scanning signal line. Each of the plurality of pixel circuits is
A fourth capacitor;
The fourth capacitor and the fourth switch are further connected in series between the constant potential terminal and an electrode to which the second switch of the first capacitor is connected. The array substrate according to claim 9, wherein the second capacitor is connected to the constant potential terminal via the fifth switch.   The array substrate of claim 12, wherein the capacitances of the first and third capacitors are equal to each other, and the capacitances of the second and fourth capacitors are equal to each other. A plurality of first to sixth scanning signal lines arranged corresponding to a plurality of rows formed by the plurality of pixel circuits;
The output control switch includes a field effect transistor having a gate connected to the first scanning signal line,
The switch group includes a selection switch including a field effect transistor connected between the second terminal and the video signal line and having a gate connected to the second scanning signal line, and the second terminal. A diode connection switch including a field effect transistor connected between the control terminal and having a gate connected to the third scanning signal line;
The first switch includes a field effect transistor having a gate connected to the fourth scanning signal line,
The second switch includes a field effect transistor having a gate connected to the first scanning signal line,
The third switch includes a field effect transistor having a gate connected to the second scanning signal line,
The fourth switch includes a field effect transistor having a gate connected to the fifth scanning signal line,
The array substrate of claim 12, wherein the fifth switch includes a field effect transistor having a gate connected to the sixth scanning signal line.   The array substrate according to claim 9, wherein the constant potential terminal is connected to the first power supply terminal. A method for driving a display device according to claim 1, comprising:
Sequentially selecting a plurality of rows formed by the plurality of pixels;
Performing first and second writing operations on each of a plurality of pixels included in the selected row;
Performing a display operation on each of a plurality of pixels included in a non-selected row. The first write operation includes connecting the second terminal to the control terminal in a state where the output control switch and the third switch are opened and the first and second switches are closed;
In the second writing operation, the output control switch, the first and second switches are opened, the second terminal, the control terminal, and the video signal line are connected to each other, and the third switch is closed. And supplying a current signal as a video signal to the video signal line,
In the display operation, the second terminal, the control terminal, and the video signal line are disconnected from each other, the first and second switches are closed, and the third switch is opened. The method of claim 16, comprising connecting to the first electrode. Performing a reset operation on each of a plurality of pixels included in the selected row before performing the first and second writing operations;
The reset operation includes closing the output control switch and the first and second switches and connecting the second terminal to the control terminal with the third switch open. The method of claim 17. Each of the plurality of pixels further includes a fourth capacitor and fourth and fifth switches, wherein the fourth capacitor and the fourth switch are the constant potential terminal and the second switch of the first capacitor. Are connected in series between the electrodes connected to each other, and the second capacitor is connected to the constant potential terminal via the fifth switch,
In the first write operation, the output control switch and the second, third, and fifth switches are opened and the first and fourth switches are closed, and the second terminal is connected to the control terminal. Including
In the second writing operation, the output control switch and the first, fourth, and fifth switches are opened, the second terminal, the control terminal, and the video signal line are connected to each other. Supplying a current signal as a video signal to the video signal line in a state where the 5 switch is closed,
In the display operation, the second terminal, the control terminal, and the video signal line are disconnected from each other, the first, second, and fifth switches are closed, and the third and fourth switches are opened. The method of claim 16, comprising connecting the second terminal to the first electrode. Further comprising performing a first reset operation and / or a second reset for each of a plurality of pixels included in the selected row before performing the first and second write operations;
In the first reset operation, the output control switch and the first and fourth switches are closed and the second, third, and fifth switches are opened and the second terminal is connected to the control terminal. Including
The second reset operation closes the output control switch and the second and third switches and connects the second terminal to the control terminal with the first, fourth and fifth switches open. 20. The method of claim 19, comprising:

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