JP2006300891A - Failure part specifying device of lsi, and failure part locating method of lsi - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a failure part locating method of an LSI capable of early analyzing the cause of a failure operation of the LSI on a system. <P>SOLUTION: This failure part locating device obtains difference in clock cycle number between a first clock signal at the timing when the first LSI 4a of a good article outputs first output data and a second clock signal at the timing when the second LSI 4b having the same structure as that of the first LSI 4a outputs second output data same as the first output. The locating device determines a first clock cycle number of the first clock signal on the basis of the difference in clock cycle number when the first output data corresponding to the second output data is different from the second output data. The device detects second internal data of a second internal flip-flop that is different from first internal data of a first internal flip-flop disposed in the first LSI 4a stored as a clock cycle number equal to or less than the first clock cycle number, that is stored as a clock cycle number equal to or less than a second clock cycle number considering the difference in clock cycle number in the first clock cycle number, and that functions in the second LSI 4b similarly to the first internal flip-flop. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an LSI failure analysis method, and more particularly to an LSI failure location identification method and a failure location identification device.

  Recently, with the progress of LSI sub-micron (DSM), even if the LSI chip passes the shipping test using the LSI tester, the customer's customer system with the passed LSI is installed. There is an increase in defects that do not work properly.

  Elucidating the reason why the customer's system does not operate normally is very effective in reducing the failure rate of LSI that occurs only on the customer's system and reducing the failure rate of the customer's system quickly. is important.

  However, in the past, failure analysis of a system that does not operate normally is performed by a customer who has failed to reproduce the failure by evaluating the LSI mounted in the system that does not operate normally using an LSI tester. It was necessary to borrow a system board or make a similar system board by itself and try to reproduce the defect exclusively by hand. Moreover, the failure can be reproduced mainly by the failure that occurs after a very short time (within several seconds) after the system reset. For defects that occur after a longer period of time, it is necessary to extract a large amount of data for analyzing the operation, and it is almost impossible to analyze the defects. An LSI that cannot reproduce a defect is a so-called non-reproducible defective product, which has been a major obstacle to reducing the defect rate of LSI.

  Furthermore, we believe that it is difficult to eliminate defects in LSI on the customer's system by testing with the LSI tester alone, and a system board similar to that used in the customer's system should be installed before shipping the LSI. When an LSI that has been prepared and passed the shipment test by the LSI tester is further mounted on the system board and operated to determine the quality of the LSI, the test cost of the LSI is greatly increased. As described above, there has been a strong demand for a method that can analyze the cause of the malfunction of the LSI on the system at an early stage.

There has been proposed a circuit function inspection apparatus that inspects a system board to be inspected using a system board on which a non-defective LSI is mounted (for example, see Patent Document 1).
JP-A-10-206504

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an apparatus for identifying a defective part of an LSI that can analyze the cause of the defective operation of the LSI on the system at an early stage.

  It is another object of the present invention to provide a method for identifying a defective portion of an LSI that can analyze the cause of the defective operation of the LSI on the system at an early stage.

  The first feature of the present invention for solving the above problems is that a first LSI is used in a defective part specifying device for specifying a defective part of a second LSI having the same structure as the first LSI by using a good first LSI. A first clock generation circuit for generating a first clock signal synchronized with each other, a second clock generation circuit for generating a second clock signal having the same frequency as the first clock signal and synchronized with the second LSI, and the first clock signal. A first subtraction counter for subtracting, a second subtraction counter for subtracting in synchronization with the second clock signal, a first register for storing first output data of the first LSI for each first clock signal, and a second clock A second register that stores second output data of the second LSI for each signal, and a computer that sets the same first count value in the first subtraction counter and the second subtraction counter. The operation of the first LSI and the second LSI and the decrement of the first count value of the first subtraction counter and the second subtraction counter are started simultaneously. When the first count value becomes 0, the first subtraction counter or the second subtraction counter Based on the first signal flag, the computer serially transfers the first external data as the first external data string to the first register, and the second output data is serialized as the second external data string to the second register. The first external data string and the second external data string are compared, and if they do not match, different count values are set in the first subtraction counter and the second subtraction counter and the first external data string is subtracted from the subtraction. Until the comparison between the first output data and the second external data string is repeated, the first output data and the second output data corresponding to the first output data match the count value difference. A first clock cycle number of the first clock signal when the first output data corresponding to the second output data is different from the second output data is obtained based on the clock cycle number difference, and the first clock cycle number is obtained. Unlike the first internal data of the first internal flip-flop in the first LSI stored with the following clock cycle number, the first clock cycle number is a clock cycle number less than or equal to the second clock cycle number considering the clock cycle number difference. The defect location device of the LSI detects the second internal data of the second internal flip-flop stored and functioning similarly to the first internal flip-flop in the second LSI.

  The second feature of the present invention is that the first clock signal at the time (timing) at which the non-defective first LSI outputs the first output data and the second LSI having the same structure as the first LSI have the same second output as the first output data. A clock cycle number difference of the second clock signal at the time (timing) of outputting data is acquired, and the first output data corresponding to the second output data is different from the second output data based on the clock cycle number difference. The first clock cycle number of the clock signal is obtained, and unlike the first internal data of the first internal flip-flop in the first LSI that is stored with the clock cycle number less than or equal to the first clock cycle number, the clock cycle is set to the first clock cycle number. The first internal flip stored in the second LSI is stored with a clock cycle number less than or equal to the second clock number considering the number difference In bad position identification method of LSI for detecting a second internal data of the second internal flip-flop to drop the same function.

  As described above, according to the present invention, it is possible to provide an LSI defect location identification device that can analyze the cause of the malfunction of the LSI on the system at an early stage.

  Further, according to the present invention, it is possible to provide a method for identifying a defective part of an LSI that can analyze the cause of the defective operation of the LSI on the system at an early stage.

  Next, embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. It should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones.

  As shown in FIG. 1, the defective part identifying apparatus according to the first embodiment includes a printed circuit board 1 a on which a system can be mounted, a printed circuit board 1 b on which the same system as the printed circuit board 1 a can be mounted, and printed circuit boards 1 a and 1 b. A computer 3 such as a personal computer PC or an engineering workstation EWS for controlling the operation is provided. The computer 3 may include a part configured on a printed circuit board for high-speed signal input / output. The printed circuit board 1a includes a non-defective LSI 4a, a presettable 1 subtraction counter (decrementor) 5a, a clock generation circuit 7a, an input register 8a for holding an input to the LSI 4a, and an output (including input / output) from the LSI 4a. Is mounted. The printed circuit board 1b includes an LSI 4b to be inspected, a 1-subtraction counter 5b, a clock generation circuit 7b, an input register 8b for holding input to the LSI 4b, and an output register for holding output (including input / output) from the LSI 4b. 9b is mounted. The mounted system can be composed of LSIs including LSIs 4a and 4b, ICs, various passive components, and the like.

  The defective part specifying device can specify a defective part of the LSI 4b having the same structure as the LSI 4a by using a non-defective LSI 4a. A circuit diagram of the clock generation circuits 7a and 7b is shown in FIG.

  As shown in FIG. 2, in the defective part specifying method using the defective part specifying device, first, in step S1, the correlation between the time when the output data of the non-defective LSI 4a and the defective LSI 4b is output is obtained. Specifically, the first clock signal at the time (timing) at which the non-defective LSI 4a outputs the first output data, and the time at which the LSI 4b having the same structure as the LSI 4a outputs the second output data identical to the first output data ( The difference in the number of clock cycles of the second clock signal of (timing) is acquired.

  Next, in step S2, the occurrence time of the defect in the defective LSI 4b is specified. Specifically, the first clock cycle number of the first clock signal when the first output data corresponding to the second output data is different from the second output data based on the acquired clock cycle number difference is used as the failure occurrence time. Ask.

  In step S3, the internal data of the LSIs 4a and 4b before an appropriate number of clock cycles from the occurrence time of the defect is acquired. Specifically, the first internal data of the first internal flip-flop in the LSI 4a stored with the clock cycle number equal to or less than the first clock cycle number is acquired. Further, the second internal data of the second internal flip-flop, which is stored in the first clock cycle number with a clock number less than or equal to the second clock number considering the clock cycle number difference and functions in the same manner as the first internal flip-flop in the LSI 4b, is stored. get.

  In step S4, the first internal data and the second internal data are compared to identify the location where the defect has occurred. Specifically, second internal data different from the first internal data is detected at the earliest clock cycle number equal to or less than the first clock cycle number. As a result, the second internal flip-flop that has output the detected second internal data can be identified as a failure occurrence location.

  Step S1 of the defective part specifying method using the defective part specifying device will be described in detail with reference to FIG. 1, FIG. 3, FIG. 4, and FIG. In advance, the non-defective product 4a and the defective product 4b of the LSI to be analyzed are mounted on the sockets of the printed circuit boards 1a and 1b. Except for the LSI to be analyzed, the printed circuit boards 1a and 1b have the same structure. Therefore, the combination of the printed circuit boards 1a and 1b and the non-defective product 4a and the defective product 4b of the LSI to be analyzed is arbitrary. However, in the following description, since the description becomes complicated, the LSI 4a is mounted on the printed circuit board 1a, and the LSI 4b is mounted on the printed circuit board 1b.

In step S11, the clock generation circuit 7a generates a first clock signal in which the LSI 4a, the register 8a, the register 9a, and the subtraction counter 5a are synchronized from the basic clock signal transmitted from the basic clock generation circuit in the printed circuit board 1a. The clock generation circuit 7b has the same frequency as the first clock signal, and the basic clock signal transmitted from the basic clock generation circuit in the printed circuit board 1b is the second clock signal synchronized with the LSI 4b, the register 8b, the register 9b, and the subtraction counter 5b. Generate from. (In FIG. 1, only wirings connected to the LSI 4a and the LSI 4b are shown to avoid complexity.)
In step S12, the computer 3 supplies a common system reset signal Reset to the two printed circuit boards 1a and 1b, and resets the system and the LSIs 4a and 4b. During this period, the computer 3 transmits a preset command to the first subtraction counter 5a that subtracts in synchronization with the first clock signal and the second subtraction counter 5b that subtracts in synchronization with the second clock signal. At the same time, the same appropriate first count value is serially transmitted via SIcntrA and SIcntrB and preset. For example, these counters are configured to accept preset data during a period during which a preset command is transmitted and hold data during a period during which reset is valid. Note that this serial transmission may be configured to use a clock having a multiple cycle of the normal operation clock as will be described later in steps S15 to S17 so that the data is transmitted reliably.

  In step S13, the reset of the system and LSIs 4a and 4b is released, and the system operation is started. At the same time, the subtraction counters 5a and 5b are released from reset. The operation of the LSIs 4a and 4b and the decrement of the first count value of the subtraction counters 5a and 5b are started simultaneously. The counter 5a counts down in synchronization with the first clock signal from the clock generation circuit 7a. The counter 5b counts down in synchronization with the second clock from the clock generation circuit 7b. The register 8a stores first input data to the LSI 4a for each first clock signal. The register 9a stores the first output data from the LSI 4a for each first clock signal. The register 8b stores second input data to the LSI 4b for each second clock signal. The register 9b stores the second output data from the LSI 4b for each second clock signal.

  In step S14, when the count value reaches zero 0, one of the subtraction counters 5a or 5b stops counting and transmits a 0 signal flag Z1 or Z2. For reliable operation, the 0 signal flag may be transmitted via a flip-flop that detects a count value of 1 and generates a 0 signal flag, but such circuit design contrivances are within the scope of the present invention. Is within.

  In step S15, when the other counter 5a or 5b receives the 0 signal flag Z1 or Z2, it stops the subtraction count. Further, as shown in FIG. 4, the clock generation circuits 7a and 7b can select a clock having a multiple cycle of the normal operation clock so that the data can be reliably shifted.

  In step S16, when the computer 3 receives the 0 signal flag Z1 or Z2, the computer 3 transmits a shift instruction Shift to the clock generation circuits 7a and 7b by a predetermined number of clock cycles (see the timing chart of FIG. 5). . Here, the “number of clock cycles of a predetermined multiple-fold cycle” basically means a value obtained by adding the number of flip-flops of the register 8a (and 8b) and the register 9a (and 9b) (more precisely, at least the register 9a). And the number of clock cycles from which the contents of 9b can be read). For reliable confirmation of the operation, these numbers and the number of flip-flops connected in series in the counter 5a (and 5b) may be set to a large number.

  In step S17, when receiving the shift instruction Shift, the clock generation circuits 7a and 7b start to generate the first and second clock signals having a multiple cycle (see the timing chart of FIG. 5). At the same time, the same instruction is transmitted to the LSIs 4a and 4b, the registers 8a and 8b, the registers 9a and 9b, and the counters 5a and 5b, and these operation modes are changed from the normal operation mode to the shift operation mode. As a result, the flip-flops inside the LSIs 4a and 4b transmit the internal data from the SOLSIa and SOLSIb to the computer 3 in accordance with the multiple-cycle clocks from the clock generation circuits 7a and 7b. The registers 8a and 9a serially transfer the first input data and the first output data to the computer 3 via the SOIOa as a first external data string. The registers 8b and 9b serially transfer the second input data and the second output data to the computer 3 as a second external data string via the SOIOB. Further, the counters 5a and 5b transmit the count-down count value to the computer 3 via SOcntrA and SOcntrB. The computer 3 reads the transmitted data at an appropriate timing synchronized with the multiple-cycle clock.

  In step S18, after canceling the shift instruction Shift, the computer 3 obtains the count value difference (count value of the counter 5a−count value of the count 5b) D1. D1 can take the value of positive or negative or 0. Since one of the count values is zero, the absolute value of the difference coincides with the larger count value.

  In step S19, the computer 3 compares the contents of the register 9a and the register 9b to determine whether they match. At this time, the contents of the registers 8a and 8b may be compared for reference.

  In step S20, if the contents of the register 9a and the register 9b are different, the computer 3 sets the first count value as a preset value for one of the counters 5a and 5b (for example, the counter 5a) and presets the other. The count value “first count value + D2”, which is different from the first count value by D2, is set as the value, and the process returns to step S12 again and repeats up to step S18. Specifically, for example, D2 = n when the odd number (2n-1th, n = 1, 2,...) Is repeated, and when the even number (2n, n = 1, 2,...) Is repeated. As D2 = −n, the first count value + D2 is set as a preset value for the counter 5b.

  In step S21, if the contents of the register 9a and the register 9b match, the computer 3 uses the count value “first count value” of the counter 5a and the count value “first count value + D1 + D2” of the counter 5b to the non-defective LSI 4a. And the count value difference D1 + D2 of the same operation of the non-defective product LSI 4b and the defective product LSI 4b is stored as a count value difference of the same operation of the non-defective product LSI 4a and the defective product LSI 4b. In step S2 and subsequent steps, a counter value holding this difference is preset in the counters 5a and 5b. As a result, the counters 5a and 5b can be adjusted to be “0” at the same time, and the data to be compared can be read from the LSI 4a and the LSI 4b. The contents of the registers 9a and 9b, which are the external output data of the LSIs 4a and 4b, coincide with each other because the LSIs 4a and 4b have the same function, so that the same output as the first and second input data requiring the same input is obtained. This is because the first and second output data being transmitted always exist.

  As described above, it is possible to correctly grasp the correlation between the shifts in the operation time of the same operation after the reset release in the non-defective product LSI 4a and the defective product LSI 4b. That is, the location of data to be compared can be grasped as a time shift amount (difference between the first and second clock cycles), and the counters 5a and 5b are set to “0” at the same time. The counter value can be set.

  Step S2 of the defective part specifying method using the defective part specifying device will be described in detail with reference to FIGS. Assume that the clock signal has already been generated.

  In step S30, as in step S13, the computer 3 supplies a common system reset signal Reset to the two printed boards 1a and 1b, and resets the system and the LSIs 4a and 4b. During this period, the computer 3 transmits a preset command to the first subtraction counter 5a that subtracts in synchronization with the first clock signal and the second subtraction counter 5b that subtracts in synchronization with the second clock signal. At the same time, a value near the time at which it is estimated that a defect has occurred in the defective LSI 4b in the subtraction counter 5a is serially input as a second count value via SIcntrA and preset. At the same time, the computer 3 serially inputs via SIcntrB as a third count value taking the clock number difference D1 + D2 into the subtraction counter 5b and presets it.

  Thus, in these initial values, the count values reflecting the shift of the operation time obtained in step S1 are stored in the counters 5a and 5b via SIcntrA and SIcntrB, respectively. As a result, at the time of 0 count, the external data strings of the input / output values of the LSIs 4a and 4b after the same operation are shifted via the SOIOa and the SOIOb or the LSIs 4a and 4b after the same operation. The internal data string of the register can be acquired via SOLSIa and SOLSIb. This is due to the cause of the difference in operation time between the boards 1a and 1b. The difference in operation time is due to the fact that the processing is not executed every clock cycle of the first and second clock signals, and there is a clock cycle in which the processing is not executed, such as a wait state. Even if there is a clock cycle in which this processing is not performed, if the outputs of the LSIs 4a and 4b are desired outputs, there is no inconvenience for using the LSIs 4a and 4b in the normal operation mode, and the LSI 4a (until that time) The LSI 4b is considered to be a good product. A clock cycle in which this processing is not executed occurs at the same clock signal timing for each LSI 4a, 4b every time it is executed. The individual LSIs 4a and 4b are different in time (timing) and frequency of occurrence of a clock cycle in which processing is not executed. Due to the difference in the timing and frequency of occurrence of the clock cycle in which the processing of the individual LSIs 4a and 4b is not executed, a difference or deviation in operation time occurs. Also, in the case of high-speed operation, there may be a difference or deviation in operation time due to the possibility that the system reset time may slightly shift depending on the board. Such a difference in operation time is considered to be reflected in a difference in the number of occurrences of clock cycles in which processing is not performed, so-called clock cycle number difference D1 + D2.

  In step S31, as in step S13, the computer 3 cancels the reset of the system and the LSIs 4a and 4b, and the system operation is started. At the same time, the subtraction counters 5a and 5b are released from reset. The operation of the LSIs 4a and 4b and the decrement of the first count value of the subtraction counters 5a and 5b are started simultaneously. The counter 5a counts down in synchronization with the first clock signal from the clock generation circuit 7a. The counter 5b counts down in synchronization with the second clock from the clock generation circuit 7b. The register 8a stores first input data to the LSI 4a for each first clock signal. The register 9a stores the first output data from the LSI 4a for each first clock signal. The register 8b stores second input data to the LSI 4b for each second clock signal. The register 9b stores the second output data from the LSI 4b for each second clock signal.

  In step S32, when the count value reaches 0, the counter 5a or 5b stops the count operation and generates the 0 signal flag Z1 or Z2.

  In step S33, when the computer 3 receives the 0 signal flag Z1 or Z2, the computer 3 transmits the shift instruction Shift to the clock generation circuits 7a and 7b by the number of clock cycles of a predetermined multiple-cycle. Here, the “number of clock cycles having a predetermined multiple-fold cycle” is basically the number of flip-flops of the registers 8a (and 8b) and the registers 9a (and 9b). More precisely, it is the number of clock cycles in which at least the contents of the register 9a (and 9b) can be read. For reliable confirmation of the operation, these numbers and the number of flip-flops connected in series in the counter 5a (and 5b) may be set to a large number.

  In step S34, when receiving the shift command Shift, the clock generation circuits 7a and 7b start generating the first and second clock signals having a multiple period. At the same time, the same instruction is transmitted to the LSIs 4a and 4b, the registers 8a and 8b, the registers 9a and 9b, and the counters 5a and 5b, and these operation modes are changed from the normal operation mode to the shift operation mode. As a result, the flip-flops inside the LSIs 4a and 4b transmit the internal data from the SOLSIa and SOLSIb to the computer 3 in accordance with the multiple-cycle clocks from the clock generation circuits 7a and 7b. The registers 8a and 9a serially transfer the first input data and the first output data to the computer 3 via the SOIOa as a first external data string. The registers 8b and 9b serially transfer the second input data and the second output data to the computer 3 as a second external data string via the SOIOB. Further, the counters 5a and 5b transmit the count-down count value to the computer 3 via SOcntrA and SOcntrB. The computer 3 reads the transmitted data at an appropriate timing synchronized with the multiple-cycle clock and stores the data itself or stores it in an external storage device.

  In step S35, the computer 3 determines whether the second count value preset via SIcntrA and the third count value preset via SIcntrB have converged to a specific value (time). Further, the computer 3 compares the values of the registers 9a and 9b with each other. At this time, the values of the registers 8a and 8b may be compared for reference. If it has converged, the process of step S2 ends. If they have not converged and do not match, the process proceeds to step S36. If it is not converged and coincides, the process proceeds to step S37. If the compared values do not match, it can be seen that a defect has already occurred in the defective product 4b at the time corresponding to the preset count value.

  In step S36, count values (so-called early times) smaller than the previous second count value and third count value are set as preset values to be given to the counters 5a and 5b from SIcntrA and SIcntrB, respectively. Then, the process returns to step S30.

  In step S37, count values larger than the previous second count value and third count value (so-called later time) are set as preset values to be given to the counters 5a and 5b from SIcntrA and SIcntrB, respectively. Then, the process returns to step S30.

  In step S2, the above loop is repeated. The computer 3 obtains the smallest clock number as the first clock number T when the value of the register 9a (and 8a) read from the SOIOa is different from the value of the register 9b (and 8b) read from the SOIOb. By repeating this loop, an accurate time T (count value given from SIcntrA) at which a failure occurs at the output terminal (including a bidirectional terminal) of the LSI 4b to be analyzed, and the non-defective LSI 4a at that time T and the analysis Data strings of registers 8a and 9a, and 8b and 9b for input / output values of the target LSI 4b (read from SOIOa and SOIOb, respectively), and if necessary, data strings of shift registers in the LSI 4a and LSI 4b (SOLSIa and SOLSIb, respectively) Is read out).

  A method for efficiently obtaining an accurate defect occurrence time is a binary search method as a basic method, and this method can be applied to values preset in the counters 5a and 5b. good.

  Steps S3 and S4 of FIG. 2 of the defective part specifying method using the defective part specifying device will be described in detail with reference to FIGS. In the operation of the LSIs 4a and 4b, a true defect has occurred inside the LSI 4b 10 to several tens of clocks before the time when the defect occurs in the output value of the LSI 4b. For this reason, the input / output value of the analysis target LSI 4b and the value of the internal F / F at the time reduced by one clock from the time T until the difference of the internal data with the LSI 4a is no longer found. Reading is performed via the SOIOb and SOLSIb by the shift operation. The non-defective LSI 4a is similarly processed. The input / output values of the LSIs 4a and 4b and the internal F / F values are stored in the external storage device of the computer 3.

  First, in step S41, the computer 3 supplies a common system reset signal Reset to the two printed boards 1a and 1b to reset the system and the LSIs 4a and 4b. At the same time, the first clock cycle number T is preset in the first counter, and the second clock cycle number considering the clock cycle number difference D1 + D2 in the first clock cycle number T is preset in the second counter.

  In step S42, the computer 3 cancels the reset of the system and the LSIs 4a and 4b, and the system operation is started. At the same time, the subtraction counters 5a (first counter) and 5b (second counter) are released from reset. The operation of the LSIs 4a and 4b and the decrement of the first count value of the subtraction counters 5a and 5b are started simultaneously. The counter 5a counts down in synchronization with the first clock signal from the clock generation circuit 7a. The counter 5b counts down in synchronization with the second clock from the clock generation circuit 7b.

  In step S43, when the first clock cycle number T and the second clock cycle number become 0, the 0 signal flag Z1 or Z2 is transmitted.

  In step S44, when the computer 3 receives the 0 signal flag Z1 or Z2, the computer 3 transmits the shift instruction Shift to the clock generation circuits 7a and 7b by the number of clock cycles of a predetermined multiple-cycle. Here, the “number of clock cycles having a predetermined multiple-fold cycle” basically means the maximum number of flip-flops serially connected for the scan test inside the LSI 4a (and 4b) and the counter 5a (and 5b). This is the largest number among the number of flip-flops connected in series and the number of flip-flops of the registers 8a (and 8b) and 9a (and 9b).

  In step S45, when receiving the shift instruction Shift, the clock generation circuits 7a and 7b start generating the first and second clock signals having a multiple period. At the same time, the same instruction is transmitted to the LSIs 4a and 4b, the registers 8a and 8b, the registers 9a and 9b, and the counters 5a and 5b, and these operation modes are changed from the normal operation mode to the shift operation mode. As a result, the flip-flops inside the LSIs 4a and 4b transmit the internal data from the SOLSIa and SOLSIb to the computer 3 in accordance with the multiple-cycle clocks from the clock generation circuits 7a and 7b. The registers 8a and 9a serially transfer the first input data and the first output data to the computer 3 via the SOIOa as a first external data string. The registers 8b and 9b serially transfer the second input data and the second output data to the computer 3 as a second external data string via the SOIOB. Further, the counters 5a and 5b transmit the count-down count value to the computer 3 via SOcntrA and SOcntrB. The computer 3 reads the transmitted data at an appropriate timing synchronized with the multiple-cycle clock and stores the data itself or stores it in an external storage device.

  In step S46, the computer 3 compares the first internal data string read from SOLSIa with the second internal data string read from SOLSIb, and determines whether they match. If they are different, in step S47, second internal data different from the first internal data is detected and stored, and a value one smaller than the value set in step S41 is set as the first clock cycle number. Then, the process returns to step S41. On the other hand, if they match, in step S48, the computer 3 determines that the first clock cycle number (time) set in the previous loop is the failure occurrence time, and stores and outputs it. Further, the internal F / F storing the second internal data in which the difference from the non-defective product stored in the previous loop is detected is determined as the cause of the failure and output. Further, as reference data for analysis, all second internal data in which a difference from a good product is detected may be traced out as the second and first clock cycle numbers.

  According to the defect location identification method of the first embodiment, the external data and internal data of the non-defective product 4a and the defective product 4b can be automatically compared on the computer 3, and the exact failure occurrence time T and the failure occurrence location of the defective LSI 4b can be efficiently calculated. Can be extracted and specified automatically.

  In the above, the subtraction counter is not limited to the subtraction counter itself, but can be realized by an addition counter register that can set a target count value. Therefore, the subtraction counter in the above description is realized by replacing it with an addition counter register having substantially the same function. Including doing.

  In the first embodiment, the operations of the non-defective product 4a and the defective product 4b are compared every cycle. However, in the case of a high-speed LSI in which the LSI is operated with a multiple clock in a phase-locked loop (PLL) circuit, internal multiplication is performed. It is difficult to read out the internal data for each clock, and further ingenuity is required. In the second embodiment, a case will be described in which an LSI that includes a PLL circuit and operates in synchronization with a multiplied clock is used as an analysis target. The important part is the method of selection of the clock phase caused by multiplication. In the second embodiment, a case of quadruple multiplication will be described.

  As shown in FIG. 8, the defective part specifying apparatus according to the second embodiment is almost the same as the defective part specifying apparatus of the first embodiment shown in FIG. There are four points of difference between the failure location device of the second embodiment and the first embodiment. First, the first point is that the computer 3 outputs the phase data phasedataA to the LSI 4a. The second point is that the computer 3 outputs the phase data phasedataB to the LSI 4b. The third point is that the LSI 4a inputs the 0 signal flag Z1. The fourth point is that the LSI 4b inputs the 0 signal flag Z2.

  Further, the LSI 4a of the second embodiment and the first embodiment is different. As shown in FIG. 9, the LSI 4a according to the second embodiment includes a register 11a with an internal comparator, a selector 12a, and a phase-locked loop (PLL) circuit PLL in addition to the LSI 4a according to the first embodiment. The LSIs 4b of the second embodiment and the first embodiment are also different. As shown in FIG. 10, the LSI 4b according to the second embodiment includes a register 11b with an internal comparator, a selector 12b, and a phase-locked loop circuit PLL in addition to the LSI 4b according to the first embodiment. FIG. 11 shows a configuration example of the registers with comparators 11a and 11b. The 2-bit counter is always incremented by the internal multiplied clock signal after being reset by the LSI internal reset signal, and returns to “00” after “11”. Also, this 2-bit counter has a count enable input E, and counts up when E = 1, and holds the count value at that time (does not count up) when E = 0. Yes. Here, when the “0” flag signal Z is changed from 0 to 1 in the state where the phase data is given from the computer 3, the count value is counted up from that point until the count value becomes equal to the phase data, and the output signal S = 1. Since E = 0, the count value is held.

  In the defective part specifying method using the defective part specifying device of the second embodiment, several steps are newly added to the defective part specifying method of the first embodiment.

  First, before steps S11, S30, and S41, as the initial states of the LSIs 4a and 4b, the PLLs included in the LSIs 4a and 4b output internal multiplication clock signals for the multiplication operation. The selector 12a receives an internal multiplied clock output from the PLL and an external clock output from the clock generation circuit 7a. The selector 12a selects the internal multiplied clock output from the PLL, and outputs the internal multiplied clock to the internal circuit of the LSI 4a. The selector 12b receives an internal multiplied clock output from the PLL and an external clock output from the clock generation circuit 7b. The selector 12b selects the internal multiplied clock output from the PLL and outputs the internal multiplied clock to the internal circuit of the LSI 4b.

  After steps S12, S30, and S41, the computer 3 inputs phase data phase data A and phase data B representing the phase of the multiplication operation to stop the LSIs 4a and 4b to the counters with comparators 11a and 11b. Counters with comparators 11a and 11b are synchronized with the multiplied clock. As a result, it is possible to set in advance how the computer 3 shifts out the internal data of the LSIs 4a and 4b that are output at the multiplied phase. In quadruple multiplication, it is only necessary to specify four types of phases from the first phase to the fourth phase C1 to C4. Therefore, each of the phase data phase data A and phase data B may be 2 bits. 9 and 10, the phase data phase data A and phase data B are (0, 1), indicating that the second phase C2 is designated.

  After steps S14, S32, and S43, the counters with comparators 11a and 11b output the select signal Sa or Sb at the first corresponding second phase C2 after inputting the 0 signal flag Z1 or Z2, and the selector 12a And 12b are switched to the external clock. Therefore, the 0 signal flag Z1 or Z2 is preferably synchronized with a specific phase such as the first phase C1 of the internal clock. The selectors 12a and 12b block the clock signals C3 and C4 after the second phase based on the select signal Sa or Sb. Note that it is preferable to stop the supply of the external clock immediately after the interruption. This is to stabilize the states of the LSIs 4a and 4b.

  After steps S14, S32, and S43, as in the first embodiment, LSI data is read out via the SOIOa, SOIOb, SOLSIa, and SOLSIb by a shift instruction. As described above, the count values of the subtraction counters 5a and 5b are preset from SIcntrA and SIcntrB, respectively, and by specifying the phase data phase dataA and phase dataB, all the LSI data of the desired phases of the LSIs 4a and 4b to be analyzed Can be read from SOIOa, SOIOb, SOLSIa, and SOLSIb.

  Of course, the circuits on the boards 1a and 1b described in the first and second embodiments may be mounted inside the LSIs 4a and 4b.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a configuration diagram of an LSI defect location identifying apparatus according to a first embodiment. 3 is a flowchart of a method for identifying a defective portion of an LSI according to the first embodiment. 4 is a detailed flowchart of step S1 of the method for identifying a defective portion of an LSI according to the first embodiment. 1 is a configuration diagram of a clock generation circuit according to Embodiment 1. FIG. 3 is a timing chart of the defective part specifying method according to the first embodiment. 4 is a detailed flowchart of step S2 of the method for identifying a defective portion of an LSI according to the first embodiment. 4 is a detailed flowchart of steps S3 and S4 of the method for identifying a defective portion of an LSI according to the first embodiment. FIG. 6 is a configuration diagram of an LSI defect location identification apparatus according to a second embodiment. FIG. 10 is a configuration diagram of a non-defective LSI used in Example 2. 6 is a configuration diagram of an LSI to be inspected used in Example 2. FIG. 6 is a configuration diagram of a counter with a comparator used in Embodiment 2. FIG.

Explanation of symbols

1a, 1b Board 3 Computer 4a Non-defective LSI
4b LSI to be inspected
5a, 5b Subtraction counter 7a, 7b Clock generation circuit 8a, 8b Input register 9a, 9b Output register 11a, 11b Counter with internal comparator 12a, 12b Selector

Claims (5)

In a defective part specifying device for specifying a defective part of a second LSI having the same structure as that of the first LSI using a good first LSI,
A first clock generation circuit for generating a first clock signal synchronized with the first LSI;
A second clock generation circuit for generating a second clock signal having the same frequency as the first clock signal and synchronized with the second LSI;
A first subtraction counter for subtracting in synchronization with the first clock signal;
A second subtraction counter for subtracting in synchronization with the second clock signal;
A first register for storing first output data of the first LSI for each first clock signal;
A second register for storing second output data of the second LSI for each second clock signal;
A computer for setting the same first count value in the first subtraction counter and the second subtraction counter;
Simultaneously starting the operation of the first LSI and the second LSI, and decrementing the first count value of the first subtraction counter and the second subtraction counter,
The first subtraction counter or the second subtraction counter transmits a first signal flag when the first count value becomes 0,
Based on the first signal flag, the computer causes the first register to serially transfer the first output data to the computer as a first external data string, and causes the second register to transmit the second output data. Serial transfer as a second external data string to the computer;
The computer compares the first external data string and the second external data string. If they do not match, the computer sets a different count value to the first subtraction counter and the second subtraction counter and sets the first subtraction counter to the second subtraction counter. Repeat until the comparison of one external data string and the second external data string, and obtain the clock cycle number difference from the difference between the count values at which the first output data and the second output data corresponding to the first output data match,
Determining a first clock cycle number of the first clock signal when the first output data corresponding to the second output data is different from the second output data based on the clock cycle number difference;
Unlike the first internal data of the first internal flip-flop in the first LSI, which is stored with a clock cycle number less than or equal to the first clock cycle number, the first clock cycle number takes into account the difference in the number of clock cycles. A defective portion of an LSI, wherein the second internal data of a second internal flip-flop that is stored with a clock cycle number less than or equal to two clock cycle numbers and functions in the second LSI in the same manner as the first internal flip-flop is detected. Specific device. When determining the first clock cycle number of the first clock signal when the first output data corresponding to the second output data is different from the second output data based on the clock cycle number difference,
The computer inputs a second count value to the first counter;
The computer inputs a third count value obtained by adding the clock cycle number difference to the second count value to the second counter;
Simultaneously starting the operations of the first LSI and the second LSI, and decrementing the second count value and the third count value,
A first register storing the first output data for each of the first clock signals;
A second register stores the second output data for each second clock signal;
When the second count value or the third count value becomes 0, a second signal flag is transmitted,
Based on the first signal flag, the computer causes the first register to serially transfer the first output data to the computer as a first external data string, and causes the second register to transmit the second output data. Serial transfer as a second external data string to the computer;
2. The LSI defect according to claim 1, wherein the computer obtains the smallest clock cycle number as the first clock cycle number when the first external data sequence and the second external data sequence are different. Location specific device. Unlike the first internal data of the first internal flip-flop in the first LSI, which is stored with a clock cycle number less than or equal to the first clock cycle number, the first clock cycle number takes into account the difference in the number of clock cycles. When detecting second internal data of a second internal flip-flop that is stored with a clock cycle number less than or equal to two clock cycle numbers and functions in the same manner as the first internal flip-flop in the second LSI,
The computer inputs the first clock cycle number to the first counter;
The computer inputs the second clock cycle number to the second counter;
Simultaneously start the operation of the first LSI and the second LSI and the decrement of the first clock number and the second clock number,
When the first clock number or the second clock number becomes 0, a third signal flag is transmitted,
The computer serially transfers the first internal data of the first LSI to the computer as a first internal data string based on the first signal flag, and causes the computer to transfer the second internal data of the second LSI to the second internal data. Serial transfer as a data string, serially transfer the first output data to the computer as a first external data string to the first register, and second external data to the computer to the second register Serial transfer as a data string,
The computer compares the first internal data string with the second internal data string when the first clock cycle number input to the first counter is as small as possible, and the first internal data is different from the first internal data. 2. The apparatus for identifying a defective portion of an LSI according to claim 1, wherein internal data is detected. The phase-locked loop circuit PLL included in each of the first LSI and the second LSI outputs a clock signal for multiplication operation,
The computer inputs phase data representing the phase of the multiplication operation for stopping the first LSI and the second LSI to a first internal counter included in the first LSI and a second internal counter included in the second LSI,
The first internal counter and the second internal counter output a select signal during the first phase after inputting any one of the first signal flag to the third signal flag,
4. The LSI defect location identifying device according to claim 1, wherein the first selector and the second selector block the clock signal in the phase based on the select signal. 5. A first clock signal at a time (timing) at which the first non-defective LSI outputs the first output data, and a time at which the second LSI having the same structure as the first LSI outputs the second output data identical to the first output data ( Timing) of the clock cycle number difference of the second clock signal,
Determining a first clock cycle number of the first clock signal when the first output data corresponding to the second output data is different from the second output data based on the clock cycle number difference;
Unlike the first internal data of the first internal flip-flop in the first LSI, which is stored with a clock cycle number less than or equal to the first clock cycle number, the first clock cycle number takes into account the difference in the number of clock cycles. A defective portion of an LSI, wherein the second internal data of a second internal flip-flop that is stored with a clock cycle number less than or equal to two clock cycle numbers and functions in the second LSI in the same manner as the first internal flip-flop is detected. Identification method.

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