JP2006295043A - Semiconductor device, electronic module, and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and an electronic module with high electrical reliability that can easily be inspected for electrical characteristics and excellent in mountability, and a method for manufacturing them.
A semiconductor device includes a semiconductor substrate, an electrode pad formed above the semiconductor substrate, and an opening that exposes at least a part of the electrode pad. The semiconductor device is formed above the semiconductor substrate. The passivation film 16 and the bump 20 formed so as to cover the opening 18 and the end of the passivation film 16 above the semiconductor substrate 10 are included. The bump 20 includes a concave portion 22, a first convex portion 24 surrounding the concave portion 22, and a second convex portion 26 whose height from the electrode pad 14 is higher than that of the first convex portion 24.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device and an electronic module, and methods for manufacturing the same.

  It is known that bumps formed on a semiconductor chip are electrically connected to face a wiring pattern. In this case, in order to manufacture a highly reliable semiconductor device, it is preferable that the bump has a shape suitable for electrical connection with the wiring pattern. It is also known to inspect the electrical characteristics of a semiconductor chip using bumps. In this case, in order to efficiently perform a highly reliable inspection, it is preferable that the bumps have a shape suitable for the inspection.

An object of the present invention is to provide a semiconductor device, an electronic module with high electrical reliability, and a manufacturing method thereof, which are easy to inspect for electrical characteristics and excellent in mountability.
JP 2000-357701 A

(1) A semiconductor device according to the present invention includes a semiconductor substrate,
An electrode pad formed above the semiconductor substrate;
A passivation film having an opening exposing at least a part of the electrode pad, and formed above the semiconductor substrate;
A bump formed above the semiconductor substrate so as to cover the opening and the end thereof, and a height from the concave portion, the first convex portion surrounding the concave portion, and the electrode pad. The bump having a second convex portion higher than the convex portion of
including. According to the present invention, it is possible to provide a semiconductor device that can be easily inspected for electrical characteristics and has high mountability. The semiconductor device includes a semiconductor substrate having an electrode pad and a passivation film in which an opening exposing a central region of the electrode pad is formed;
A recess formed on the semiconductor substrate so as to cover the opening and its end, a first protrusion surrounding the recess, and a height from the electrode pad is higher than that of the first protrusion. A bump having a high second protrusion;
It may be said that it contains.
(2) In this semiconductor device,
The concave portion may be arranged inside a region overlapping with the opening.
(3) In this semiconductor device,
The first convex portion may be arranged so as to overlap with the passivation film.
(4) In this semiconductor device,
The second convex portion may be disposed inside a region overlapping with the opening.
(5) In this semiconductor device,
The outer shape of the bump may be smaller than the electrode pad.
(6) In this semiconductor device,
The outer shape of the bump may be larger than the electrode pad.
(7) The above semiconductor device is mounted on the electronic module according to the present invention.
(8) In the method for manufacturing a semiconductor device according to the present invention, a semiconductor substrate having an electrode pad and a passivation film in which an opening exposing at least a part of the electrode pad is formed. Forming a bump having one convex portion and a second convex portion having a height from the electrode pad higher than the first convex portion so as to cover the opening and the end thereof. According to the present invention, it is possible to manufacture a semiconductor device that can be easily inspected for electrical characteristics and has high mountability.
(9) In this method of manufacturing a semiconductor device,
You may form the said bump so that the said recessed part may be arrange | positioned inside the area | region which overlaps with the said opening.
(10) In this method of manufacturing a semiconductor device,
The bump may be formed such that the first convex portion overlaps the passivation film.
(11) In this method of manufacturing a semiconductor device,
The bump may be formed so that the second convex portion is disposed inside a region overlapping with the opening.
(12) In this method of manufacturing a semiconductor device,
The bump may be formed to be smaller than the electrode pad.
(13) In this method of manufacturing a semiconductor device,
The bump may be formed to be larger than the electrode pad.
(14) In this method of manufacturing a semiconductor device,
The step of forming the bump may include a plating step.
(15) An electronic module manufacturing method according to the present invention includes a step of preparing a wiring board having a wiring pattern;
An electrode pad, a passivation film in which an opening exposing at least a part of the electrode pad is formed, and a bump formed so as to cover the opening and an end thereof, a recess, and a first surrounding the recess A step of preparing a semiconductor device having the bumps and the bumps having the second bumps having a height higher than the first bumps from the electrode pads;
Mounting the semiconductor device on the wiring board and bringing the bump and the wiring pattern into contact with each other to electrically connect;
Including
A method of manufacturing an electronic module, wherein in the step of mounting the semiconductor device, the second convex portion is deformed by bringing the second convex portion into contact with the wiring pattern. According to the present invention, a highly reliable electronic module can be manufactured.

  Embodiments to which the present invention is applied will be described below with reference to the drawings. However, the present invention is not limited to the following embodiments.

  1A to 1C are diagrams for describing a semiconductor device according to an embodiment to which the present invention is applied. FIG. 1A is a cross-sectional view of the semiconductor device 1. FIG. 1B is an enlarged view of the vicinity of the bump 20 in FIG. FIG. 1C is a top view of the bump 20.

The semiconductor device according to the present embodiment includes a semiconductor substrate 10 as shown in FIG. The semiconductor substrate 10 may be a silicon substrate, for example. The semiconductor substrate 10 may have a chip shape (see FIG. 1A). However, the semiconductor substrate 10 may have a wafer shape (see FIG. 9A). The semiconductor substrate 10 may have one or a plurality of integrated circuits 12 (one for a semiconductor chip and a plurality for a semiconductor wafer). The configuration of the integrated circuit 12 is not particularly limited, and may include, for example, an active element such as a transistor or a passive element such as a resistor, a coil, or a capacitor. The semiconductor substrate 10 has electrode pads 14 as shown in FIGS. That is, it can be said that the semiconductor device according to the present embodiment includes the electrode pad 14. The electrode pad 14 may be electrically connected to the inside of the semiconductor substrate 10. The electrode pad 14 may be electrically connected to the integrated circuit 12. Alternatively, the electrode pad 14 including the electrode pad that is not electrically connected to the integrated circuit 12 may be referred to. The electrode pad 14 may be formed of a metal such as aluminum or copper. The electrode pads 14 may be arranged along the outer periphery of the semiconductor substrate 10. Alternatively, the electrode pads 14 may be arranged in an area array. The electrode pad 14 may be formed so as to overlap with the integrated circuit 12 or may be formed so as not to overlap with the integrated circuit 12. As shown in FIGS. 1A and 1B, the semiconductor substrate 10 has a passivation film 16. That is, it can be said that the semiconductor device according to the present embodiment has the passivation film 16. The passivation film 16 is formed with an opening 18 for exposing at least a part of the electrode pad 14. The opening 18 may be formed so as to expose only the central region of the electrode pad 14 (see FIGS. 1B and 9B). That is, the passivation film 16 may be formed so as to cover the peripheral edge of the electrode pad 14. The passivation film may be formed of, for example, SiO ₂ , SiN, polyimide resin, or the like. Note that a region of the electrode pad 14 exposed from the opening 18 of the passivation film 16 may be referred to as an exposed portion 15 (see FIGS. 1B and 9B).

  The semiconductor device according to the present embodiment has bumps 20 as shown in FIGS. The bump 20 is formed on the semiconductor substrate 10. The bump 20 is formed so as to cover the opening 18 of the passivation film 16 and its end. That is, the bump 20 may be formed so as to cover the exposed portion 15. The bumps 20 may be formed so as to reach the passivation film 16. The outer shape of the bump 20 is not particularly limited, but may be a rectangle (including a square and a rectangle) or a circle. Further, the outer shape of the bump 20 may be smaller than that of the electrode pad 14. At this time, the bump 20 may be formed only in a region overlapping with the electrode pad 14. Alternatively, the outer shape of the bump 20 may be larger than the electrode pad 14.

  As shown in FIGS. 1B and 1C, the bump 20 has a recess 22. The recess 22 may be a portion of the surface of the bump 20 that has the lowest height from the electrode pad 14. The bottom surface of the recess 22 may be a flat surface. The recess 22 may be disposed inside a region overlapping with the opening 18 of the passivation film 16. The outer shape of the bottom surface of the recess 22 may have the same shape as the opening 18. The concave portion 22 may be disposed so as to overlap the exposed portion 15.

  The bump 20 has the 1st convex part 24, as shown in FIG.1 (B) and FIG.1 (C). The first convex part 24 is arranged so as to surround the concave part 22. The first convex portion 24 is higher than the concave portion 22 from the electrode pad 14. The first convex portion 24 may be disposed so as to overlap with the passivation film 16. The first convex portion 24 may be disposed inside a region overlapping with the electrode pad 14. Or the 1st convex part 24 may be arrange | positioned so that it may reach an outer side rather than the area | region which overlaps with the electrode pad 14. FIG. The first convex portion 24 may constitute the outer shape of the bump 20. The first convex portion 24 may have the same thickness as the bottom portion of the concave portion 22.

  The bump 20 has the 2nd convex part 26, as shown to FIG. 1 (B) and FIG.1 (C). The height of the second convex portion 26 from the electrode pad 14 is higher than that of the first convex portion 24. The second convex portion 26 may be a portion of the surface of the bump 20 that has the highest height from the electrode pad 14. The second convex portion 26 may be formed inside a region overlapping with the opening 18 of the passivation film 16. In other words, the second convex portion 26 may be formed in a region overlapping with the exposed portion 15. At this time, the 2nd convex part 26 may be formed so that it may be enclosed by the recessed part 22 (refer FIG.1 (C)). Further, the second convex portion 26 may be formed avoiding the first convex portion 24. That is, the 2nd convex part 26 may be formed so that it may be enclosed by the 1st convex part 24 (refer FIG.1 (C)). The second convex portion 26 may be smaller than the outer shape of the bump 20.

  The semiconductor device 1 according to the present embodiment may have the above configuration. As described above, the bump 20 is formed so as to cover the opening 18 and the end portion of the passivation film 16. That is, the bump 20 is formed so as to cover the exposed portion 15. According to this, exposure of the electrode pad 14 can be prevented. Therefore, it is possible to provide a highly reliable semiconductor device that can prevent deterioration of the electrode pad 14.

  In addition, the use of the bumps 20 facilitates the inspection of the electrical characteristics of the semiconductor device 1. FIG. 2A to FIG. 2D are diagrams for explaining the electrical property inspection process using the bump 20. Generally, it is known that a probe is brought into contact with a bump of a semiconductor device (semiconductor chip) to inspect its electrical characteristics. In this inspection, the probe may be pressed against the bump in order to electrically connect the probe to the bump (see FIG. 2C), but in order to perform a highly reliable inspection, the probe is removed from the bump. It is necessary to prevent it from coming off. In particular, as the bump size becomes smaller, it is expected that it will be difficult to reliably contact the probe and the bump. Incidentally, as described above, the bump 20 has the concave portion 22 and the first convex portion 24 surrounding the concave portion 22. Therefore, as shown in FIGS. 2 (A) and 2 (B), if the probe 100 is arranged inside the recess 22, even if the probe is further pressed as shown in FIG. Can be prevented from coming off from the recess 22. That is, as shown in FIG. 2D, since the first convex portion 24 is disposed between the probe 100 and the end portion of the bump 20, it is possible to prevent the probe 100 from being detached from the bump 20. . Therefore, the probe 100 can be reliably brought into contact with the bump 20. That is, according to the present invention, it is possible to provide a semiconductor device capable of accurately inspecting electrical characteristics.

  Further, by using the bumps 20, the semiconductor device 1 can be easily and reliably mounted on a wiring board or the like. That is, the bump 20 and the wiring pattern can be electrically connected easily and reliably. Hereinafter, in order to explain this feature, an electronic module manufacturing method will be described with reference to FIGS.

  The method for manufacturing the electronic module may include preparing the wiring board 30 shown in FIG. The material of the wiring board 30 is not particularly limited, and may be any organic or inorganic material, or may be composed of a composite structure thereof. For example, a substrate or a film made of polyethylene terephthalate (PET) may be used as the wiring substrate 30. Alternatively, a flexible substrate made of polyimide resin may be used as the wiring substrate 30. As the flexible substrate, a tape used in FPC (Flexible Printed Circuit) or TAB (Tape Automated Bonding) technology may be used. Examples of the wiring substrate 30 formed from an inorganic material include a ceramic substrate and a glass substrate. When the wiring board 30 is a glass substrate, the wiring board 30 may be a part of an electro-optical panel (liquid crystal panel, electroluminescence panel, etc.). The wiring board 30 has a wiring pattern 32. The material of the wiring pattern 32 is not particularly limited. For example, the wiring pattern 32 may be formed by stacking any one of copper (Cu), chromium (Cr), titanium (Ti), nickel (Ni), and titanium tungsten (Ti—W). Alternatively, when the wiring substrate 30 is a liquid crystal panel, the wiring pattern 32 may be formed of a metal film such as ITO (Indium Tin Oxide), Cr, or Al, a metal compound film, or a composite film thereof. At this time, the wiring pattern 32 may be electrically connected to an electrode (scanning electrode, signal electrode, counter electrode, etc.) that drives the liquid crystal.

  The electronic module manufacturing method includes mounting the semiconductor device 1 on the wiring board 30. In this step, the semiconductor device 1 is mounted on the wiring board 30, the bumps 20 and the wiring pattern 32 are brought into contact with each other, and both are electrically connected. Hereinafter, this process will be described with reference to FIGS. 4 (A) to 4 (C). First, as shown in FIG. 4A, the semiconductor device 1 may be disposed on the wiring board 30. At this time, the semiconductor device 1 and the wiring substrate 30 may be aligned so that the bumps 20 of the semiconductor device 1 and the wiring pattern 32 (electric connection portions of the wiring pattern 32) face each other. At this time, the resin material 34 may be provided on at least one of the semiconductor device 1 and the wiring substrate 30. The resin material 34 may be an insulating material. As the resin material 34, for example, NCF or NCP may be used. Then, as shown in FIG. 4B, at least one of the semiconductor device 1 and the wiring substrate 30 is pressed to bring the bump 20 and the wiring pattern 32 into contact with each other. At this time, the second convex portion 26 of the bump 20 may be brought into contact with the wiring pattern 32. Then, as shown in FIG. 4C, the second convex portion 26 is deformed. The second protrusion 26 may be deformed by further pressing at least one of the semiconductor device 1 and the wiring substrate 30. That is, the bumps 20 may be pressed by the electrode pads 14 and the wiring patterns 32 to crush the second protrusions 26 to deform the second protrusions 26 (bumps 20). Thereby, the wiring pattern 32 and the 2nd convex part 26 (bump 20) can be electrically connected reliably. In addition, the 2nd convex part 26 may be further crushed and the 1st convex part 24 may be made to contact the wiring pattern 32 (not shown). The resin material 34 may be cured to form the resin portion 36. The semiconductor device 1 may be mounted on the wiring board 30 through the above steps. Note that ultrasonic vibration or heat may be used when the second convex portion 26 is deformed. Thereby, the wiring pattern 32 and the bump 20 can be electrically connected more efficiently and reliably. The second convex portion 26 and the wiring pattern 32 may be eutectic alloy bonded.

  As described above, the bump 20 has the second convex portion 26. The height of the second convex portion 26 from the electrode pad 14 is higher than that of the first convex portion 24. Therefore, when the bump 20 and the wiring pattern 32 are brought into contact with each other, the second convex portion 26 can be brought into contact with the wiring pattern 32 first. Then, by deforming the second protrusion 26 using the wiring pattern 32, the wiring pattern 32 and the second protrusion 26 (bump 20) can be reliably electrically connected. In addition, since the external shape of the 2nd convex part 26 is smaller than the external shape of the bump 20, the 2nd convex part 26 can be changed easily. Further, since the outer shape of the second convex portion 26 is smaller than the outer shape of the bump 20, the second convex portion 26 and the wiring pattern 32 can be easily brought into contact with each other even when the resin material 34 is arranged in advance. Can be made. Therefore, according to the semiconductor device 1, the bump 20 can be electrically connected to the wiring pattern 32 easily and reliably. That is, according to the semiconductor device 1, it is possible to efficiently manufacture a highly reliable electronic module.

  The electronic module 2 shown in FIG. 5 may be formed by the above process. The electronic module 2 includes a semiconductor device 1 and a wiring board 30. In the electronic module 2, the bump 20 is in contact with and electrically connected to the wiring pattern 32. FIG. 6 shows a display device 1000 having the electronic module 2. The display device may be, for example, a liquid crystal display device or an EL (Electrical Luminescence) display device. Furthermore, as an electronic device having the electronic module 2, FIG. 7 shows a notebook personal computer 2000 and FIG. 8 shows a mobile phone 3000.

  A method for manufacturing a semiconductor device according to an embodiment to which the present invention is applied will be described below. FIG. 9A to FIG. 14 are diagrams for explaining a method for manufacturing a semiconductor device according to an embodiment to which the present invention is applied.

  The method for manufacturing a semiconductor device according to this embodiment may include preparing a semiconductor substrate 10 shown in FIGS. 9A and 9B. FIG. 9A is a schematic view of the semiconductor substrate 10. FIG. 9B is a partially enlarged view of a cross-sectional view of the semiconductor substrate 10. The semiconductor substrate 10 may be prepared in a wafer shape (see FIG. 9A). The wafer-like semiconductor substrate 10 may include a region 11 to be a plurality of semiconductor devices. However, the semiconductor substrate 10 may have a chip shape (see FIG. 1A). The semiconductor substrate 10 has a plurality of electrode pads 14. The semiconductor substrate 10 has a passivation film 16. As shown in FIG. 9B, the passivation film 16 is formed with an opening 18 exposing at least a part of each. The opening 18 may be formed so as to expose only the central portion of the electrode pad 14.

  The manufacturing method of the semiconductor device according to the present embodiment includes forming bumps 20 on the semiconductor substrate 10. The bumps 20 are formed so as to cover the openings 18 and the end portions of the passivation film 16. Although the method for forming the bump 20 is not particularly limited, a process for forming the bump 20 will be described below with reference to FIGS.

  The step of forming the bumps 20 may include forming a metal layer 42 on the semiconductor substrate 10 as shown in FIG. The metal layer 42 may be referred to as an under bump metal layer. The metal layer 42 may be formed of a single layer or a plurality of layers. The metal layer 42 may be formed so as to cover the passivation film 16. Further, the metal layer 42 may be formed so as to be in contact with the exposed portion 15 of the electrode pad 14. The metal layer 42 may be a metal layer for electrolytic plating power feeding on which the first and second conductive portions 48 and 50 are deposited. The metal layer 42 may have a titanium tungsten layer. When the metal layer 42 is formed of a plurality of layers, the outermost layer of the metal layer 42 may be a gold layer.

  The step of forming the bump 20 may include forming a resist layer 46 having an opening 44 on the metal layer 42 as shown in FIG. The opening 44 may be formed in a region for forming the bump 20. The opening 44 may be formed to be larger than the opening 18. The opening 44 may be formed only in a region overlapping with the electrode pad 14.

  The step of forming the bump 20 may include forming the first conductive portion 48 as shown in FIG. The first conductive portion 48 is formed so as to cover the opening 18 and the end portion of the passivation film 16. That is, the first conductive portion 48 may be formed so as to overlap the exposed portion 15 of the electrode pad 14. The first conductive portion 48 may be formed so as to reach a region overlapping with the end portion of the opening 18. The first conductive portion 48 may be formed inside the opening 44. That is, the first conductive portion 48 may be formed by filling the opening 44 with a conductive material. According to this, the position and shape of the first conductive portion 48 can be adjusted by controlling the position and shape of the opening 44. The first conductive portion 48 may be formed by, for example, a plating process (electrolytic plating or electroless plating). The first conductive portion 48 may be formed to have a uniform thickness. That is, the first conductive portion 48 may have the same thickness in a region overlapping with the opening 18 and a region overlapping with the passivation film 16. Thus, the first conductive portion 48 may be formed so as to have the concave portion 52 in the central portion. In other words, the height of the first conductive portion 48 from the electrode pad 14 may be formed such that the peripheral edge portion 54 is higher than the central portion (recessed portion 52).

  The step of forming the bump 20 may include forming a resist layer 58 having an opening 56 as shown in FIG. The resist layer 58 is formed so as to cover the metal layer 42 and the first conductive portion 48. The opening 56 is formed so as to overlap with the first conductive portion 48. That is, the opening 56 is formed so as to partially expose the first conductive portion 48. At this time, the opening 56 may be formed so as to expose the central portion (concave portion 52) of the first conductive portion 48. The opening 56 may be formed to be smaller than the outer shape of the first conductive portion 48.

  The step of forming the bump 20 may include forming the second conductive portion 50 as shown in FIG. The second conductive part 50 may be formed inside the opening 56. That is, the second conductive portion 50 may be formed by filling the opening 56 with a conductive material. By controlling the position and shape of the opening 56, the position and shape of the second conductive portion 50 can be adjusted. The second conductive part 50 is formed on the first conductive part 48. The second conductive portion 50 may be formed on the central portion (recessed portion 52) of the first conductive portion 48. Note that the second conductive portion 50 may be formed avoiding at least a part of a region overlapping with the opening 18 of the passivation film 16. That is, the second conductive portion 50 may be formed so as to expose at least a part of the recess 52 of the first conductive portion 48. Further, the second conductive portion 50 is formed so that the outer shape is smaller than the outer shape of the first conductive portion 48.

  Then, the bump 20 may be formed on the semiconductor substrate 10 through a step of peeling the resist layer 58 and a step of partially removing the metal layer 42 (see FIGS. 1A to 1C). . That is, the metal layer 42 and the first and second conductive portions 48 and 50 may be collectively referred to as the bump 20. The bump 20 has a recess 22, a first protrusion 24 surrounding the recess 22, and a second protrusion 26 whose height from the electrode pad 14 is higher than that of the first protrusion 24. Here, the region exposed from the second conductive portion 50 in the concave portion 52 of the first conductive portion 48 may be referred to as the concave portion 22 of the bump 20. Further, the peripheral edge portion 54 of the first conductive portion 48 may be referred to as the first convex portion 24 of the bump 20. Further, the second conductive portion 50 may be referred to as the second convex portion 26 of the bump 20. The semiconductor device 1 may be formed by the above process.

(Modification)
Hereinafter, a semiconductor device according to a modification of the embodiment to which the present invention is applied will be described. It should be noted that the contents already described are applied as much as possible in this modified example.

  The semiconductor device may have bumps 60 shown in FIG. The outer shape of the bump 60 may be larger than the electrode pad 14. According to this, the distance from the end portion of the bump 60 to the exposed portion 15 of the electrode pad 14 (open end portion of the passivation film 16) can be increased. Therefore, the moisture that has entered between the bump 60 and the passivation film 16 does not easily reach the exposed portion 15 of the electrode pad 14. Therefore, a highly reliable semiconductor device can be provided.

  The semiconductor device may have bumps 62 shown in FIGS. 16A and 16B. 16A is a top view of the bump 62, and FIG. 16B is a cross-sectional view of the bump 62. The bump 62 has a concave portion 64, a first convex portion 66 surrounding the concave portion 64, and a second convex portion 68. The second convex portion 68 may have the same width as the bump 62. At this time, the second convex portion 68 may be formed so as to partially overlap the passivation film 16. The bump 62 may have a plurality of recesses 64.

  The semiconductor device may have bumps 70 shown in FIGS. 17A and 17B. The bump 70 has a concave portion 72, a first convex portion 74 surrounding the concave portion 72, and a second convex portion 76. The second convex portion 76 may be disposed on the first convex portion 74. At this time, the second convex portion 76 may be disposed only in a region overlapping with the passivation film 16. That is, the second convex portion 76 may be arranged so as to avoid a region overlapping with the opening 18 of the passivation film 16.

  The semiconductor device may have bumps 78 shown in FIGS. 18A and 18B. The bump 78 has two or more second convex portions 76 (two in the example shown in FIGS. 18A and 18B). The second convex portion 76 may be arranged avoiding the concave portion 72. The second convex portion 76 may be arranged to avoid a region overlapping with the opening 18 of the passivation film 16. The two second convex portions 76 may be arranged so as to sandwich the concave portion 72.

  In addition, this invention is not limited to embodiment mentioned above, A various deformation | transformation is possible. For example, the present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same objects and effects). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that achieves the same effect as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.

1A to 1C are diagrams for describing a semiconductor device according to an embodiment to which the present invention is applied. 2A to 2D are diagrams for describing a semiconductor device according to an embodiment to which the present invention is applied. FIG. 3 is a diagram for explaining a method of manufacturing an electronic module according to an embodiment to which the present invention is applied. 4A to 4C are diagrams for explaining a method for manufacturing an electronic module according to an embodiment to which the present invention is applied. FIG. 5 is a diagram for explaining an electronic module according to an embodiment to which the present invention is applied. FIG. 6 is a diagram showing a display module having an electronic module according to an embodiment to which the present invention is applied. FIG. 7 is a diagram showing an electronic apparatus having an electronic module according to an embodiment to which the present invention is applied. FIG. 8 is a diagram showing an electronic apparatus having the electronic module according to the embodiment to which the present invention is applied. 9A and 9B are diagrams for explaining a method for manufacturing a semiconductor device according to an embodiment to which the present invention is applied. FIG. 10 is a diagram for explaining a method of manufacturing a semiconductor device according to an embodiment to which the present invention is applied. FIG. 11 is a diagram for explaining a method of manufacturing a semiconductor device according to an embodiment to which the present invention is applied. FIG. 12 is a diagram for explaining a method of manufacturing a semiconductor device according to an embodiment to which the present invention is applied. FIG. 13 is a diagram for explaining a method of manufacturing a semiconductor device according to an embodiment to which the present invention is applied. FIG. 14 is a diagram for explaining a method of manufacturing a semiconductor device according to an embodiment to which the present invention is applied. FIG. 15 is a diagram for explaining a semiconductor device according to a modification of the embodiment to which the present invention is applied. 16A and 16B are diagrams for describing a semiconductor device according to a modification of the embodiment to which the present invention is applied. 17A and 17B are diagrams for describing a semiconductor device according to a modification of the embodiment to which the present invention is applied. 18A and 18B are diagrams for describing a semiconductor device according to a modification of the embodiment to which the present invention is applied.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Semiconductor substrate, 11 ... Area | region, 12 ... Integrated circuit, 14 ... Electrode pad, 15 ... Exposed part, 16 ... Passivation film, 18 ... Opening, 20 ... Bump, 22 ... Recessed part, 24 ... First convex part, 26 2nd convex part, 30 ... Wiring board, 32 ... Wiring pattern, 34 ... Resin material, 36 ... Resin part, 42 ... Metal layer, 44 ... Opening, 46 ... Resist layer, 48 ... First conductive part, 50 ... Second conductive part 52 ... Concave part 54 ... Perimeter part 56 ... Opening 58 ... Resist layer 60 ... Bump 64 ... Concave part 66 ... First convex part 68 ... Second convex part 70 ... Bumps 72 ... Recesses 74 ... First convex parts 76 ... Second convex parts 78 ... Bumps 100 ... Probe

Claims (15)

A semiconductor substrate;
An electrode pad formed above the semiconductor substrate;
A passivation film having an opening exposing at least a part of the electrode pad, and formed above the semiconductor substrate;
A bump formed above the semiconductor substrate so as to cover the opening and the end thereof, and a height from the concave portion, the first convex portion surrounding the concave portion, and the electrode pad. The bump having a second convex portion higher than the convex portion of
A semiconductor device including: The semiconductor device according to claim 1,
The recess is a semiconductor device arranged inside a region overlapping with the opening. The semiconductor device according to claim 1 or 2,
The semiconductor device is configured such that the first convex portion overlaps the passivation film. The semiconductor device according to any one of claims 1 to 3,
The second convex portion is a semiconductor device arranged inside a region overlapping with the opening. The semiconductor device according to any one of claims 1 to 4,
A semiconductor device in which an outer shape of the bump is smaller than that of the electrode pad. The semiconductor device according to any one of claims 1 to 4,
A semiconductor device in which an outer shape of the bump is larger than that of the electrode pad.   An electronic module on which the semiconductor device according to claim 1 is mounted.   A semiconductor substrate having an electrode pad and a passivation film in which an opening exposing at least a part of the electrode pad is formed, a recess, a first protrusion surrounding the recess, and a height from the electrode pad. A method of manufacturing a semiconductor device, comprising: forming a bump having a second protrusion higher than the first protrusion so as to cover the opening and an end thereof. The method of manufacturing a semiconductor device according to claim 8.
A method of manufacturing a semiconductor device, wherein the bump is formed so as to be disposed inside a region where the concave portion overlaps the opening. In the manufacturing method of the semiconductor device according to claim 8 or 9,
A method of manufacturing a semiconductor device, wherein the bump is formed so that the first convex portion overlaps the passivation film. In the manufacturing method of the semiconductor device in any one of Claims 8-10,
A method of manufacturing a semiconductor device, wherein the bump is formed so as to be disposed inside a region where the second convex portion overlaps the opening. In the manufacturing method of the semiconductor device in any one of Claims 8-11,
A method of manufacturing a semiconductor device, wherein the bump is formed to be smaller than the electrode pad. In the manufacturing method of the semiconductor device in any one of Claims 8-11,
A method of manufacturing a semiconductor device, wherein the bump is formed to be larger than the electrode pad. In the manufacturing method of the semiconductor device in any one of Claims 8-13,
The step of forming the bump includes a semiconductor device manufacturing method including a plating step. Preparing a wiring board having a wiring pattern;
An electrode pad, a passivation film in which an opening exposing at least a part of the electrode pad is formed, and a bump formed so as to cover the opening and an end thereof, a recess, and a first surrounding the recess A step of preparing a semiconductor device having the bumps and the bumps having the second bumps having a height higher than the first bumps from the electrode pads;
Mounting the semiconductor device on the wiring board and bringing the bump and the wiring pattern into contact with each other to electrically connect;
Including
A method of manufacturing an electronic module, wherein in the step of mounting the semiconductor device, the second convex portion is deformed by bringing the second convex portion into contact with the wiring pattern.

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