JP2006278404A - Power supply separation layout design method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power supply separation layout design method capable of surely separating a power supply in a short processing time. <P>SOLUTION: A primitive cell library is prepared which consists of primitive cells 11, 12, and 13 which receive power supply from a power supply system wired in a different wiring layer of the same function and size. The primitive cell 11 which receives power supply from a power supply system in one wiring layer is arranged and optimized for timing, and then the arranged primitive cell 11 is replaced with the primitive cells 12 and 13. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a power supply separation layout design method for a semiconductor integrated circuit having a plurality of power supply systems.

  2. Description of the Related Art Conventionally, as a power supply separation layout design method for a semiconductor integrated circuit having a plurality of power supply systems, a method using a macro cell and a method for dividing an arrangement region are known.

  As a method using a macro cell, for example, a cell connected to one power source is arranged inside the macro cell for power source separation, and a cell connected to the other power source is arranged outside the macro cell. There has been proposed a technique of performing power source separation by handling equivalent to one power source (see Patent Document 1).

In addition, as a method of dividing the arrangement area, for example, power supply information is added to power supply wirings of different power supply systems and cells of different power supply systems, and cell arrangement is performed based on the power supply information, thereby efficiently separating power supplies A technique that is often performed has been proposed (see Patent Document 2).
JP-A-9-153548 JP-A-11-297844

  However, the technique proposed in Patent Document 1 described above requires cell placement and timing optimization processing to be performed separately inside and outside the macro cell. For this reason, there exists a problem that processing time is long.

  Further, in the technique proposed in Patent Document 2, it is difficult to add power supply information to a cell to be added at the time of timing optimization processing. Therefore, a cell to be arranged in a region of a predetermined power supply system has another power supply. There is a problem that a cell to be arranged in a system area or a cell to be arranged in another power system area is arranged in a predetermined power system area.

  In view of the above circumstances, an object of the present invention is to provide a power supply separation layout design method capable of reliably performing power supply separation in a short processing time.

The power source separation layout design method of the present invention that achieves the above object is as follows.
Prepare a primitive cell library that receives power supply from power supply systems that have the same function and the same size and are wired to different wiring layers,
In constructing a circuit having a plurality of power supply systems divided into wiring layers, primitive cells that receive power supply from one power supply system are arranged regardless of the wiring layer of the power supply system in which each primitive cell receives power supply. ,
Perform an operation check simulation,
Thereafter, the arranged primitive cell is replaced with a primitive cell that receives power supply from a wiring layer of a power supply system to which the primitive cell is to be supplied with power.

  The power supply separation layout design method of the present invention provides a primitive cell library that receives power supply from power supply systems that have the same function and size and are wired to different wiring layers, and supplies power from the power supply system of one wiring layer. This is a method in which a primitive cell that receives power is placed and an operation check simulation is performed, and then the placed primitive cell is replaced with a primitive cell that receives power from the wiring layer of the power supply system to which the primitive cell is to be supplied with power. . For this reason, arrangement and operation check simulations can be executed collectively. Therefore, power supply separation can be performed in a short processing time compared to the technique proposed in Patent Document 1 in which cell placement and timing optimization processing are separately performed inside and outside the macro cell. In addition, as compared with the technique proposed in Patent Document 2 in which a cell to be arranged in a predetermined power supply system region may be arranged in another power supply system region, power supply separation is surely performed. Can do. Therefore, it is possible to provide a power supply separation layout design method capable of reliably performing power supply separation in a short processing time.

  Here, it is preferable to perform a simulation of signal transmission timing as the operation check simulation.

  As an operation confirmation simulation, timing optimization processing can be performed by simulating the timing of signal transmission.

  According to the power supply separation layout design method of the present invention, power supply separation can be reliably performed in a short processing time.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a schematic diagram showing an example of a CAD system to which an embodiment of a power supply separation layout design method of the present invention is applied.

  A computer generally called a workstation or a personal computer can be used for the CAD system 100 shown in FIG.

  The CAD system 100 includes a CPU (Central Processing Unit), a RAM (Random Access Memory), a hard disk, etc., and a display device that displays images and character strings on the display screen 102a according to instructions from the main body 101. 102, by specifying an arbitrary position on the display screen 102a by specifying a keyboard 103 for inputting an operator's instruction to the CAD system 100, an instruction corresponding to the icon or the like displayed at that position at the time of the designation is given. A mouse 104 for inputting is provided.

  The main body 101 further has a flexible disk (not shown), a flexible disk loading port 101a into which a CD-ROM 700 is loaded, and a CD-ROM loading port 101b. A flexible disk and a CD-ROM drive for accessing the flexible disk loaded from the loading ports 101a and 101b by driving the CD-ROM 700 are also incorporated.

  FIG. 2 is a hardware configuration diagram of the CAD system having the appearance shown in FIG.

  2 shows a CPU 111, RAM 112, hard disk controller 113, FD (flexible disk) drive 114, CD-ROM drive 115, mouse controller 116, keyboard controller 117, and display controller 118. They are connected to each other by a bus 110.

  As described with reference to FIG. 1, the FD drive 114 and the CD-ROM drive 115 access the flexible disk 710 and the CD-ROM 700 loaded from the flexible disk loading slot 101a and the CD-ROM loading slot 101b, respectively. It is.

  2 also shows a hard disk 120 accessed by the hard disk controller 113, a mouse 104 controlled by the mouse controller 116, a keyboard 103 controlled by the keyboard controller 117, and a display device 102 controlled by the display controller 118. Has been.

  FIG. 3 is a conceptual configuration diagram of the CAD system shown in FIGS. 1 and 2.

  FIG. 3 shows the hard disk 120, the computer unit 130, the key operation device 140, and the display device 102 that constitute the CAD system 100 described above.

  The hard disk 120 stores layout / library information 120a including layout data and library data, power connection information 120b, and timing constraint information 120c.

  The computer unit 130 includes a calculation unit 150 including a CPU 111 and a RAM 112, and an input / output control unit 160 including a hard disk controller 113, an FD drive 114, a CDROM drive 115, a mouse controller 116, a keyboard controller 117, and a display controller 118. .

  Although the details will be described later in the RAM 112 of the arithmetic unit 150, a power source wiring unit 151, an automatic placement and routing unit 152, a timing optimization unit 153, and a cell replacement as a program for executing the power source separation layout design method of the present invention. 154, a timing constraint determination unit 155, and a power connection information determination unit 156 are provided.

  The key operation device 140 includes a mouse 104 and a keyboard 103.

  FIG. 4 is a diagram showing a procedure of the power supply separation layout design method executed in the CAD system shown in FIG. 3, and FIG. 5 is a diagram showing a primitive cell library prepared in the power supply separation layout design method shown in FIG. .

  In the power supply separation layout design method of this embodiment, a primitive cell library shown in FIG. 5 is prepared. FIG. 5 shows primitive cells 11, 12, and 13 constituting a primitive cell library. These primitive cells 11, 12, and 13 are examples of primitive cells that have the same function and the same size and receive power supply from power supply systems wired in different wiring layers.

  Specifically, the primitive cell 11 is a CMOS inverter gate having a gate 11a and a drain wiring 11b, and also has an active area (diffusion layer) shown by a dotted line and a well (not shown). The primitive cell 11 includes a first power supply wiring layer 11V and a first ground wiring layer 11G.

  The primitive cell 12 has the same configuration as that of the primitive cell 11, but the first power supply wiring layer 11V and a part of the first power supply wiring layer 11V are used as wiring for receiving power supply. The second power wiring layer 12V is disposed so as to overlap with the second power wiring layer 12V. Furthermore, it has the 1st ground wiring layer 11G and the 2nd ground wiring layer 12G arrange | positioned so that it may overlap with a part on this 1st ground wiring layer 11G.

  Further, the primitive cell 13 has the same configuration as that of the primitive cell 11, but the first power supply wiring layer 11V and a part of the first power supply wiring layer 11V are used as wirings for receiving power supply. And a third power supply wiring layer 13V disposed so as to overlap with a part of the second power supply wiring layer 12V. Furthermore, the first ground wiring layer 11G, the second ground wiring layer 12G arranged to overlap with a part on the first ground wiring layer 11G, and a part on the second ground wiring layer 12G And a third ground wiring layer 13G disposed so as to overlap with each other. Each power supply wiring layer and ground wiring layer are connected to each other by a via contact at a part of which overlaps.

  Here, the first power wiring layer 11V and the first ground wiring layer 11G, the second power wiring layer 12V and the second ground wiring layer 12G, the third power wiring layer 13V and the third ground wiring layer 13G. May be the same wiring layer or different wiring layers, but are preferably the same wiring layer. In the present embodiment, the first power wiring layer 11V and the first ground wiring layer 11G are first metal wiring layers.

  In addition, although an inverter gate has been described as an example of a primitive cell, the primitive cell may have any function.

  First, power supply wiring is performed in step S1 shown in FIG. Specifically, power supply wiring is performed by the power supply wiring unit 151 and the power supply connection information determination unit 156 based on the layout library information 120a and the power supply connection information 120b shown in FIG.

  FIG. 6 is a diagram showing the power supply wiring performed in step S1 shown in FIG.

  FIG. 6A shows different power supply wiring layers 11V, 12V, and 13V arranged on top of each other (see FIGS. 7 to 9 described later) designed by this power supply separation layout design method. The figure which looked at from the upper part is shown. Further, FIG. 6B shows a view of different ground wiring layers 11G, 12G, and 13G arranged in the middle of the layout, which are arranged to overlap each other, as viewed from above. Further, FIG. 6 (c) shows different power supply wiring layers 11V, 12V, and 13V, which are arranged at the lower part of the layout and are arranged to overlap each other. In these figures, the wiring layers are displayed so as to be distinguished from each other. Here, the wiring layers 11V and 11G receive power from the first power supply system. The wiring layers 12V and 12G are supplied with power from the second power supply system. Furthermore, the wiring layers 13V and 13G are supplied with power from the third power supply system.

  Furthermore, automatic placement and routing is performed in step S2 shown in FIG. Specifically, based on the layout library information 120a and the timing constraint information 120c shown in FIG. 3, the automatic placement and routing unit 152 and the timing constraint determination unit 155 perform the first power supply wiring layer 11V and the first ground wiring layer. Automatic placement and routing of the primitive cell 11 having 11G is performed.

  FIG. 7 is a diagram showing the placement of primitive cells by automatic placement and routing performed in step S2 shown in FIG.

  FIG. 7 shows five primitive cells 11 having the first power supply wiring layer 11V and the first ground wiring layer 11G shown in FIG. However, the lower two are arranged upside down. The first power supply wiring layer 11V in the primitive cells 11 is connected to the power supply wiring layer 11V that receives power supply from the first power supply system, and the first ground wiring layer 11G in the cell is connected to the first power supply layer 11V. It is connected to a ground wiring layer 11G that receives power supply from the system.

  Next, in step S3, timing optimization is performed. Specifically, the timing optimization unit 153 and the timing constraint determination unit 155 perform timing optimization based on the timing constraint information 120c shown in FIG.

  Further, in step S4, the power supply system is specified.

  FIG. 8 is a diagram for explaining how the power supply system is specified in step S4 shown in FIG.

  Here, an example in which two primitive cells 11 (referred to as a first primitive cell and a second primitive cell) indicated by arrows A and B in FIG. 8 are replaced with primitive cells 12 and 13 will be described. In step S4, the power connection information determination unit 156 identifies the second power system connected to the second power wiring layer 12V and the second ground wiring layer 12G included in the primitive cell 12. Further, the power supply connection information determination unit 156 specifies the third power supply system connected to the third power supply wiring layer 13V and the third ground wiring layer 13G included in the primitive cell 13.

  Further, in step S5, cell replacement is performed. Specifically, the arranged first and second primitive cells are replaced with primitive cells 12 and 13 by the cell replacement unit 154 and the power connection information determination unit 156.

  FIG. 9 is a diagram showing the arrangement of primitive cells including the primitive cell whose cell is replaced in step S5.

  FIG. 9 shows primitive cells 12 and 13 that have been replaced in step S5. The power supply wiring layer 12V included in the primitive cell 12 is connected to the power supply wiring layer of the second power supply system, and the ground wiring layer 12G is connected to the ground wiring layer of the second power supply system.

  The power supply wiring layer 13V of the primitive cell 13 is connected to the wiring layer of the third power supply system, and the ground wiring layer 13G is connected to the ground wiring layer of the third power supply system. In this way, a series of procedures is completed.

  The power supply separation layout design method of the present embodiment prepares a primitive cell library including primitive cells 11, 12, and 13 that receive power supply from power supply systems that have the same function and size and are wired to different wiring layers. A method of arranging a primitive cell 11 that receives power supply from a power supply system of one wiring layer and optimizing timing, and then replacing the arranged first and second primitive cells 11 with primitive cells 12 and 13 It is. For this reason, arrangement and timing optimization can be executed collectively. Therefore, the power supply can be reliably separated in a short processing time.

It is a schematic diagram showing an example of a CAD system to which an embodiment of a power supply separation layout design method of the present invention is applied. It is a hardware block diagram of the CAD system which has the external appearance shown in FIG. FIG. 3 is a conceptual configuration diagram of the CAD system shown in FIGS. 1 and 2. It is a figure which shows the procedure of the power supply isolation | separation layout design method performed with the CAD system shown in FIG. FIG. 5 is a diagram showing an example of a primitive cell library prepared in the power supply separation layout design method shown in FIG. 4. It is a figure which shows the power supply wiring performed in procedure S1 shown in FIG. It is a figure which shows arrangement | positioning of the primitive cell by the automatic arrangement | positioning wiring performed in procedure S2 shown in FIG. It is a figure for demonstrating a mode that the power supply system performed in procedure S4 shown in FIG. 4 is performed. It is a figure which shows arrangement | positioning of the primitive cell containing the primitive cell by which the cell replacement was performed in procedure S5.

Explanation of symbols

11, 12, 13 Primitive cell 11a Gate 11b Drain 11V First power wiring layer 11G First ground wiring layer 12V Second power wiring layer 12G Second ground wiring layer 13V Third power wiring layer 13G Third power Ground wiring layer 100 CAD system 101 Main unit 101a Flexible disk loading slot 101b CD-ROM loading slot 102 Display device 102a Display screen 103 Keyboard 104 Mouse 110 Bus 111 CPU
112 RAM
113 Hard disk controller 114 FD drive 115 CDROM drive 116 Mouse controller 117 Keyboard controller 118 Display controller 120 Hard disk 120a Layout library information 120b Power connection information 120c Timing constraint information 130 Computer unit 140 Key operation device 150 Arithmetic unit 151 Power supply wiring unit 152 Automatic arrangement Wiring unit 153 Timing optimization unit 154 Cell replacement unit 155 Timing constraint determination unit 156 Power connection information determination unit 160 Input / output control unit 700 CD-ROM
710 Flexible disk

Claims (2)

Prepare a primitive cell library that receives power supply from power supply systems that have the same function and the same size and are wired to different wiring layers,
In constructing a circuit having a plurality of power supply systems divided into wiring layers, primitive cells that receive power supply from one power supply system are arranged regardless of the wiring layer of the power supply system in which each primitive cell receives power supply. ,
Perform an operation check simulation,
Then, the arranged primitive cell is replaced with a primitive cell that receives power supply from a wiring layer of the power supply system to which the primitive cell should receive power supply.   The power supply separation layout design method according to claim 1, wherein a signal transmission timing simulation is performed as the operation check simulation.

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