JP2006268956A - Nonvolatile semiconductor memory device - Google Patents

Abstract

In a MNOS type and MONOS type nonvolatile semiconductor memory device, there is a problem that a threshold voltage changes with the passage of time and stored information cannot be read correctly.
The present invention includes a measurement circuit for measuring a thermal equilibrium threshold voltage of a nonvolatile memory element, a readout circuit for inputting a measurement result by the measurement circuit, and a control means for controlling these circuits. . The control means performs control so that the thermal equilibrium state threshold voltage of the nonvolatile memory element measured by the measurement circuit matches the sense level of the readout circuit. With such a structure, it is possible to lengthen the time that the nonvolatile memory element holds information.
[Selection] Figure 1

Description

  The present invention relates to a nonvolatile semiconductor memory device capable of electrically rewriting information.

  Conventionally, as a nonvolatile semiconductor memory device, an MNOS (Metal-Nitride-Oxide-Semiconductor) type or a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) having different types of insulating films between a gate electrode and a semiconductor surface. Types of storage elements are known. These memory elements have a bound level of electric charge in the interface of the laminated insulating film and in the film.

The state in which electrons are accumulated in the bound level, that is, the threshold voltage in the written state of information is Vtw, the state in which holes are accumulated in the bound level, that is, the threshold voltage in the erased state of information is Vte, and the bound level The threshold voltage in a state where neither electrons nor holes are accumulated, that is, the thermal equilibrium state threshold voltage is called V0.
Here, when the value of the voltage Vcg applied to the gate electrode when reading information is set so that the relationship of Vte <Vcg <Vtw holds, the drain current of the memory element does not flow in the information writing state, and the information Since it flows in the erased state, it is possible to determine the information writing state and the erased state.

  However, the values of Vtw and Vte are not always constant. The storage element gradually approaches a thermal equilibrium state that is a stable state of energy with the passage of time. That is, since the charge accumulated in the bound level is released with the passage of time, the values of Vtw and Vte approach V0, and finally Vtw = Vte = V0.

  In the process in which the values of Vtw and Vte approach V0, if the relationship of Vte <Vcg <Vtw does not hold, information cannot be read correctly.

  Among the above, the difference between the values of Vtw and Vcg or the difference between the values of Vte and Vcg is called a read margin. There are several proposals for expanding the read margin (see Patent Document 1, for example).

  The prior art shown in Patent Document 1 will be described. FIG. 3 is a configuration diagram of a reading device of a nonvolatile semiconductor memory device in the prior art.

  In FIG. 3, 1 is a memory transistor, 2 is a read circuit, 3 is a pull-up load circuit, 4 is a reference voltage generation circuit, and 5 is a voltage comparison circuit.

  FIG. 3 shows a case where the source of the memory transistor 1 is set to the ground potential, and the power supply voltage Vcc is connected to the pull-up load circuit 3. In such a case, by inputting the read signal S1 to the voltage comparison circuit 5, the data S2 is output from the read circuit 2 according to the information written in the memory transistor 1.

The read device of the nonvolatile semiconductor memory device having such a configuration reads information by applying a read voltage Vcg to the gate of the memory transistor 1. The information read once is fed back to increase or decrease the value of the read voltage Vcg, and the read information is repeatedly read, whereby the difference between the initial value of the read voltage Vcg and the threshold voltage of the memory transistor 1 is obtained. Even if is small, information can be read accurately.

  Here, the initial value of the read voltage Vcg is the reference voltage Vref. The value of the reference voltage Vref is set to an intermediate value between the threshold voltage Vtw immediately after writing to the memory transistor 1 and the threshold voltage Vte immediately after erasing.

When the value of the threshold voltage of the memory transistor 1 is higher than the value of the reference voltage Vref, the read margin is widened by feeding back the information read once and lowering the value of the read voltage Vcg.
By widening the read margin, information is discriminated in a state where the drain current of the memory transistor 1 is further reduced, and the read accuracy is improved.

Next, when the value of the threshold voltage of the memory transistor 1 is lower than the value of the reference voltage Vref, the read margin is widened by feeding back the information read once and increasing the value of the read voltage Vcg.
By widening the read margin, information is discriminated in a state where the drain current of the memory transistor 1 is further increased, and the read accuracy is improved.

  The prior art disclosed in Patent Document 1 is to increase or decrease the value of the read voltage Vcg according to the value of the threshold voltage of the memory transistor. Thereby, it is possible to widen the read margin as compared with the conventional method in which the value of the read voltage Vcg is constant.

JP 2001-195891 A (page 3-6, FIG. 1)

In the prior art disclosed in Patent Document 1, since the value of the read voltage Vcg is repeatedly applied to the gate of the memory transistor 1, the threshold voltage value of the memory transistor 1 fluctuates and the reliability of information is increased. There is a problem that it falls.
Although it has become possible to widen the read margin, when the time has elapsed since the memory transistor 1 is still written or erased and the relationship of Vte <Vref <Vtw no longer holds, the information is accurately obtained. The problem of not being able to read is not solved.

  The problem to be solved by the present invention is that in the method of setting the read voltage based on the threshold voltage value immediately after writing and erasing, the threshold voltage value fluctuates over time. Since a read margin cannot be ensured, the memory element cannot hold information for a long time.

  In order to solve the above problems, the present invention adopts the following configuration.

A non-volatile storage element; a measurement circuit that includes a memory bit and measures a thermal equilibrium threshold voltage of the memory bit; a read circuit that can change a sense level when reading information from the non-volatile storage element; and a control unit. And
The control means controls the read circuit so that the sense level of the read circuit matches the thermal equilibrium threshold voltage of the memory bit of the measurement circuit.

The measurement circuit includes a memory bit, a variable voltage generation circuit, a memory bit read circuit, and a determination unit.
The memory bit is a memory element having the same structure as the nonvolatile memory element,
The variable voltage generation circuit outputs a plurality of write voltages, writes information to the memory bits using the write voltages,
The memory bit read circuit reads information of a memory bit corresponding to the write voltage,
The determination means measures the thermal equilibrium threshold voltage of the memory bit using the information of the memory bit.

  The control means is characterized by giving an instruction to the readout circuit in accordance with the value of the thermal equilibrium state threshold voltage, and performing control so that the sense level of the readout circuit matches the value of the thermal equilibrium state threshold voltage.

  The readout circuit includes a regulator circuit having a variable resistor, a load P-channel transistor, and a comparator.

  The nonvolatile memory element is an element having a multilayer structure film including an ONO film.

According to the nonvolatile semiconductor memory device of the present invention, the sense level of the reading circuit is adjusted by adjusting the load when determining information depending on whether or not the drain current of the nonvolatile memory element flows to the comparator. The threshold voltage in the state in which all charges are released from the binding order, that is, the value of the thermal equilibrium state threshold voltage is set.
By adopting such a configuration, the charge is gradually released from the binding order of the nonvolatile memory element over time, and even if the threshold voltage fluctuates, immediately before it matches the thermal equilibrium state threshold voltage. Since the reading margin can be secured until this time, it is possible to lengthen the time that the nonvolatile memory element holds information.

  In addition, since the read margin is secured by adjusting the load, the value of the read voltage applied to the gate of the nonvolatile memory element is increased or decreased in order to ensure the read margin as in the prior art disclosed in Patent Document 1. Thus, it is not necessary to repeatedly apply the read voltage and the read voltage can be fixed. Furthermore, by adjusting the impurity concentration on the semiconductor surface so that the threshold voltage in the information writing state is a positive value and the threshold voltage in the information erasing state is a negative value, the read voltage is reduced. The voltage can be set to 0 V, and there is an advantage that fluctuation of the value of the threshold voltage caused by applying the read voltage to the gate can be prevented.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a configuration diagram of a reading device of a nonvolatile semiconductor memory device of the present invention.

[Description of configuration: FIG. 1]
In FIG. 1, 10 is a measurement circuit, 20 is a control means, 30 is a readout circuit, and 40 is a nonvolatile memory element. Although not shown, there are a plurality of nonvolatile memory elements 40, which are 40-1 to 40-m.

The measurement circuit 10 includes a variable voltage generation circuit 11, a memory bit read circuit 12, a determination unit 13, and a memory bit 14. Although not shown, there are a plurality of memory bits 14, which are 14-1 to 14-n. Further, the write voltage generated by the variable voltage generation circuit 11 is VP, and the VP corresponding to each memory bit is Vp-1 to Vp-n.
The threshold voltage of the memory bit 14 is set to V1, and the threshold voltage of the memory bit 14 after the elapse of time is set to V2. The threshold voltages corresponding to the memory bits 14-1 to 14-n are V1-1 to V1-n and V2-1 to V2-n, respectively.

The read circuit 30 includes a regulator circuit 32 having a variable resistor 31, a load P-channel transistor 33, and a comparator 34.
The load P-channel transistor 33 is used as a load when determining information stored in the nonvolatile memory element 40. Information S20 of the nonvolatile memory element 40 is output from the comparator 34.

  The memory bits 14-1 to 14-n and the non-volatile memory elements 40-1 to 40-m are all memory elements having the same structure. For example, a MONOS nonvolatile memory element that is a memory element having a multilayer structure film including an ONO (Oxide-Nitride-Oxide) film can be used.

[Description of overall operation: Fig. 1]
The nonvolatile semiconductor memory device of the present invention applies the write voltages Vp-1 to Vp-n to the memory bits 14-1 to 14-n, respectively.
Subsequently, the memory bit read circuit 12 reads the threshold voltages V1-1 to V1-n of the memory bits 14-1 to 14-n.
Then, after time elapses, the memory bit read circuit 12 reads the threshold voltages V2-1 to V2-n of the memory bits 14-1 to 14-n again.

  The values of threshold voltages V1-1 to V1-n and V2-1 to V2-n are sent to determination means 13. The judging means 13 obtains the value of the thermal equilibrium state threshold voltage V0, which is a common value for the memory bits 14-1 to 14-n, by a method described later. This V0 is also the thermal equilibrium state threshold voltage of the nonvolatile memory elements 40-1 to 40-m, which are memory elements having the same structure as the memory bits 14-1 to 14-n.

The value of the thermal equilibrium state threshold voltage V0 is sent to the control means 20. The control means 20 determines the value of the voltage Vpg applied to the gate of the load P-channel transistor 33 in order to make the sense level of the readout circuit 30 coincide with the thermal equilibrium state threshold voltage V0.
Further, a signal S10 corresponding to the determined value of the voltage Vpg is sent from the control means 20 to the regulator circuit 32.

  The regulator circuit 32 receives the signal S 10 from the control means 20, generates a voltage Vpg by adjusting the resistance value of the variable resistor 31, and applies it to the gate of the load P-channel transistor 33.

  By applying the voltage Vpg to the gate of the load P-channel transistor 33, the sense level of the read circuit 30 matches the thermal equilibrium state threshold voltage V0 of the nonvolatile memory elements 40-1 to 40-m.

With such a configuration, the read margin between the threshold voltage Vtw after writing and the threshold voltage Vte after erasure of the nonvolatile memory elements 40-1 to 40-m and the sense level of the read circuit 30 is achieved. Can be maximized.
Further, even in the process in which the threshold voltage values of the nonvolatile memory elements 40-1 to 40-m converge to the thermal equilibrium threshold voltage V0 over time, Vte until just before the complete match. Since the relationship of <sense level <Vtw holds and it is possible to discriminate writing and erasing, it is possible to lengthen the time for holding information.

[Description of the operation of the judging means: FIG. 2]
Next, the threshold voltage V1-1 to V1-n immediately after the write voltages Vp-1 to Vp-n are applied to the memory bits 14-1 to 14-n in the determination unit 13 and time have elapsed. The principle for obtaining the value of the thermal equilibrium state threshold voltage V0 from the information of the threshold voltages V2-1 to V2-n after the operation will be described.

FIG. 2 is an explanatory diagram showing the change of the threshold voltage value of the memory bit of the present invention over time, and schematically shows how the threshold voltage changes over time. It is. The vertical axis represents the threshold voltage value, and the horizontal axis represents the passage of time since information was written to the memory bits.
Here, since the non-volatile memory elements 40-1 to 40-m and the memory bits 14-1 to 14-n in FIG. 1 are memory elements having the same structure, a change in the value of the threshold voltage with the passage of time. Is the same.

The write voltages Vp-1 to Vp-n generated by the variable voltage generation circuit 11 in FIG. 1 are applied to the memory bits 14-1 to 14-n, respectively, so that the memory bits 14-1 to 14-n are updated. The threshold voltage values are V1-1 to V1-n.
With the passage of time thereafter, the threshold voltage values of the memory bits 14-1 to 14-n change to V2-1 to V2-n. The value always changes from V1-1 to V1-n to V2-1 to V2-n in a direction approaching the thermal equilibrium threshold voltage V0.

Therefore, when V0 is between V1-a and V1- (a + 1), V2-1 to V2-a have a threshold voltage value in the negative direction with respect to V1-1 to V1-a. V2- (a + 1) to V2-n change in a positive direction with respect to V1- (a + 1) to V1-n.
Here, a is an arbitrary integer of 1 or more and less than n.

Based on the above principle, it is understood that the thermal equilibrium state threshold voltage V0 is a value between V2-a and V2- (a + 1).
Furthermore, the value of V0 can be obtained with higher accuracy by finely setting the values of the write voltages Vp-1 to Vp-n.
Further, the memory bits 14-1 to 14-n may be heated at a high temperature. In that case, since the amount of change in the value of the threshold voltage for the same elapsed time increases as compared with the case where no heating is performed, the difference between the values of V2-a and V2- (a + 1) is reduced and higher accuracy is achieved. Thus, the value of V0 can be obtained.

  The above is a case where V0 is between V1-1 and V1-n. When V2-1 to V2-n all change in the negative direction with respect to V1-1 to V1-n, V0 is a value on the minus side of V2-n. The same measurement is performed again by decreasing the values of the write voltages Vp-1 to Vp-n.

  Further, when the threshold voltage values of all of V2-1 to V2-n change in the positive direction with respect to V1-1 to V1-n, V0 is a value on the plus side of V2-1. Therefore, the same measurement is performed again by increasing the values of the write voltages Vp-1 to Vp-n.

  In the above description, the case where there are a plurality of memory bits 14-1 to 14-n has been described. For example, if the memory bit is only 14-1, a total of n measurements are performed from the measurement where the value of the write voltage applied to the memory bit 14-1 is Vp-1 to the measurement where Vp-n. Thus, it is possible to specify the value of V0 in the same manner.

  Further, since the nonvolatile memory elements 40-1 to 40-m and the memory bits 14-1 to 14-n are memory elements having the same structure, the threshold voltage value with respect to the passage of time shown in FIG. The change is the same, and the value of V0 is also common. Therefore, a part of the nonvolatile memory elements 40-1 to 40-m can be used instead of the memory bits 14-1 to 14-n. For example, the nonvolatile memory elements 40-1 to 40-n are used instead of the memory bits 14-1 to 14-n. With such a configuration, it is possible to specify the value of V0 in the same manner, and the space efficiency of the nonvolatile semiconductor memory device can be improved.

  As described above, according to the present invention, it is possible to lengthen the time for which the memory element holds information.

  Since the nonvolatile semiconductor memory device of the present invention can increase the time for retaining information without changing the constituent elements of the memory element such as the film structure, dimensions, and material of the memory element, the memory element It is possible to replace the semiconductor device in which is used. In particular, it is suitable for computer devices and electronic devices that need to store information for a long time.

It is a block diagram of the reading device of the nonvolatile semiconductor memory device of the present invention. It is a figure which shows typically a mode that the value of the threshold voltage of the memory bit of this invention changes with progress of time. It is a block diagram of the read-out apparatus of the non-volatile semiconductor memory device of a prior art example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Memory transistor 2 Reading circuit 3 Pull-up load circuit 4 Reference voltage generating circuit 5 Voltage comparison circuit 10 Measuring circuit 11 Variable voltage generating circuit 12 Memory bit reading circuit 13 Judgment means 14-1 to 14-n Memory bit 20 Control means 30 Reading Circuit 31 Variable resistance 32 Regulator circuit 33 Load P-channel transistor 34 Comparator 40-1 to 40-m Nonvolatile memory element

Claims (5)

Nonvolatile memory element, measurement circuit having memory bit and measuring thermal equilibrium threshold voltage of memory bit, read circuit capable of varying sense level when reading information of nonvolatile memory element, and control means And
The non-volatile semiconductor memory device, wherein the control means controls the sense level of the read circuit to coincide with a thermal equilibrium threshold voltage of the memory bit measured by the measurement circuit. The measurement circuit includes the memory bit, a variable voltage generation circuit, a memory bit read circuit, and a determination unit.
The memory bit is a storage element having the same structure as the nonvolatile storage element,
The variable voltage generation circuit outputs a plurality of write voltages, writes information to the memory bits using the write voltages,
The memory bit read circuit reads information of the memory bit corresponding to the write voltage;
The nonvolatile semiconductor memory device according to claim 1, wherein the determination unit measures a thermal equilibrium state threshold voltage of the memory bit using information of the memory bit.   The control means gives an instruction to the readout circuit in accordance with the value of the thermal equilibrium state threshold voltage, and controls the sense level of the readout circuit to match the value of the thermal equilibrium state threshold voltage. The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is a non-volatile semiconductor memory device.   4. The nonvolatile semiconductor memory device according to claim 1, wherein the read circuit includes a regulator circuit having a variable resistor, a load P-channel transistor, and a comparator. 5.   5. The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile memory element is an element having a multilayer structure film including an ONO film. 6.

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