JP2006261812A - Transmission controller and device for converting sampling frequency - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a transmission controller rapidly converging the residual quantity of data at a proper value in conformity with the fluctuation of the residual quantity of the data of an FIFO buffer resulting from a jitter in a transmission controller conducting asynchronous transmission using the FIFO buffer. <P>SOLUTION: The FIFO buffer 10 stores input data in an area specified by a writing address, and outputs the stored data into an area specified by a reading address. A writing control section 30 updates input-phase information composed of (m) bits, and supplies the FIFO buffer 10 with a bit row composed of a high-order (j) bit (j<m) in the input-phase information as the writing address. A reading control section 40 updates output-phase information composed of the (m) bits, and supplies the FIFO buffer 10 with the bit row composed of the high-order (j) bit in the output-phase information as the reading address. A PLL 80 controls the updating speed of the input-phase information so that the input-phase information is updated by phase synchronizing with the output-phase information changed in response to a reading-requirement signal RR. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a transmission control device having a jitter absorption function and a sampling frequency conversion device using the transmission control device.

In the field of digital audio and the like, data is often exchanged between two devices that operate in synchronization with independent clocks. In such a case, the preceding device outputs data in synchronization with the clock of the device, and the subsequent device inputs data in synchronization with the clock of the device, but the clocks of both devices have jitter. It is common to do. Thus, a FIFO (First-In First-Out) buffer for jitter absorption is inserted between both devices, and data transmission is often performed via this FIFO. In addition to using such a FIFO, the remaining data amount in the FIFO is monitored so that the FIFO does not overflow or underflow due to clock jitter. Is increased, for example, the data output speed in the FIFO is increased, and when the remaining amount of data is lower than an appropriate value, for example, PLL (Phase Locked Loop) control for decreasing the data output speed in the FIFO is performed. In some cases. In the field of digital audio and the like, devices corresponding to various sampling frequencies are provided, and thus devices with different sampling frequencies are often connected. In such a case, for example, a sampling frequency converter that matches the sampling frequency of the sample data output from the preceding device with the sampling frequency of the succeeding device is used. Patent Document 1 discloses a technique in which the above-described FIFO and PLL control are applied to a sampling frequency converter.
JP-A-11-55075

  By the way, in the conventional technique described above, in order to quickly converge the fluctuation of the remaining data amount of the FIFO due to the jitter to an appropriate value, the resolution of the remaining data amount of the FIFO used for the PLL control is increased, and the remaining data amount Therefore, it is necessary to finely adjust the data output speed in the FIFO in response to the subtle changes. However, the resolution of the remaining data amount depends on the number of FIFO stages, and in order to increase this, it is necessary to increase the number of FIFO stages. For this reason, the conventional transmission control apparatus uses a FIFO with a large number of stages in order to improve the response to jitter and quickly converge the remaining data amount of the FIFO to an appropriate value. However, using such a FIFO with a large number of stages has a problem of increasing the circuit scale of the transmission control device.

  The present invention has been made in view of the above-described circumstances, and quickly converges the remaining data amount to an appropriate value in response to fluctuations in the remaining data amount of the FIFO caused by jitter without causing an increase in circuit scale. It is an object of the present invention to provide a transmission control device that can be used and a sampling frequency conversion device using the same.

The present invention stores input data in an area specified by a write address and outputs data stored in an area specified by a read address, and an input composed of m bits (m is a plurality). Write control means for updating the phase information and supplying the storage means with a bit string consisting of upper j bits (j <m) in the input phase information as the write address, and an output phase consisting of m bits (m is a plurality) Read control means for updating the information and supplying a bit string consisting of the upper j bits (j <m) in the output phase information to the storage means as the read address, and a phase in one of the input phase information or the output phase information The other of the input phase information or the output phase information is updated in synchronization. To provide a transmission control device comprising a transmission control apparatus characterized by comprising a phase synchronizing means for controlling the other update rate forces the phase information or the output phase information.
The present invention also provides a sampling frequency conversion device using such a transmission control device.
According to this invention, the operation for phase synchronization for converging the remaining data amount to an appropriate value has more bits than the write address and read address supplied to the storage means, and the input phase information and output phase with high resolution. Done based on information. Therefore, the operation of phase-synchronizing one of the input phase information and the output phase information with the other can be performed with high resolution without incurring a large-scale storage means, and can respond immediately to fluctuations in the amount of remaining data due to jitter. The remaining data amount can be quickly returned to an appropriate value.

The best mode for carrying out the present invention will be described below with reference to the drawings.
<First Embodiment>
FIG. 1 is a block diagram showing a configuration of a sampling frequency conversion apparatus according to the first embodiment of the present invention. This sampling frequency converter is roughly divided into a transmission control device 100A, an interpolation unit 200A, and an interface 300A.

  As illustrated in FIG. 2, the interpolation unit 200 </ b> A includes an n-stage shift register 201, an interpolation coefficient generation unit 202, and a convolution operation unit 203. Here, the shift register 201 sequentially fetches the data of the first sampling frequency from the preceding stage of the interpolation unit 200A, and holds the past n data strings as an input data string for interpolation calculation.

The interpolation ratio generator 202 is supplied with the interpolation ratio Δt from the transmission control device 100A. This interpolation ratio Δt indicates the phase of the sampling point of data to be generated in the interpolation unit 200A. More specifically, in the present embodiment, as illustrated in FIG. 3, the interpolation unit 200 _</ b _{> A} performs data D _{m + 1} and data D in the interpolation calculation input data strings D _{0 to} D _n−1 held in the shift register 201. _The data P _k existing between _m and _m is _obtained by interpolation, and the interpolation ratio Δt is interpolated at any position between the sampling point of the data D _{m + 1 and} the sampling point of the data D _m on the time axis. Indicates whether there is a sampling point of the data _Pk to be _obtained . The interpolation coefficient generator 202 is, for example, a ROM that stores interpolation coefficient sequences corresponding to various interpolation ratios Δt. The interpolation coefficient generation unit 202 stores interpolation coefficient sequences a _{0 to an n−1} corresponding to the interpolation ratio Δt given from the transmission control device 100A. Output.

The convolution operation unit 203 receives the input data string D _{0 to} D _n−1 for interpolation calculation held in the shift register 201 in response to the data input permission signal IE synchronized with the main clock φ from the transmission control device 100A. Are interpolated with the interpolation coefficient sequence a _{0 to an n−1} output from the interpolation coefficient generation unit 202, and output data P _k of the second sampling frequency. Here, the main clock φ is a clock having a frequency four times the first sampling frequency, but the transmission control device 100A sets the data input permission signal IE synchronized with the main clock φ to the second sampling frequency. The data is supplied to the interpolation unit 200A at a corresponding time density. A configuration for generating the data input permission signal IE at such a time density will be described later.

The sampling point of the data to be obtained by the interpolation operation moves on the time axis at a speed corresponding to the second sampling frequency. As a result, as illustrated in FIG. 3, the phase of the data P _{k−1 to} be _obtained next to the data P _k obtained by the interpolation operation is now advanced from the phase of the data D _m stored in the shift register 201. Can happen. In this case, after the interpolation operation data P _k, in preparation for the interpolation calculation of the next data P _k-1, the new data D _-1 is taken from the preceding apparatus to the shift register 201, the shift register 201 of The oldest data D _n-1 is discarded. The operation of sequentially advancing the phase of the data obtained by the interpolation operation is an operation of adding frequency control information y determined based on the ratio of the first sampling frequency and the second sampling frequency to the current interpolation ratio Δt. Is repeated. This operation is performed by the transmission control apparatus 100A, and details will be described later.

  The transmission control device 100A in FIG. 1 is a device that receives and stores the data string of the second sampling frequency from the interpolation unit 200A described above, and outputs it at a timing synchronized with the read request signal RR from the interface 300A. . The interface 300A outputs a read request RR to the transmission control device 100A in response to a data request signal LRCK from an external device, and outputs data output from the transmission control device 100A as a serial bit string SDO in response thereto It is.

Next, the configuration of the transmission control apparatus 100A will be described.
The FIFO 10 is a first-in first-out buffer configured by a RAM (Random Access Memory) or the like, and the present embodiment can store a maximum of four pieces of input data having a predetermined number of bits. The FIFO 10 sequentially stores the data P _k supplied from the interpolation unit 200A and outputs the data P _k to the interface 300A in order from the oldest one. The write control unit 30 performs a full addition process of adding the bit “1” to the least significant bit of the input phase information consisting of m bits when the main clock φ passes through the AND gate 101 and is given as the write request signal WR. . In the present embodiment, m is 4. Further, when the write request signal WR is given, the write control unit 30 writes the bit string composed of the upper j bits when the integer part of the input phase information represented by the upper j bits of the input phase information increases. The address is supplied to the FIFO 10 together with the write request signal WE. In the present embodiment, j is 2. The input data P _k supplied to the FIFO 10 is written in an area designated by a write address in the FIFO 10 by a write request signal WE. In response to the read request signal RR from the interface 300A, the read control unit 40 increments the integer part of the output phase information consisting of m bits by “1” and outputs the integer part of the output phase information at that time. The read address is supplied to the FIFO 10 together with the read request signal RE. Here, the read address designates the oldest input data that has not been read and remains in the FIFO 10. The input data specified by the read address is read from the FIFO 10 by the read request signal RE and supplied to the interface 300A.

  The phase difference detection unit 50 receives the m-bit input phase information generated by the write control unit 30 and the m-bit input generated by the read control unit 40 when the main clock φ is supplied via the AND gate 102. This circuit detects a phase difference that is a difference from output phase information. The integer part of this phase difference represents the remaining data amount that is the number of input data that has not yet been read and remains in the FIFO 10.

  The phase difference ΔS output from the phase difference detection unit 50 indicates the remaining data amount of data in the FIFO 10 as described above, and also indicates the phase difference between input data and output data in the FIFO 10. The read control unit 40, the write control unit 30, the phase difference detection unit 50, the frequency control unit 60, and the variable frequency oscillation unit 70 described above constitute a PLL 80 that converges the phase difference to an appropriate value. Yes.

  The frequency controller 60 includes a correction amount generator 61, a full adder 62, a latch circuit 63, and a limiter 64. The correction amount generator 61 is a means for generating a correction amount ΔT that is added to the frequency control information y in order to return the phase difference ΔS to an appropriate value. There are various methods for generating the correction amount ΔT. For example, there are the following methods.

<< First Method >>
In this method, when the phase difference ΔS is larger than an appropriate value, a positive correction amount having an absolute value corresponding to the difference between the two is generated to reduce the data input speed in the FIFO, and the phase difference ΔS is an appropriate value. If the value is smaller than that, a negative correction amount having an absolute value corresponding to the difference between the two is generated in order to increase the data input speed in the FIFO. This method has an advantage that it can be realized by a simple circuit.

<< Second Method >>
In principle, in this method, a correction amount ΔT corresponding to a value obtained by subtracting an appropriate value from the phase difference ΔS is generated as in the first method. However, in the following four cases, the correction amount ΔT is used as an exception. Generates “0”.
a. When the phase difference ΔS exceeds an appropriate value and is increasing b. When the phase difference ΔS is less than the appropriate value and is decreasing c. When the phase difference ΔS changes from an increasing state to a decreasing state d. When the phase difference ΔS changes from a decreasing state to an increasing state This method does not correct the data input speed when the phase difference ΔS is going to an appropriate value unnecessarily, so the data input speed is corrected more than necessary. This is advantageous in that it is possible to prevent the remaining data amount from fluctuating.

<< Third Method >>
In this method, a correction amount ΔT is generated as follows.
a. When the phase difference ΔS is increasing and exceeds the appropriate value, or when the phase difference ΔS is the upper limit value, a positive correction amount ΔT corresponding to the difference between the phase difference ΔS and the appropriate value is generated. Thus, the data input speed in the FIFO 10 is reduced.
b. When the phase difference ΔS is decreasing and below the appropriate value, or when the phase difference ΔS is the lower limit value, a negative correction amount ΔT corresponding to the difference between the phase difference ΔS and the appropriate value is generated. To increase the data input speed.
c. In cases other than a and b, “0” is output as the correction amount ΔT.
In this method, the data input speed is corrected only when the phase difference ΔS is about to diverge out of the proper value or when the phase difference ΔS is completely divergent, so the data input speed is corrected during an unnecessary period. There is an advantage that the phase difference ΔS can be quickly converged to an appropriate value, and fluctuations in the remaining data amount can be kept low.

The full adder 62 and the latch circuit 63 constitute means for correcting the frequency control information y based on the correction amount ΔT generated as described above. First, the full adder 62 performs the calculation shown in the following equation (1) based on the current frequency control information y held in the latch circuit 63 and the correction amount ΔT supplied from the conversion unit 61. The new frequency control information y that is the output data of the full adder 62 is latched by the latch circuit 63 when the main clock φ is supplied to the latch circuit 63 via the AND gate 103, and is less than a certain upper limit value by the limiter 64. And is supplied to the variable frequency oscillator 70.
y ← y + ΔT (1)
The latch circuit 63 can be initialized. When the sampling frequency converter starts operation, the latch circuit 63 is set with a value represented by the following equation as the initial value y of the frequency control information.
y = constant × (f1 / (4 · f2)) (2)
Here, f1 is a first sampling frequency before sampling frequency conversion, and f2 is a second sampling frequency after sampling frequency conversion.

  The variable frequency oscillating unit 70 includes a full adder 71, a latch circuit 72, an AND gate 73, a down counter 74, an enable signal generating circuit 75, and a latch circuit 76. The full adder 71 adds the frequency control information y output from the frequency control unit 60 and the interpolation ratio Δt, which is a decimal part of the output data of the latch circuit 72, and outputs the result. By the addition of the frequency control information y and the interpolation ratio Δt, the above-described “operation for sequentially advancing the phase of data obtained by interpolation calculation” is performed. The latch circuit 72 latches and outputs the output data of the full adder 71 when the main clock φ is given through the AND gate 73. A value obtained by subtracting “1” from the integer part of the output data of the latch circuit 72 is given to the down counter 74 as preset data. The down counter 74 takes in the preset data as a count value in synchronization with the main clock φ when an enable signal EN (to be described later) is asserted, and thereafter performs down-counting with the main clock φ. The enable signal generation circuit 75 is configured by a latch circuit, for example, and asserts an enable signal EN in synchronization with the main clock φ when the count value of the down counter 74 becomes “0”. The enable signal generation circuit 75 is initialized at the same time when the above-described initial setting of the latch circuit 63 is performed, and the enable signal EN is asserted regardless of the count value of the down counter 74 at the time of the initial setting. Is configured to do. The latch circuit 76 receives the data input permission signal IE and latches the decimal part of the output data of the latch circuit 72 and outputs the result to the interpolation unit 200A as the interpolation ratio Δt.

When the enable signal EN is asserted, the AND gate 101 outputs the main clock φ to the write control unit 30 as the write request signal WR. The AND gates 73, 102, and 103 supply the main clock φ to the latch circuit 72, the phase difference detection unit 50, and the latch circuit 63 when the enable signal EN is asserted. When the main clock φ is supplied to the latch circuit 72 via the AND gate 73, the integer part of the data stored in the latch circuit 72 may increase by 2 or more. This is because, as described with reference to FIG. 3, the phase of data to be obtained next in the interpolation unit 200 </ b> A is not advanced from the phase of the data D _m currently held in the shift register 201. means. Therefore, in this case, the down counter 74 performs a down count of several clocks, and the interpolation unit 200A performs an operation of fetching new data necessary for the interpolation calculation from the preceding device to the shift register 201.

The counter 110 is a quaternary counter and outputs a signal “1” every time the enable signal EN is asserted four times. When the signal “1” is output from the counter 110, the AND gate 111 outputs the main clock φ to the interpolation unit 200A and the latch circuit 76 as the data input permission signal IE. The reason why the frequency of the enable signal EN is set to ¼ and the data input permission signal IE is generated by the counter 110 and the AND gate 111 as described above is as follows. That is, the PLL control for converging the phase difference ΔS to an appropriate value is performed in synchronization with the main clock φ having a frequency four times the first sampling frequency, and the enable signal EN is also generated in synchronization with the main clock φ. This is because the data supply from the interpolation unit 200A to the FIFO 10 needs to be performed at a speed corresponding to the first sampling frequency.
The above is the details of the configuration of the transmission control apparatus 100A.

Next, the operation of this embodiment will be described.
When the operation of the sampling frequency converter is started, an initial setting operation is performed. In this initial setting operation, the initial value y of the frequency control information given by the above equation (2) is written in the latch circuit 63 in the transmission control apparatus 100A. In the initial setting operation, the enable signal EN is asserted by the enable signal generation circuit 75. Therefore, the frequency control information y written in the latch circuit 63 is written in the latch circuit 72 via the limiter 64 and the full adder 71, and the integer part of the frequency control information y written in the latch circuit 72 is It is preset in the down counter 74. Thereafter, the down counter 74 performs a down count based on the main clock φ. When the count value of the down counter 74 becomes “0”, the enable signal EN is asserted by the enable signal generation circuit 75. As a result, the main clock φ is supplied to the latch circuit 72 via the AND gate 73, the output data of the full adder 71 at that time, that is, the frequency control information output from the frequency control unit 60 and the output of the latch circuit 72. The addition result with the decimal part of the data is written to the latch circuit 72. The integer part of the output data of the latch circuit 72 is preset in the down counter 74. As a result of such an operation being repeated, the enable signal EN is generated with an average time density according to the frequency control information.

Each time the enable signal EN is generated, the main clock φ passes through the AND gate 101 and is supplied to the write control unit 30 as the write request signal WR. The main clock φ passes through the AND gates 102 to 103 every time the enable signal EN is generated, and is given to the phase difference detection unit 50 and the latch circuit 63. Further, the data input permission signal IE synchronized with the main clock φ is output from the AND gate 111 to the interpolation unit 200A and the latch circuit 76 at a rate of once per four assertions of the enable signal EN. By outputting the data permission signal IE, the data held in the latch circuit 72 is latched by the latch circuit 76 as the interpolation ratio Δt and sent to the interpolation unit 200A. In the interpolation unit 200A, in accordance with the data input permission signal IE, data of the second sampling frequency is obtained by interpolation using the correction coefficient sequence corresponding to the interpolation ratio Δt at that time and the data sequence held in the shift register 201. P _k is generated and supplied to the FIFO 10.

When the write request signal WR is given, the write control unit 30 performs a full addition process of adding the bit “1” to the least significant bit of the input phase information composed of m bits. In addition, when the numerical value represented by the upper j bits of the input phase information is increased by the full addition process, the write control unit 30 uses the upper j bits as a write address and supplies the write request signal WE to the FIFO 10. . As a result, the data P _k from the interpolation unit 200A is written into the area designated by the write address in the FIFO 10.

  On the other hand, the interface 300A outputs a read request signal RR in response to the supply of the clock LRCK from the external device. In response to this read request signal RR, the read control unit 40 increments the integer part, which is the upper j bits of the output phase information, by “1”, and the integer part of this output phase information, that is, the most stored in the FIFO 10 A read address designating old data is supplied to the FIFO 10 together with a read request signal RE. As a result, the oldest data is read from the FIFO 10 and supplied to the interface 300A.

  When the enable signal EN is asserted and the main clock φ is supplied via the AND gate 102, the phase difference detection unit 50 obtains the phase difference ΔS that is the difference between the input phase information and the output phase information at that time. The operation for obtaining the phase difference ΔS is performed every time the enable signal EN is asserted. Then, the correction amount generator 61 generates a correction amount ΔT corresponding to the phase difference ΔS.

  The correction amount ΔT output in this way and the current frequency control information y stored in the latch circuit 63 are added by the full adder 62, and new frequency control information y is generated by the main clock φ from the AND gate 103. Is written in the latch circuit 63. As a result, when the positive correction amount ΔT is output, the frequency control information y increases, and when the negative correction amount ΔT is output, the frequency control information y decreases, and “0” is output as the correction amount ΔT. When the frequency control information is set, the frequency control information y maintains the current value.

  The frequency control unit 60 adjusts the increase / decrease of the frequency control information y based on the correction amount ΔT in this way, and the variable frequency oscillation unit 70 outputs the enable signal EN based on the frequency control information y that has undergone such adjustment. Is done. Here, when the frequency control information y increases, the average number of main clocks φ required until the count value becomes “0” after the down counter 74 is preset increases, and the enable signal EN Average time density is reduced. For this reason, the data writing speed to the FIFO 10 is lowered. On the contrary, when the frequency control information y decreases, the average time density of the enable signal EN increases, so that the data writing speed to the FIFO 10 increases.

  When the data writing speed (that is, the frequency of the enable signal EN) in the FIFO 10 is lower than the reading speed (that is, the frequency of the read request signal RR), the phase difference ΔS is decreased, and negative correction is performed in the decreasing process. When the amount ΔT is generated, the frequency control information y decreases, and the data writing speed increases. On the contrary, when the data writing speed in the FIFO 10 is higher than the reading speed, the phase difference ΔS increases. When a positive correction amount ΔT is generated in this increasing process, the frequency control information y increases and the data writing is increased. The speed will be reduced. As a result of the PLL control corresponding to the increase / decrease of the phase difference ΔS, the write speed in the FIFO 10 follows the read speed, and the phase difference ΔS in the FIFO 10 converges to an appropriate value.

  According to the present embodiment described above, information having a higher number of bits than the write address and read address of the FIFO 10 and higher resolution is used as input phase information and output phase information, and the output increases according to the read request signal RR. PLL control for causing the input phase information to follow the phase information is performed. Therefore, by using the FIFO 10 having a small number of stages, the residual data amount can be quickly converged to an appropriate value in response to the fluctuation of the residual data amount of the FIFO 10 caused by the jitter of the read request signal RR. Further, according to the present embodiment, since the resolution of the input phase information and the output phase information is high, the resolution of the phase difference ΔS that is the difference between them is also high. Therefore, the correction amount ΔT with high resolution can be generated in accordance with the phase difference ΔS with high resolution, and the PLL control for making the input phase information follow the output phase information can be accurately performed. In addition, according to the present embodiment, the PLL control for causing the input phase information to follow the output phase information is performed in synchronization with the main clock φ having a frequency higher than the first sampling frequency corresponding to the data input speed of the FIFO 10. Is called. Therefore, according to the present embodiment, it is possible to perform the PLL control that responds to the temporal change in the remaining data amount of the FIFO 10 at a high speed and causes the input phase information to follow the output phase information.

<Second Embodiment>
FIG. 4 is a block diagram showing a configuration of a sampling frequency conversion apparatus according to the second embodiment of the present invention. In the present embodiment, an interface 300B is provided at the front stage of the transmission control device 100B, and an interpolation unit 200B is provided at the rear stage. The interface 300B supplies the data Din having the first sampling frequency together with the write request signal WR to the transmission control apparatus 100B. The interpolation unit 200B has the same configuration as the interpolation unit 200A in the first embodiment. The interpolation unit 200B holds a predetermined number of past data strings fetched from the FIFO 10 in a built-in shift register, and, as in the first embodiment, an interpolation coefficient string corresponding to the interpolation ratio Δt supplied from the latch circuit 76. Is output to the data string, and output data P _k as a result of the convolution operation is output at a timing synchronized with the output clock CKout having the second sampling frequency.

  The configuration of the transmission control device 100B is different from the transmission control device 100A according to the first embodiment in the following points. First, the write request signal WR having the same frequency as the first sampling frequency is directly supplied to the write control unit 30 from the interface 300B. Further, a counter 112 is provided instead of the counter 110 and the AND gate 111 in the first embodiment. Further, the write control unit 30 and the read control unit 40 are replaced with a write control unit 30B and a read control unit 40B. Other points are the same as in the first embodiment.

  In the transmission control device 100B, when the write request signal WR is given to the write control unit 30B from the interface 300B, the write control unit 30B increments the integer part, which is the upper j bits of the input phase information consisting of m bits, by “1”. Then, the integer part is used as a write address and supplied to the FIFO 10 together with the write request signal WE. As a result, the data from the interface 300B is written into the area specified by the write address in the FIFO 10. Further, in the transmission control device 100B, PLL control for stabilizing the phase difference ΔS is performed in synchronization with the main clock φ having a frequency four times the second sampling frequency, and in the process of this control, the main clock The enable signal EN is asserted at a time density corresponding to the first sampling frequency in synchronization with φ.

  The enable signal EN output from the enable signal generation circuit 75 is input to the read control unit 40B and the counter 112. When the enable signal EN is given, the read control unit 40B performs full addition processing to add the bit “1” to the least significant bit of the output phase information composed of m bits. Further, when the integer part of the output phase information represented by the upper j bits of the output phase information increases with the generation of the enable signal EN, the read control unit 40B uses the bit string consisting of the upper j bits as a read address. Hold.

  The counter 113 outputs the data output permission signal OE at a rate of once per four assertions of the enable signal EN. By outputting the data output permission signal OE, the decimal part of the output data of the latch circuit 72 is latched by the latch circuit 76 as the interpolation ratio Δt and supplied to the interpolation unit 200B. When the data output permission signal OE is given, the interpolation unit 200B outputs the read permission signal PRE at a timing synchronized with the output clock CKout. When the read permission signal PRE is given, the read control unit 40B outputs the read address held at that time to the FIFO 10 together with the read request signal RE. As a result, the oldest data is read from the FIFO 10 and supplied to the interpolation unit 200B. When the data output permission signal OE is given, the interpolation unit 200B performs an interpolation calculation using the correction coefficient string corresponding to the interpolation ratio Δt at that time and the data string held in the shift register. Data of a certain second sampling frequency is output in synchronization with the output clock CKout.

  In the first embodiment, the PLL control for causing the input phase information to follow the output phase information is performed. However, in the present embodiment, the PLL control for causing the output phase information to follow the input phase information is performed. This PLL control is performed by the same method as in the first embodiment. Therefore, also in this embodiment, the same effect as the first embodiment is obtained.

It is a block diagram which shows the structure of the sampling frequency converter which is 1st Embodiment of this invention. It is a block diagram which shows the structural example of the interpolation part in the same embodiment. It is a wave form diagram explaining operation | movement of the interpolation part. It is a block diagram which shows the structure of the sampling frequency converter which is 2nd Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100A, 100B ... Transmission control apparatus, 200A, 200B ... Interpolation part, 201 ... Shift register, 202 ... Interpolation coefficient generation part, 201 ... Convolution operation part, 300A, 300B ... Interface, 10 ... FIFO, 30, 30B ... Write control part , 40, 40B... Read control unit, 50... Phase difference detection unit, 60... Frequency control unit, 70... Variable frequency oscillation unit, 80.

Claims (4)

Storage means for storing input data in an area specified by a write address, and outputting data stored in an area specified by a read address;
Write control means for updating input phase information consisting of m bits (m is a plurality) and supplying a bit string consisting of upper j bits (j <m) in the input phase information to the storage means as the write address;
Read control means for updating output phase information consisting of m bits (m is a plurality), and supplying a bit string consisting of upper j bits (j <m) in the output phase information to the storage means as the read address;
Phase synchronization for controlling the update speed of the other of the input phase information or the output phase information so that the other of the input phase information or the output phase information is updated in synchronization with one of the input phase information or the output phase information And a transmission control apparatus. The phase synchronization means includes
Variable frequency oscillating means for generating a permission signal for permitting generation of a signal for requesting writing or reading of data in the storage means at a time density according to frequency control information;
The transmission control apparatus according to claim 1, further comprising: frequency control means for correcting the frequency control information so that a difference between the input phase information and the output phase information becomes an appropriate value. Interpolating means, transmission control means,
The interpolation means includes
Interpolation calculation input data holding means for sequentially taking in data of the first sampling frequency and holding it as an interpolation calculation input data string;
Interpolation calculation means for generating and outputting data of the second sampling frequency by interpolation calculation using the interpolation calculation input data string held in the interpolation calculation input data holding means,
The transmission control means includes
Storing the data output from the interpolation means in the area specified by the write address, and storing the data stored in the area specified by the read address;
Write control means for updating input phase information consisting of m bits (m is a plurality) and supplying a bit string consisting of upper j bits (j <m) in the input phase information to the storage means as the write address;
In response to the read request signal, the output phase information consisting of m bits (m is a plurality) is updated, and the bit string consisting of the upper j bits (j <m) in the output phase information is supplied to the storage means as the read address. Reading control means for
A sampling frequency conversion device comprising: phase synchronization means for controlling an update speed of the input phase information so that the input phase information is updated in phase with the output phase information. Interpolating means, transmission control means,
The interpolation means includes
Interpolation calculation input data holding means for sequentially taking in data of the first sampling frequency output via the transmission control means and holding the data as an interpolation calculation input data string;
Interpolation calculation means for generating and outputting data of the second sampling frequency by interpolation calculation using the interpolation calculation input data string held in the interpolation calculation input data holding means,
The transmission control means includes
Storage means for storing input data in an area specified by a write address, and outputting data stored in an area specified by a read address to the interpolation means;
In response to the write request signal, the input phase information consisting of m bits (m is a plurality) is updated, and the bit string consisting of the upper j bits (j <m) in the input phase information is supplied to the storage means as the write address. Write control means to
Read control means for updating output phase information consisting of m bits (m is a plurality), and supplying a bit string consisting of upper j bits (j <m) in the output phase information to the storage means as the read address;
A sampling frequency converter comprising: phase synchronization means for controlling an update speed of the output phase information so that the output phase information is updated in synchronization with the input phase information.

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