JP2006243144A - Data control circuit, image processing apparatus and display apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that a memory means is expensive and a circuit scale becomes larger. <P>SOLUTION: This apparatus comprises; a dividing means for dividing a display frame into m-pieces of sub-frames; and a combining means 11 for combining m-piece of the divided sub-frames by the dividing means into n-piece of sub-frames. The sub-frames which are parallelized and outputted are combination of n-pieces of sub-frames into which the same display frame is divided, regardless of m and n (m≠n or m=n). <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a data control circuit that divides a display frame into m subframes, outputs the m subframes in parallel for every n subframes, and outputs the image data. About.

In order to perform a display method (hereinafter referred to as pixel shift) that displays more than the number of pixels of the light modulation element by time division using the light deflection element and the light modulation element, a subframe for performing time division display is generated. In order to perform pixel arrangement / adjustment for this purpose, a frame buffer is necessary.
In Patent Document 1, a frame memory is provided for inputting data to a display liquid crystal panel, and in synchronization with the timing for sequentially switching data, a light modulation element is used by combining a polarization direction control liquid crystal panel and a crystal plate. There is described a display device that realizes high definition by deflecting modulated light to shift a display frame.
Patent Document 2 describes a method for reducing a required memory capacity by using a plurality of line buffers at the time of input for a frame buffer (not a pixel shift frame buffer) for storing input image data.

Patent Document 3 describes a method of performing image processing in parallel by inputting data of a plurality of scanning lines of an input image to an image processing unit.
In this method, in a driving method in which one frame of image data is divided into a plurality of subframes and time-division display is performed, one frame of image data is divided into subframes composed of pixels on the same scanning line of the output image. Sometimes image processing is performed in parallel for each sub-frame, but when dividing one frame of image data into sub-frames that include pixels on different scanning lines of the output image, pixels on different scanning lines of the output image are particularly important. It cannot be processed in parallel.

  For this reason, in the processing of subframes including pixels on different scanning lines of the output image, it is necessary to adjust the timing of each subframe using storage means for temporarily storing the processing results of each subframe. Since the storage means for storing the sub-frame has a capacity of one or more output images, it increases the component cost. The prior art does not provide a solution for these points.

Japanese Patent No. 0239826 JP 2001-109442 A JP2004-184457

  In the method described in Patent Document 2, when the input image is displayed as it is by alternately repeating the step of sequentially writing the input image data to the line buffer and the step of reading the image data from the line buffer after writing the image data to the line buffer. In this case, display can be performed without storing input image data of one screen, but in order to realize pixel shift, storage means is necessary for the arrangement of subframes. It does not provide a method.

In a display device that performs time-division display, conventionally, storage means for storing each sub-frame is required for each sub-frame for displaying one frame forming one image in a time-division manner.
If a dedicated storage means (for example, a FIFO memory, a multi-port VRAM, etc.) capable of performing writing and reading asynchronously is used, the storage capacity may be the same as the subframe capacity. However, the dedicated storage means is expensive. In particular, the multi-port VRAM has a problem that the standard of each company is not constant and the circuit scale of the control circuit becomes large. The cost of the storage means can be reduced by using inexpensive storage means such as general-purpose SDRAM, but in this case, the storage capacity is required to be twice the capacity of the subframe (because writing and reading are performed alternately). In addition, there is a problem that the control of the storage means is complicated and the circuit scale increases.

An object of the present invention is to provide a data control circuit capable of reducing the cost by reducing the storage means.
Another object of the present invention is to provide a data control circuit capable of preventing deterioration in image quality.
Another object of the present invention is to provide a data control circuit capable of reducing the processing speed of each image processing means and realizing reduction in component costs.

Another object of the present invention is to provide a data control circuit capable of reducing the capacity of a storage element and reducing the cost of components.
Another object of the present invention is to provide a display device capable of reducing the cost of components and realizing high-definition display at low cost.
Another object of the present invention is to provide a display device capable of realizing an optical deflection element whose deflection amount can be easily controlled.

Another object of the present invention is to provide an image processing apparatus that can reduce the memory elements for subframes and reduce the component cost.
Another object of the present invention is to provide an image processing apparatus that can reduce the number of signal lines necessary for control and can easily update and control scanning line information.
Another object of the present invention is to provide an image processing apparatus that can reduce the number of signal lines necessary for control and can easily read out scanning line information necessary for processing.

Another object of the present invention is to provide an image processing apparatus capable of easily realizing writing and reading control of storage means.
Another object of the present invention is to provide an image processing apparatus capable of performing image input and image processing of image input means asynchronously.
Another object of the present invention is to provide a display device capable of reducing the storage element capacity for subframes and reducing the component cost.

  In order to achieve the above object, the invention according to claim 1 divides a display frame into m (an integer greater than or equal to 2) subframes, and the m subframes are divided into n (an integer greater than or equal to 2) subframes. A data control circuit that outputs a frame in parallel for each frame, a dividing unit that divides a display frame into m subframes, and a subframe that is divided into n subframes divided into m by the dividing unit. The sub-frame to be combined and output to the frame and output in parallel is the n sub-frames obtained by dividing the same display frame regardless of m and n (m ≠ n or m = n). It is a combination of frames.

  According to a second aspect of the present invention, in the data control circuit according to the first aspect, the dividing unit includes a changing unit that changes a combination of n subframes for each display frame, and the changing unit includes n Means for indicating the order of the subframes, selects the subframe to be output in parallel according to the order of the subframes, and subsequently returns to the top of the order of the subframes at the end of the order of the subframes. Then, the order of the subframes is repeated in a ring shape, and the subframes are divided from the display frames, and the subframes are combined while maintaining the order.

  The invention according to claim 3 is the data control circuit according to claim 1 or 2, wherein the data control circuit has a plurality of image processing means for processing image data of a display frame, and the plurality of image processing means divides the display frame. Used for each subframe, the output data of the plurality of image processing means is pixel data for each subframe, and is processed in parallel for each subframe.

  According to a fourth aspect of the present invention, in the data control circuit according to any one of the first to third aspects, the display frame includes data of a plurality of scanning lines, and the data of the scanning lines includes a plurality of pixel data. A plurality of storage means for storing pixel data of m subframes divided by the dividing means for each subframe, input / output control means for controlling input / output of the storage means, The entry output control means controls the operation of storing the pixel data of each subframe divided by the dividing means in the storage means and the operation of outputting from the storage means for each scanning line of the display frame. .

  The invention according to claim 5 includes a light modulation element that modulates light from a light source according to an input signal, and a light deflection element that deflects light modulated by the light modulation element, and performs display in which time division display of an image is performed. The apparatus includes a display control circuit that controls display of the light modulation element, the display control circuit being a means for inputting a plurality of image data in parallel and sequentially outputting each image data to the light modulation element. And using the data control circuit according to any one of claims 1 to 4 to display each subframe corresponding to each deflection position by the light deflection element by the light modulation element, thereby performing time division display. Is what you do.

  According to a sixth aspect of the present invention, in the display device according to the fifth aspect, a liquid crystal composed of a chiral smectic C phase having homeotropic alignment is used for the light deflecting element.

  The invention according to claim 7 processes each pixel data of the input image having the scanning line number M (M ≧ 1) to generate each pixel data of the output image having the scanning line number N (N ≧ 1), One frame of the output image is decomposed into at least a plurality of sub-frames, and the pixel data of the output image is output for each of the sub-frames. A plurality of image processing units, each having a plurality of scanning lines i (i ≧ 1), that simultaneously generate pixel data of the output image for each of the plurality of subframes, and corresponding to each of the plurality of image processing units Image input means for inputting pixel data of the input image.

  According to an eighth aspect of the present invention, in the image processing apparatus according to the first aspect, each of the plurality of sub-frames is provided at every scanning line number i (i ≧ 1) in the output image data. Per pixel number j (j ≧ 1).

  According to a ninth aspect of the present invention, in the image processing apparatus according to the seventh or eighth aspect, the image input means stores a plurality of storage means for storing input image data and capable of at least independent writing and reading control. A first storage unit comprising: a write control unit having a function of selecting and writing the input pixel data corresponding to each of the plurality of image processing units to the first storage unit; and the plurality of storages And an output control unit having a function of selecting the plurality of image processing units and outputting input pixel data corresponding to the plurality of image processing units.

  According to a tenth aspect of the present invention, in the image processing apparatus according to the ninth aspect, the input pixel data to be written to each storage means is at least input pixel data of one scanning line of the input image.

  According to an eleventh aspect of the present invention, in the image processing apparatus according to the ninth or tenth aspect, in the write control for the first storage unit, the write control unit performs one scanning line of a subframe in the image processing unit. Each time the image data is generated and updated sequentially for each storage means, the input image to be newly written to the first storage means necessary for the image processing apparatus to perform processing at the time of writing By designating the number of scanning lines, the designated number is updated.

  According to a twelfth aspect of the present invention, in the image processing apparatus according to the eleventh aspect, the output control unit performs input line scanning control of the corresponding input image from the first storage unit to the image processing unit. Then, when the image processing unit performs processing from one scanning line of the input image, the first storage unit for storing the scanning line necessary for the processing is designated, and the image processing unit specifies the input image. When k scanning lines (k> 1) are required, at least one of the storage means for storing the corresponding scanning lines is designated.

  A thirteenth aspect of the present invention is the image processing apparatus according to any one of the ninth to twelfth aspects, further comprising a resolution detection unit that detects the resolution of the input image, and the write control unit and the output control unit. At least one control method or both control methods are stored in advance in a lookup table corresponding to at least the resolution detected by the resolution detection unit, and the lookup table corresponding to the resolution detected by the resolution detection unit is used. One or both of the write control unit and the output control unit are controlled.

  The invention according to claim 14 is the image processing apparatus according to any one of claims 7 to 13, comprising second storage means having a storage capacity of at least one frame of the input image data, The input image data is once stored in the second storage means, and the input image data is input from the second storage means 2 to the image input means.

  The invention according to claim 15 is an optical modulation that modulates the amount of reflection or transmission of incident light by the image processing device according to any one of claims 7 to 14 and an image signal from the image processing device. An element, a light source and an optical system for irradiating light to the light modulation element, and a light deflection element for deflecting light modulated by the light modulation element, corresponding to the position deflected by the deflection element Image display is performed by time-division display of subframes using the light modulation element.

  According to the present invention, by combining a plurality of subframes output in parallel with each other by combining subframes obtained by dividing the same display frame, combinations of subframes composed of different frames are not used. As a result, it is possible to reduce the storage means required for holding the period of at least one display frame in order to use subframes made up of different frames at the same time, thereby realizing a reduction in component costs.

According to the present invention, the combination of subframes is changed for each display subframe, and subframes are selected and switched sequentially, so that the subframe output order does not change and subframes of different frames are used. Even in such a case, since the subframe order is maintained and output, it is possible to realize display with no sense of missing images.
According to the present invention, by performing image processing in parallel for each subframe by the image processing means, it is possible to reduce the processing speed of each image processing means, and it is possible to realize a reduction in component costs.

  According to the present invention, pixel data of a subframe is stored for each scanning line based on switching of scanning lines of the display frame, and pixel data of subframes are also combined based on switching of scanning lines of the display frame. By outputting to the means, it is possible to deal with input data of continuous display frames, it is possible to reduce the capacity of the storage means used by the dividing means for dividing the display frame into sub-frames, and it is possible to reduce component costs .

According to the present invention, it is possible to reduce the storage capacity of the storage means when dividing into subframes, to reduce the cost of components, and to realize a high-definition display device at low cost.
According to the present invention, by using a liquid crystal composed of a chiral smectic C phase having homeotropic orientation as an optical deflecting element, an optical deflecting element having no operation sound can be realized by the liquid crystal, and the deflection amount of the optical deflecting element Therefore, it is possible to realize a good high-resolution display by realizing easy control of the amount of light deflection.

According to the present invention, it is possible to reduce the memory elements for subframes that have been required in the past, reduce the component cost of the memory elements and the circuits for controlling the memory elements, and realize cost reduction. it can.
According to the present invention, it is possible to perform image processing using a plurality of input image scanning lines at the same time, and it is possible to reduce the capacity of a storage element for subframes necessary for timing adjustment for display, and to reduce the component cost. Can be reduced.

  According to the present invention, it is possible to perform image processing in units of scanning lines of the input image by setting at least the input pixel data stored in the storage unit as scanning lines of the input image, and the generated subframe is also in units of scanning lines of the subframe Can be generated. As a result, it is possible to reduce the memory elements for the subframe that have been necessary in the past, reduce the component cost of the memory elements and the circuit for controlling the memory elements, and realize cost reduction.

According to the present invention, in the control of writing to the storage means, the number of scan lines of the input image data to be updated is designated and the storage means is sequentially updated to designate the scan lines of the input image data to be updated. Therefore, it is possible to reduce the number of bits of a signal for reducing the cost and to realize an easy control method by reducing the circuit scale.
According to the present invention, in the control of reading from the storage unit, a plurality of scans required by the image processing unit are specified by designating the storage unit that stores the scanning lines of one input image required by the image processing unit. By specifying the line, the number of bits of a signal designated for reading can be reduced, and cost reduction and easy control can be realized by reducing the circuit scale.

  According to the present invention, a control method for controlling input / output of storage means necessary for performing image processing in parallel for each resolution is stored in advance in a lookup table, and is read out from the lookup table corresponding to the resolution of the input image. Since the input / output of the storage means can be controlled according to the control method, the circuit scale required for control can be reduced and the component cost can be reduced as compared with the case where the sequential control method is calculated according to the resolution.

According to the present invention, the input image data is stored in the storage means, read out, and image input and image processing of the subsequent image input means are performed, so that input of the input image and image processing are mainly performed asynchronously. be able to. This makes it possible to execute processing at a processing speed that depends on the process after the image processing separately from the frequency of the input image data, and to select and use parts that meet the required processing speed. Reduction can be performed. Further, a control signal different from the input image can be used for the output from the storage means. In particular, by separately preparing a clock signal that does not include jitter, image processing can be performed stably.
According to the present invention, the capacity of a memory element used in a subframe for performing time-division display can be reduced and can be provided at low cost.

  According to the first embodiment of the present invention, a subframe buffer for making a subframe combination which has been conventionally required is reduced or eliminated by a subframe combination method necessary for pixel shift. Cost reduction was achieved by reducing the scale and the number of parts used. In particular, color display is performed by inputting subframes in parallel for each display color (red, blue, and green) constituting one frame using one light modulation element, and sequentially displaying each subframe. When a sub-frame necessary for pixel shift is configured using a display control circuit of a light modulation element that performs a field-sequential method to realize a sub-frame, A frame buffer was needed.

  By reducing or eliminating the capacity of the subframe buffer for making this combination of subframes, the circuit scale is reduced and the cost is reduced by reducing the number of parts used. For this field sequential method, by applying the present invention, it is possible to use a display control circuit (general-purpose product) that controls the display of a light modulation element corresponding to the field sequential method as it is, and newly supports pixel shift. Since the pixel shift can be realized without developing a display control circuit, a significant reduction in development cost and the like can be realized.

Embodiment 1 of the present invention will be specifically described below. Hereinafter, unless otherwise specified, it is assumed that the display frame is composed of a plurality of scanning lines, and the scanning lines are composed of a plurality of pixels.
1 and 2 show a display device having a data control circuit according to the first embodiment. One input display frame is divided into sub-frames for displaying pixel shift. Pixel data necessary for constructing each subframe from the display frame is input, and a combination of the necessary pixel data of each subframe is created from the input pixel data by the combining means 11 to thereby generate pixel data. Are reduced, or the number of subframe buffers for outputting in parallel is reduced or reduced.

  FIG. 1 shows an example of a display device having a data control circuit when a frame buffer 12 for display frames is used. The frame buffer 12 stores the input display frame (image data thereof), and subsequently outputs the scanning frame of the display frame and the pixel data on the scanning line as necessary for the portion using the display frame. The data of the pixels constituting each subframe is input from the individual input terminals to the combination means 11 in accordance with the display order within the subframe. This data control circuit divides one display frame into, for example, four subframes 1 to 4.

  The subframes 1 to 4 (image data) output from the frame buffer 12 are output in parallel by the combination circuit 11 in the number of outputs corresponding to the subsequent stage using the output of the combination circuit 11. Here, the light modulation element display control unit 13 provided at the subsequent stage of the combination unit 11 performs display control of the light modulation element 14 corresponding to the field sequential to which three subframes from the combination unit 11 are input, The modulation element 14 performs display according to the output of the light modulation element display control unit 14. A detailed pixel configuration will be described later.

  FIG. 2 shows an example of a display device having a data control circuit in the case where a display frame outputs scanning lines in order (from top to bottom), and pixel data is output for each pixel in the scanning line. The dividing means 15 sequentially divides the data of each pixel of the input display frame into pixel data of each subframe. The storage means uses the line buffers 16 to 23 exclusively for each subframe. Each of the line buffers 16 to 23 is a buffer having a capacity for storing at least sub-frame pixels divided from one scanning line of the display frame. The line buffers 16, 18, 20, 22 and the line buffers 17, 19, 21, 23 performs writing and reading alternately for each subframe.

  The combination means 11 receives pixel data of each sub-frame from the line buffers 16, 18, 20, 22 or the line buffers 17, 19, 21, 23, and outputs sub-frames necessary for the light modulation element display control unit 13 at the subsequent stage. Select pixel data to be output in combination. The light modulation element display control unit 13 inputs pixel data of three subframes in parallel, and performs display control of the light modulation element 14 for sequentially outputting the pixel data to the light modulation element 14 for each subframe. Do. The light modulation element 14 performs display in accordance with the pixel data input for each subframe from the light modulation element display control unit 13. The light modulation element 14 to be used may be, for example, a self-luminous type, a device that reflects incident light, or a device that modulates transmitted light.

  The input display frame is sequentially divided into subframes for performing pixel shift by dividing the display frame into a plurality of subframes. The contents of this division will be described later. Each of the divided subframes is written in, for example, the line buffers 16, 18, 20, and 22 in order to adjust the timing for displaying on the light modulation element 14.

  At this time, as already described, the image data before at least one scanning line is written in the line buffers 17, 19, 21, and 23, and the combination means 11 selects each image data corresponding to each sub-frame output at the same time. Then, the light modulation element display control unit 13 that controls the display of the light modulation element 14 is input in parallel in a necessary combination. The light modulation element display control unit 13 receives the image signals input in parallel from the combination unit 11 and sequentially outputs the image data of the subframes to the light modulation element 14.

  FIG. 3 shows a display state in pixel units according to the first embodiment. A light deflection element (not shown) deflects the light from the light modulation element 14 to a position corresponding to each sub-frame and projects it onto the screen through the projection lens. The reflected light or transmitted light from the light modulation element 14 is sequentially deflected by the light deflection element in the order of 2 → pixel 3 → pixel 4 → pixel 1... And an image corresponding to the deflected position is displayed. As a result, an image of the number of pixels of the light modulation element 14 or more is displayed in time division. Here, pixel 1 belongs to subframe 1, pixel 2 belongs to subframe 2, pixel 3 belongs to subframe 3, and pixel 4 belongs to subframe 4.

  Next, the relationship between pixel shift pixels and sub-frame pixels in the entire image will be described. As shown in FIG. 4, in the input images 00 to 77, the input pixel 00 is divided into subframe 1, the input pixel 01 is divided into subframe 2, the input pixel 11 is divided into subframe 3, and the input pixel 10 is divided into subframe 4, respectively. Similarly, the input pixels 02, 04, 06, 20, 22... 66 are subframe 1, the input pixels 03, 05, 07, 21, 23, and 67 are subframes 2, and the input pixels 13, 15, 17, 31,. 33... 77 are divided into sub-frame 3 and input pixels 12, 14, 16, 30, 32, and 76 are divided into sub-frames 4, respectively, to form an input image.

Here, a method of directly decomposing an input image is used as a decomposition method to pixel shift. The input pixels are sequentially distributed to the subframes 1 to 4 depending on whether the scanning line is even-numbered or odd-numbered, or even-numbered or odd-numbered in the scanning line.
FIG. 5 shows the configuration of the dividing means 15. The sub-frame division control unit 24 uses the vertical synchronization signal, the horizontal synchronization signal, the clock signal, etc. that are input in synchronization with the pixel data, and the number of scanning lines in the display frame and the number of pixels on the scanning line. Count the position. The subframe division control unit 24 switches select signals Sel1, Sel2, and Sel3 that switch the output destinations of the demultiplexers (DEMUX) 25 to 27 according to the count result. The demultiplexers 25 to 27 switch the input pixel data according to select signals Sel1, Sel2, and Sel3 from the subframe division control unit 24 and classify them into a plurality of subframes 1 to 4. Assuming that the demultiplexers 25 to 27 output the input pixel data from the output terminal Y1 with the select signals Sel1, Sel2, and Sel3 = H, respectively, the select signals Sel1 to Sel3 and the pixel data of the subframes 1 to 4 are shown in FIG. The relationship shown in FIG.

  The subframe division control unit 24 counts the horizontal sync signal by resetting by the vertical sync signal and counts the scanning lines, and counts the clock signal by resetting by the horizontal sync signal and counts the pixels. The positions of the input pixels are specified, and the select signals Sel1, Sel2, and Sel3 are switched correspondingly.

  FIG. 7 shows an output state of an image decomposed into pixel shifts. In FIG. 7, an image having a pixel shift x = 1 to 4 on the y-th scanning line of the input image is indicated as PSx-y. Since the original image is sequentially input for each scanning line, when the input image is distributed to each subframe without storage means, the original image is distributed in the order shown in FIG. Of course, for the sake of simplicity, for example, when PS1-1 and PS2-1 are viewed in detail, they are alternately output for each pixel, but here they are expressed as one output block. One scanning line time in FIG. 7 is a time for outputting pixels corresponding to one scanning line of the input image. As an example, QXGA (resolution 2048 × 1536, frame frequency 60 Hz) is 95.34 KHz (VESA).

  In the first embodiment, by using storage means (hereinafter referred to as storage means 1 and storage means 2) having a capacity of two scanning lines for each subframe, PS1-1, PS2- as shown in FIG. 1, PS 3-2, PS 4-2 are storage means 1 for each sub-frame (part of each sub-frame of the frame buffer 12 or line buffers 16, 18, 20, 22 or line buffers 17, 19, 21 , 23) and then output at the timing shown. During the output of PS1-1, PS2-1, PS3-2, and PS4-2, PS1-3, PS2-3, PS3-4, and PS4-4 that are continuously input are stored in the storage unit 2 (frame buffer). 12 to the other part for each subframe or line buffer 17, 19, 21, 23 or line buffer 16, 18, 20, 22) and PS1-3, PS2-3, PS3-4, and PS4-4 are output.

  As described above, by using the storage means 1 and the storage means 2 having a storage capacity of at least two scanning lines or more, the input image data is not stored in the frame buffer and is decomposed into pixel shift subframes. Pixel shift can be realized without using a new storage means in order to store input image data using a storage element, and use the storage means to decompose into subframes. Compared to the prior art, the cost was reduced by reducing the storage capacity, reducing the number of parts, and reducing peripheral circuits such as the control circuit of the storage means.

  According to the first embodiment, subframes to be output in parallel from the data control circuit are combinations of subframes obtained by dividing the same display frame, so that combinations of subframes composed of different frames are not used. . As a result, it is possible to reduce the storage means required for holding the period of at least one display frame in order to use subframes composed of different frames at the same time, thereby realizing a reduction in component costs.

  Further, according to the first embodiment, the sub-frame pixels are stored for each scanning line based on the switching of the scanning lines of the display frame, and are output to the combination means based on the switching of the scanning lines of the display frame. By doing so, it is possible to reduce the part cost by reducing the capacity of the storage means used by the dividing means that divides into sub-frames corresponding to the input of continuous display frames.

  In the second embodiment of the present invention, the PS display order is maintained using subframes of different frames. In the second embodiment, in the first embodiment, three data control circuits of the first embodiment are provided for each of the three primary colors R, G, and B (red, green, and blue), and the three data control circuits are provided. The part that controls the display of the light modulation element used for field sequential driving in FIG. 5 is a function for inputting image data of a plurality of subframes in parallel from the combination means and displaying the image data of each subframe on the light modulation element in order. have.

  A case where color display is realized by field sequential driving in the second embodiment will be described. The image data of one frame (color) is divided into a plurality of sub-frame image data for each of R, G, and B as in the first embodiment, and each sub-frame of R, G, and B is used for each color for each color. Are input to the light modulation element display control unit 13 in parallel. The input sub-frame image data of each color is sequentially input to the light modulation element 14 for each color in the same manner as in the first embodiment.

  In the light modulation element 14 for each color that modulates transmitted light or reflected light, the illumination light applied to the light modulation element 14 is switched in accordance with the image of each color displayed by the light modulation element 14. When displaying the red sub-frame, irradiate the red light modulation element with the red illumination light, and when displaying the green sub-frame, irradiate the green light modulation element with the green light modulation element. In order to display the frame, the blue light modulation element is irradiated with blue illumination light. For example, using a rotary filter in which transmitted light is divided into R, G, and B, irradiation light of each color of R, G, and B is produced in a time division manner and irradiated to the light modulation elements for each color. A color display is reproduced by using a single-plate light modulation element as the light modulation element for each color. The light of each color from the light modulation element for each color is synthesized by the dichroic prism, deflected to a position corresponding to each subframe by the light deflection element, and projected onto the screen by the projection lens.

  FIG. 8 shows the timing of a pixel shift method using display control of a light modulation element for driving the field sequential (hereinafter referred to as FS). FIG. 8 shows an image of pixel shift subframe y = 1 to 4 of the xth frame as PSxy. For example, PS23 indicates an image of subframe 3 of the second frame. In FIG. 8, image data (image data of 3 subframes) input to the light modulation element display control unit (controller) 13 for each color is shown as a controller input, and the display of the light modulation element 14 for each color corresponding to this is shown. Shown as light modulation element display.

  As shown in FIG. 8, since only three sub-frames of image data can be input as one input to the light modulation element display control unit 13 of each color, the image data of each frame can be input to each frame across two inputs. Are combined and input. For this reason, the light modulation element display control unit 13 for each color is indispensable for storing means for storing the image data of each subframe in order to cope with the input multiple times (twice). PS11 to PS14 constituting the first frame, PS21 to PS24 constituting the second frame, and PS31 to PS34 constituting the third frame are respectively combined by the combination of the image data input to the light modulation element display control unit 13 of each color. The images are successively displayed on the light modulation elements 14 of the respective colors, and are deflected to the corresponding positions by the light deflection elements to form a display image.

  In the second embodiment, only the subframes constituting the same frame are inputted to the light modulation element display control unit 13 for each color, and the subframes constituting the different frames are not inputted at one input. . As a result, since the input of one frame is completed every time it is input, it is not necessary to store the subframes constituting one frame using the storage means.

  In the second embodiment, as shown in FIG. 9, degradation of image quality can be prevented by maintaining the order of subframes to be displayed (indicated by y of PSxy in FIG. 9) in pixel shift. In the pixel shift, the light modulated by the light modulation element 14 is deflected to the position of y = 1 to 4 by the light deflection element. For example, the deflection distance can be approximately ½ of the pixel pitch. At this time, since the light deflection element deflects the light modulated by the light modulation element 14 as y = 1 → 2 → 3 → 4 → 1 → 2 →..., The image data of the subframe corresponds to this. Need to be displayed.

  In the second embodiment, at this time, subframes constituting other frames are used so that subframes of different frames are not mixed at the time of one input, and subframes corresponding to the deflection of the optical deflection element are displayed at the time of display. Prepare without omissions. In advance, the combination means 11 sequentially selects the input of each subframe (input terminal of the combination means 11) as a display order, such as PSx1, PSx2, PSx3, PSx4, PSx1, PSx2, PSx3, and so on. Subframes obtained by dividing the display frame are output from the storage unit 1 in the input order, so that at least the display order of the subframes is maintained. The means for selecting the input of the combination means 11 detects the control signal (vertical synchronization signal) of the display frame, so as to output the subframes from the combination means 11 sequentially in parallel for every input of the combination means 11. The input of the combination means 11 is selected by shifting the display order of the subframes.

  As shown in FIG. 9, each frame is composed of PS11.fwdarw.PS12.fwdarw.PS13.fwdarw.PS24 in sequence, one frame from PS21.fwdarw.PS22.fwdarw.PS33.fwdarw.PS34, and one frame from PS31.fwdarw.PS42.fwdarw.PS43.fwdarw.PS44. Composed. As is apparent from FIG. 9, by using this method, it is possible to construct a sub-frame of pixel shift without using the storage means conventionally required for constructing the sub-frame. Can be displayed without omission.

  According to the second embodiment, the combination of subframes is changed for each display subframe, and the subframes are sequentially selected and switched, so that the subframe output order does not change and the subframes of different frames are changed. Even if it is used, the subframe order is maintained and output, so that it is possible to realize a display with no sense of missing images.

In the third embodiment of the present invention, image processing is performed in parallel for each sub-frame, and each pixel constituting the sub-frame is sequentially generated by image processing, thereby forming a pixel-shift sub-frame.
FIG. 10 shows a processing circuit and the like that perform image processing according to the third embodiment. The processing circuits 28 to 31 as image processing means perform PS1 processing, PS2 processing, PS3 processing, and PS4 processing in which the subframes PS1, PS2, PS3, and PS4 obtained by dividing each frame are processed in parallel. The subframes PS1, PS2, PS3, and PS4 from the processing circuits 28 to 31 are alternately written in the line buffers 32 to 39 in the subsequent stage, respectively. The line buffers 32, 34, 36, and 38 and the line buffers 33, 35, 37, and 39 are alternately controlled for writing and reading for each scanning line of the display frame by a storage element control unit (not shown).

  For example, when the subframes PS1, PS2, PS3, and PS4 from the processing circuits 28 to 31 are written in the line buffers 32, 34, 36, and 38, the processing has already been completed for the line buffers 33, 35, 37, and 39. Sub-frame pixels are input. The combination of subframe pixels necessary for display is selected by the combination means 40 from the subframes from the line buffers 33, 35, 37, and 39, so that the light modulation element display control unit 41 and sequentially input from the light modulation element display control unit 41 to the light modulation element 42.

  The combination means (denoted as SEL in FIG. 10) 40 includes a selector that selects three types of signals from four types of signals. The light modulation element display control unit 41 receives a vertical synchronization signal, a horizontal synchronization signal, a clock signal, and the like necessary for the light modulation element display control from the subframe control unit 42 in synchronization with the input image signal. The combination means controller 44 receives a vertical synchronization signal, a horizontal synchronization signal, a clock signal, etc. from the sub-frame control unit 42, and combines the combination means so as to select a necessary sub-frame according to the frame being displayed. A control signal for switching 40 is input to the combination means 40.

The light modulation element display control unit 40 performs display control of the light modulation element 45 corresponding to the field sequential input of the three subframes from the combination means 40, and the light modulation element 45 is a part of the light modulation element display control unit 40. Display by output. Light from the light modulation element 45 is deflected to a position corresponding to each subframe by a light deflection element (not shown) and projected onto a screen by a projection lens.
In the third embodiment, parallel processing can be performed for each subframe with the above configuration.

The input image data is input to each of the processing circuits 28 to 31 by using, for example, a plurality of line buffers, sequentially storing the input image data in the line buffer, and reading from the line buffer that has not been written. By alternately performing, image processing can be performed with a reduced storage capacity. Thereby, in order to implement | achieve the same processing speed, the part required for each process can be comprised from the part of lower speed operation | movement, and part cost can be reduced.
As described above, according to the third embodiment, the processing speed of each image processing means can be reduced by performing image processing in parallel for each sub-frame by the image processing means, thereby realizing a reduction in component costs. Can do.

Embodiment 4 of the present invention performs pixel shift using vertically aligned ferroelectric liquid crystal. In Embodiments 1 to 3, the liquid crystal is vertically aligned using ferroelectric liquid crystal as the light deflection element. An optical deflection element was used.
FIG. 11 shows the structure of the light deflection element. The optical deflection element deflects the optical axis in a direction horizontal to the paper surface. The light deflection element applies a voltage from the power source 51 to the electrode 46, so that the state of the liquid crystal molecules of the liquid crystal 50 sandwiched between the substrates 47 and 48 via the alignment film 49 is changed, and the substrates 47 and 48. The incident light in the vertical direction (the direction horizontal to the paper surface) is deflected according to the state of the liquid crystal molecules of the liquid crystal 50. In the light deflection element, the emitted light is parallel to the incident light.

  Since this optical deflection element uses a ferroelectric liquid crystal, the response speed is fast. Further, since this optical deflecting element deflects in the state of the liquid crystal 50 aligned perpendicular to the substrates 47 and 48, the controllability of the deflection amount is good and it becomes possible to deflect it to a required position. Of course, the fourth embodiment can achieve quietness because there are no moving parts by using liquid crystal. In this light deflection element, incident light is shifted into first and second emitted light as shown in FIG.

  FIG. 12 shows the state of the liquid crystal 50. The liquid crystal 50 realizes the light shift in the two directions shown in FIG. 11 according to this alignment state. As shown in FIG. 11, this optical deflection element realizes a horizontal or vertical shift in one direction with one element. In the fourth embodiment, two light deflection elements whose light shift directions are orthogonal to each other are used. By using a ferroelectric liquid crystal that is vertically aligned to the light deflection element, the deflection amount and the controllability by the electric signal are good, and the deflection of the light that does not generate the operation sound can be executed, and a good image can be obtained. I was able to get it. In addition, the light deflection element used was able to realize a quiet pixel shift operation with good controllability.

Embodiment 5 of the present invention deflects light by the vertically aligned ferroelectric liquid crystal in Embodiment 2 above, and uses three optical systems and light modulation elements (for R, G, and B). A projection display device was manufactured.
In the fifth embodiment, as shown in FIG. 13, a lamp in which an ultrahigh pressure mercury lamp is combined with a parabolic reflector is used as the light source 52, and an integrator and polarized light are unidirectional in order to uniformize the light from the light source 52. For this purpose, the polarization conversion element 53 provided between the integrator and the light modulation elements 54 to 56 is used to illuminate the portions of the light modulation elements 54 to 56 that perform light modulation substantially uniformly.

  Color separation and synthesis were performed with the optical system shown in FIG. The light that has passed through the integrator and the polarization conversion element 53 is reflected by the mirror 57 and the blue component is reflected by the blue reflecting dichroic mirror 58. The reflected light from the blue reflecting dichroic mirror 58 is relay lens 59, mirror 60, polarizing beam splitter. The light enters the light modulation element 55 via 61. The green component of the transmitted light from the blue reflecting dichroic mirror 58 is reflected by the green reflecting dichroic mirror 61, and the reflected light from the green reflecting dichroic mirror 61 enters the light modulation element 54 via the polarization beam splitter 62. The light transmitted through the green reflecting dichroic mirror 61 enters the light modulation element 56 via the polarization beam splitter 63, and the light modulation elements 54 to 56 modulate the incident light, respectively.

  The light of each color deflected by the light modulation elements 54 to 56 is rotated by 90 degrees, passes through the polarization beam splitters 60 ′, 62, 63, is synthesized by the dichroic prism 64, and is synthesized by the light deflection element 65. After being deflected in the same manner as 2, the projection lens 66 projects the image onto a screen (not shown) to display an image. The relay lens 59 is for adjusting the length of the optical path through which only the blue component passes with respect to the optical path through which the green component and red component pass.

Here, the optical deflecting element 65 is a deflecting element that is vertically aligned using a ferroelectric liquid crystal as in the fourth embodiment, but a liquid crystal composed of a chiral smectic C phase having homeotropic alignment is used. Also good. In the fifth embodiment, the capacity of the storage means used to divide the subframe for performing the pixel shift is reduced by using the data control circuit of the second embodiment to create the subframe constituting the pixel shift. Therefore, a reduction in component costs can be realized.
In the fifth embodiment, the data control circuit of the first, third, or fourth embodiment may be used.

  According to the fifth embodiment, it is possible to reduce the component cost by reducing the storage capacity when dividing into subframes, and to realize a display device for high-definition display at low cost. In addition, by using a liquid crystal consisting of a chiral smectic C phase with homeotropic orientation as the optical deflection element, an optical deflection element with no operating sound can be realized with the liquid crystal, the deflection amount can be controlled, and the optical deflection amount can be controlled. By realizing this ease, it is possible to realize a good high-resolution display.

  Next, a sixth embodiment of the present invention will be described. In the sixth embodiment, input image data is written into the storage means 1 for each scanning line every time it is input, and is processed sequentially. In this case, the image processing for the input of the image data and the input image data generate a sub-frame constituting an output image of one frame corresponding to the one frame for the input of the image data of one frame.

FIG. 14 is a block diagram showing the display device of the sixth embodiment.
Here, the input image data is stored in storage means 67 and 68 having a storage capacity for storing at least one frame of the input image data, so that the input image data is input at a timing different from the input timing of the input image data. Process. That is, by using a FIFO (First In First Out) capable of asynchronously writing and reading image data as the storage unit 2, writing of input image data, image processing at a later stage, which will be described later, and the like are performed. Can be done asynchronously. Similarly, it is possible to asynchronously write and read image data by using a multi-port RAM, a dual-port RAM, or the like that performs writing and reading of image data using separate ports.

  In these storage elements, there is no standard for multi-port VRAMs in particular, so specifications are made for each manufacturer. FIFO is a product that can operate at high speed and has a small capacity, and is used for storing large-capacity image data. Since the number of parts increases and the operation speed is limited for a large-capacity product, a storage element that asynchronously writes and reads these image data is generally expensive. On the other hand, a memory element (single-port RAM) that has one port for writing and reading and performs one of writing and reading is generally preferable because it is inexpensive. By alternately writing and reading image data using a plurality of storage elements, writing of input image data and subsequent processing can be performed continuously, which is very preferable. In recent years, controllers that realize the same operation as the FIFO described above by combining this storage element and a controller that controls input / output of the storage element are also commercially available.

  In the sixth embodiment, the storage means 67 and 68 use two SDRAMs (synchronous DRAMs), which are single-port RAMs having a storage capacity for one frame of input image data, and image data for each frame. By performing writing and reading of data, the configuration is such that continuous subsequent processing is performed. The storage means control means 69 controls the writing and reading of input image data to and from the storage means 67 and 68 by alternately switching the storage means 67 and 68 comprising the single port RAM.

  Image processing units 70 to 73 that perform image processing require a plurality of scanning line segments of input image data. Here, the image processing units 70 to 73 perform resolution conversion as image processing and perform linear interpolation as a processing method. In this linear interpolation, an output image pixel is obtained from an average of four input image pixels around the output pixel. The read control unit 80 selects a plurality of storage units 74 to 78 and a plurality of image processing units 70 to 73 and inputs input pixel data corresponding to the plurality of image processing units 70 to 73 to the plurality of image processing units 70 to 73. Output. For example, the combination means 11 of the first embodiment is used as the subframe selection unit 81, and the subframes to be simultaneously output to the light modulation element display control unit of the subsequent stage with respect to the image data from the plurality of image processing units 70 to 73 Each image data corresponding to a frame is selected and output in parallel to the subsequent light modulation element display control unit in a necessary combination.

  Hereinafter, as in the first embodiment, the light modulation element display control unit receives the image signals input in parallel from the subframe selection unit 81 and sequentially outputs the image data of the subframes to the light modulation element. The light modulation element performs display according to the pixel data input every subframe from the light modulation element display control unit.

FIG. 19 shows the relationship between input pixels and output pixels.
When the intervals of the input pixels A, B, C, and D are set to 1, and the horizontal and vertical positions of the output pixels from the input pixel A are x and y, respectively, the output pixels by linear interpolation are the four surrounding pixels. Using the input pixels A, B, C, and D, the following expression (1) is given. If the value of the output pixel is X,
X = (1-x) (1-y) A + x (1-y) B + (1-x) yC + xyD (1)
For this reason, the image processing units 70 to 73 need pixel data of two scanning lines of the input image in order to perform the image processing in the linear interpolation. The sixth embodiment is necessary for the image processing units 70 to 73 to simultaneously perform image processing on pixel data corresponding to each of the subframes from a plurality of scanning line data of the input image data stored in the storage units 67 and 68. The scanning line data is written in the storage means 74 to 78, and the image processing units 70 to 73 perform image processing. As described above, the writing control unit 79 performs control for selecting the scanning lines necessary for the image processing from the storage units 67 and 68 and writing them to the storage units 74 to 78. The sixth embodiment is characterized in that the control of writing to the storage means 74 to 78 is performed by designating the number of scanning lines of the scanning line data to be newly updated. Hereinafter, the linear interpolation performed by the image processing units 70 to 73 will be described. The present invention does not limit the interpolation method used.

  In order to explain the linear interpolation, the case where the relationship between the pixels of the input image and the pixels of the output image is the positional relationship shown in FIG. In FIG. 15, pixels of the input image are indicated by white circles, and pixels of the output image are indicated by gray circles. A virtual pixel (gray) having the same value as the actual pixel closest to the outside of the actual pixel of the input image is arranged. The present invention is not limited to the relationship between the input image and the output image. This is shown for illustrative purposes only.

  The image layout in FIG. 15 is as follows. Virtual pixels are arranged outside the input image at the pixel pitch of the input image. The value of the virtual pixel is the value of the real pixel closest to each virtual pixel. Assuming that the pixel pitch of the output pixel is B, the output pixel starts from a position shifted by ½ B inward in the horizontal and vertical directions from the point A in FIG. 15 surrounded by three virtual pixels and one real pixel. To do. At the four corners of the input image, output pixels are arranged starting from a position that is always shifted by 1 / 2B from the same starting point toward the center of the image, and equal allocation is performed with the pitch between the output pixels being B.

A division method for dividing one frame of the output image into a plurality of subframes (1 to 4) will be described.
FIG. 16 shows the relationship between the pixels of the output image of one frame and the pixels of the divided subframes 1 to 4. The same numerical value in FIG. 16 indicates the same pixel. As is apparent from FIG. 16, each subframe includes pixels on different scanning lines of the output image. In the sixth embodiment, the image processing units 70 to 73 perform image processing on the pixel data at the corresponding positions in the subframes 1 to 4 illustrated in FIG. 16 in parallel. That is, the image processing units 70 to 73 simultaneously process the image data of the subframe including the pixel of (00, 01, 11, 10), and subsequently (02, 03, 13, 12), (04, 05, 15,... And the image data of the sub-frame including the pixels on the scanning lines of different output images are processed in parallel.

  Here, a case where five line buffers having a storage capacity for one scanning line of the input image are used as the storage units 74 to 78 will be described. The resolution of one frame of the output image is QXGA (2048 × 1536), the resolution of each subframe is XGA (1024 × 768), and the input image is UXGA (1600 × 1200). For the sake of explanation, the scanning lines of each image are first, second,... In order to simultaneously perform image processing on the first scanning line data of each subframe, it is necessary to generate the first and second scanning line data of the output image by image processing. At this time, the image processing units 70 to 73 obtain scanning lines of a necessary input image.

Since the images have the relationship shown in FIG. 15, when the pixel pitch of the input image is 1, the pixel pitch B of the output image at this time is expressed by the following equation (2).
1200-1 + 1/2 × 2 = (1536-1 + 1/2 × 2) B (2)
This expression (2) is (the number of pixels of the input image) × 1 = (the number of pixels of the output image) × B. x is 0.78125. As shown in FIG. 15, the first scanning line of the output pixel is obtained from the input image, the virtual pixel (referred to as the first scanning line), and the second scanning line. It can be seen that the second scanning line of the output pixel similarly requires the second scanning line and the third scanning line of the input image. That is, scanning lines from the first scanning line to the third scanning line of the input image are necessary for image processing.

  FIG. 26 shows the relationship between the scanning lines of each output image and the scanning lines of the input image necessary for processing. In FIG. 26, the first scanning line (virtual pixel) of the input image is 0, the second scanning line (real pixel) is 1, the 1201st scanning line (real pixel) is 1200, and the 1202th scanning line (virtual pixel) is 1201. It is shown. In FIG. 26, scanning lines that need to be newly added to the scanning lines used in the previous processing are shown in bold. As is apparent from FIG. 26, the two scan line data of the output image can be sequentially processed by updating the maximum two scan line data except the first process. The first process is to start the process after the necessary scanning line data is read into the storage means 74 to 78. Thereafter, the maximum of two pieces of scanning line data is read into the storage means 74 to 78 continuously. Can be processed. In the sixth embodiment, by specifying the number of scanning lines to be updated, necessary scanning lines are specified and sequentially written in the storage units 70 to 73.

  In the above description, a case has been described in which the storage means 70 to 73 have five line buffers having a storage capacity for one scanning line of the input image. However, the present invention directly limits the number of line buffers. is not. Also, the relationship between the input image and the output image is not limited to the example shown for the above description.

  Next, in the sixth embodiment, an example in which an image having a resolution different from the above example of the sixth embodiment is input as an input image using the same relationship between the input image and the output image will be described. This example is a case where only the resolution of the input image is VGA (640 × 480) in the above example of the sixth embodiment, and other conditions are the same as those of the sixth embodiment. FIG. 27 shows the relationship between the scanning line of each output image and the scanning line of the input image necessary for processing in this example. In FIG. 27, similarly to FIG. 26, scanning lines that need to be newly added to the scanning lines used in the previous processing are shown in bold. As can be seen from FIG. 27, two scanning line data of the output image can be sequentially processed by updating almost one scanning line data except for the first processing. The first process can be performed continuously by starting the process after the necessary scanning line data is read into the storage means 67 and 68.

  As can be seen from these two examples, by specifying the number of scanning lines to be updated, it is possible to sequentially input necessary scanning line data to the storage means 74 to 78 as line buffers, depending on the resolution of the input image. The combination of scan lines to be updated is determined.

  In the sixth embodiment, the write control unit 79 assigns numerical values to the line buffers 74 to 78 as storage means, and manages the order of cyclic writing to the line buffers 74 to 78 sequentially. If four line buffers 74 to 78 are used, the writing control unit 79 determines the order of writing to the line buffers 74 to 78 from the smaller of the scanning line numbers (first, second,...) Of the input image. Writing is performed in the order of numbers 0 → 1 → 2 → 3 → 4 → 0 → 1. The writing control unit 79 stores the numerical value of the line buffer updated (written) immediately before writing, and starts writing from the stored numerical value +1.

  FIG. 17 shows a write control flow for the line buffers 74 to 78 of the write control unit 79. There are five line buffers 74-78. FIG. 28 shows the definition of each variable. Note that the scanning lines (real pixels) of the input image are indicated by Row1 to Row1536. The writing control unit 79 sets nW, WRN, and LNN to 0 at the time of initialization, and counts the number of scanning lines nW of the subframe of the output image every time processing is performed (nW ← nW + 1). The writing control unit 79 receives the number of scanning lines LW of the input image to be updated from the image processing units 70 to 73.

  The write control unit 79 processes the first line data of the input image when nW = 1, and as shown in FIG. 15, the write control unit 79 sets LB0 ← Row1, LB1 ← Row1, LB2 ← Row2, LB3 ← Row3. The same scanning line as the first scanning line is used as the scanning line of the virtual pixel, and after setting 3 to WRN and LNN, the process returns to the step of incrementing nW. The writing control unit 79 uses LBx ← Row 1535, LBx ← Row 1536, LBx ← Row 1536, and LBx in order to use the same scanning line as the last scanning line of the input image (768th line in this example) as the scanning line of the virtual pixel. After (n) = RowN, the process returns to the step of incrementing nW. In the case of 2 ≦ nw ≦ 767, the write control unit 79 returns to the step of incrementing nW if LW is 0.

  The write control unit 79 increments WRN and LNN when LW = 1 or 2, and sets LNN to 0 when LNN = 5. Then, the writing control unit 79 writes the data of the scanning line WRN to the LNN (number LNN) line buffer (denoted as LB in FIG. 17) of the line buffers 74 to 78, decrements the LNN, and the LNN If it becomes 0, it will return to the step which increments nW, and if LNN is not 0, it will return to the step which increments WRN and LNN. In this way, the writing control unit 79 writes the scanning line data designated by the storage means 67 and 68 to the storage means 74 to 78 designated by LBx (x = 0 to 4).

  In the sixth embodiment, since the subscripts indicating the storage means 67 and 68 are integers of 0 to 4, 0 → 1 → 2 → 3 → 4 → 0 when sequentially writing to the line buffers 74 to 78. Control is performed so as to sequentially instruct the storage means 67 and 68 such as 1.

  FIG. 18 shows operations of the line buffers 74 to 78 by reading the first scanning line data and the second scanning line data of the input image from time t = 1 to 4 and at time t = 1. As shown in FIG. 18, five line buffers 74 to 78 (LB0 to LB4) are used, and LW indicates the number of scanning lines to be updated as in FIG. Image processing indicates the number of scan lines of the output image to be processed. For the sake of display, the scanning line of the input image is indicated by Row + subscript. The subscript w indicates that the corresponding scanning line is written in the line buffer, and the subscript r indicates that the corresponding scanning line is read from the line buffer.

  According to the sixth embodiment, each sub-frame consisting of pixels every i (i ≧ 1) scanning lines and every pixel j (j ≧ 0) for each scanning line, Using the image processing unit that generates subframes and the corresponding image input means to simultaneously generate output pixel data for these subframes, reducing the memory elements for subframes that were required in the past Thus, the component cost of the memory element and the circuit for controlling the memory element can be reduced, and the cost can be reduced.

  The image input means includes storage means 74 to 78, a write control unit 79 that performs writing control of the storage means 74 to 78, and a read control unit 80 that controls reading from the storage means 74 to 78. By storing a plurality of input image scanning lines necessary for image processing using a plurality of storage means 74 to 78, it is possible to perform image processing using a plurality of input image scanning lines at the same time and display timing. It is possible to reduce the capacity of the sub-frame storage element that is necessary for the adjustment, and to reduce the component cost.

  Further, by making the input pixel data stored in the storage means 74 to 78 at least the scanning lines of the input image, it is possible to perform image processing in units of scanning lines of the input image, and the generated subframes are also in units of scanning lines of the subframes. Generation is possible. As a result, it is possible to reduce the memory elements for the subframe that have been necessary in the past, reduce the component cost of the memory elements and the circuit for controlling the memory elements, and realize cost reduction.

  Also, the input image data is stored in the storage means 67, 68, and is read out and subjected to image input and image processing by the subsequent image input means, thereby mainly performing input image input and image processing asynchronously. be able to. This makes it possible to execute processing at a processing speed that depends on the process after the image processing separately from the frequency of the input image data, and to select and use parts that meet the required processing speed. Reduction can be performed. Further, a control signal different from the input image can be used for the output from the storage means 67 and 68, and in particular, the clock signal can be stably processed by preparing a signal that does not include jitter. Can do.

  Further, according to the sixth embodiment, subframes including pixels on different scanning lines can be processed at the same time, and an input image scanning line necessary for processing is designated by giving a numerical value up to 2 Therefore, it is possible to reduce the number of signal lines (bus width) and the circuit scale by easy processing.

Next, a seventh embodiment of the present invention will be described.
In the seventh embodiment, in the sixth embodiment, the reading control unit 80 performs reading from the storage units 74 to 78 as follows. In the seventh embodiment, the read control unit 80 scans input images required by the image processing units 70 to 73 that perform image processing (two scanning lines are required for linear interpolation in the sixth embodiment). By specifying a line buffer that has a smaller numerical value of input, a line buffer necessary for image processing is specified, and scanning line data of the input image necessary for the image processing unit is read and input to the image processing unit . Since the scanning line data of the input image is sequentially input to the line buffers 74 to 78, the line buffer designated by designating the scanning line having the smaller numerical value among the two necessary scanning lines in this case. In addition, the scanning line data is read out from the lowermost line (+1 lower line buffer) (however, when the number of the line buffers 74 to 78 is 0 to 4, 4 + 1 indicates the line buffer 0). Necessary scanning line data is input to the image processing unit.

  FIG. 20 shows the control flow of the line buffer 7, and FIG. 29 shows the definition of each variable. Five line buffers 74 to 78 are prepared. The read control unit 80 resets all variables to 0 at the time of initialization, and increments the number nr of scanning lines in the subframe of the output image. Next, the readout control unit 80 LR1 indicating the smaller one of the scanning lines used for the processing of the subframes 1 and 2 in the first scanning line (nr = 1) of the subframe of the output image, LR2 indicating the smaller scanning line used for the process No. 4 is input from the image processing units 70-73.

  If LR1 and LR2 are equal, the read control unit 80 uses the same scan line. Therefore, the read control unit 80 reads the scan line data from the line buffer indicated by LR1 = LR2, and subsequently increments LR1 and LR2 to LR1 + 1 (or Scan line data is read from the line buffer indicated by LR2 + 1). However, the read control unit 80 sets LR1 and LR2 to 0 when LR1 and LR24 exceed 4 at the stage where LR1 and LR2 are incremented.

  On the other hand, when LR1 ≠ LR2, the read control unit 80 reads scan line data from the line buffers indicated by LR1, LR2, LR1 + 1, and LR2 + 1, respectively. Also at this time, the read control unit 80 sets LR1 and LR2 to 0 when LR1 and LR24 exceed 4 at the stage where LR1 and LR2 are incremented. The read controller 80 returns to the step of incrementing nr when scanning line data is read from the line buffer.

  Outputs from the line buffers 74 to 78 are respectively input to the four image processing units 70 to 73 in the seventh embodiment. Depending on the line buffer, the output may be input to a plurality of image processing units. Here, the contents of the line buffer (scan line data) are simultaneously input to the required image processing unit. According to the seventh embodiment, each of the image processing units 70 to 73 requires every two pieces of scanning line data. Information for designating every two pieces of scanning line data (from the image processing units 70 to 73 to the readout control unit 80). Information) is information for two lines, and the designation can be supported by information of 3 bits indicated by 0 to 4 (information for each scanning line of each subframe of the output pixel is 6 bits) It was possible to reduce the number of signal lines (bus width) and the circuit scale by easy processing.

  According to the seventh embodiment, as a specific control method for writing to the storage means 74 to 78, the storage means 74 to 78 are sequentially updated by designating the number of scanning lines of the input image data to be updated. Therefore, the number of bits of the signal for designating the scanning line of the input image data to be updated can be reduced, and the cost can be reduced and the easy control method can be realized by reducing the circuit scale.

  Further, as a specific control method for reading from the storage means 74 to 78, by specifying the storage means for storing the scanning lines of one input image required by the image processing unit among the storage means 74 to 78, By specifying a plurality of scanning lines required by the image processing units 70 to 73, it is possible to reduce the number of bits of a signal designated for reading, and to realize a cost reduction and an easy control method by reducing the circuit scale.

Next, an eighth embodiment of the present invention will be described. In the eighth embodiment, image processing is performed using a combination of scanning lines of the input image corresponding to the resolution of the input image by detecting the resolution of the input image in the seventh embodiment.
FIG. 24 shows a resolution detector of the eighth embodiment.

  The resolution detection unit according to the eighth embodiment detects the resolution using the horizontal and vertical synchronization signals and the clock signal of the input image. The horizontal synchronization signal counter 82 detects the rising edge of the vertical synchronization signal synchronized with the input image data and counts the number of horizontal synchronization signals synchronized with the input image data between the vertical synchronization signals, thereby synchronizing the horizontal synchronization between the vertical synchronization signals. Count the number of signals. A look-up table (LUT) 83 stores in advance the relationship between the number of horizontal synchronization signals between vertical synchronization signals and the number of scanning lines between vertical synchronization signals that can specify each resolution. The subtractor / comparator 84 compares the number of horizontal synchronizing signals between the vertical synchronizing signals counted by the horizontal synchronizing signal counter 82 with the number of scanning lines between the vertical synchronizing signals that can specify each resolution of the LUT 83 to identify each resolution. The signal to be output is output to the code converter 85.

  The clock signal counter 86 detects the rising edge of the horizontal synchronization signal HD synchronized with the input image data, and counts the number of clock signals synchronized with the input image data between the horizontal synchronization signals HD. The LUT 87 stores the relationship between the number of pixels between horizontal synchronization signals and the number of pixels between horizontal synchronization signals that can specify each resolution. The subtractor / comparator 88 compares the number of pixels between the horizontal synchronization signals counted by the clock signal counter 86 with the number of pixels between the horizontal synchronization signals that can specify each resolution of the LUT 87, and codes a signal specifying each resolution. Output to the converter 85. The code converter 85 converts the output signals of the subtracter / comparators 84 and 88 into a code indicating resolution and outputs the code. As long as the code can specify the resolution detected by resolution detection, this code can be expressed in binary numbers sequentially from the smallest number of pixels as an example.

  21 to 23 show the resolution detection flow of the eighth embodiment. 21 to 23, the vertical synchronizing signal is indicated by VD, the horizontal synchronizing signal is indicated by HD, and the clock signal is indicated by SCK. FIG. 30 shows the definition of each symbol.

  As shown in FIG. 21, in the routine from start 1, after the horizontal synchronization signal counter 82 detects the rising edge of VD, the HD between VDs is counted and the count result is held in RN. As shown in FIG. 22, in the routine from start 2, the clock signal counter 86 detects the rising edge of HD, counts SCK between HDs, and holds the result in CN.

  As shown in FIG. 23, the subtracter / comparator 84 reads from the LUT 83 the number of scanning lines that can specify each resolution from the number of scanning lines, with t as a subscript, and sequentially compares the number of scanning lines with the RN. In this example, it is compared with RN since the resolution is large. When the comparison result RJ (t) between the detected RN and R1 (t) of the LUT 83 switches from negative to positive, the subtracter / comparator 84 compares the comparison results RJ (t−1) and RJ (t) immediately before the switching. Are compared, and the subscript t indicating the reference result from the LUT 83 closest to the RN is specified.

The subtracter / comparator 88 reads from the LUT 87 the number of signals (number of pixels) that can specify each resolution from the number of clocks, using tt as a subscript, and sequentially compares it with CN. In this example, the comparison is performed from the one with the highest resolution. When the comparison result CJ (tt) between the detected CN and C1 (tt) of the LUT 87 switches from negative to positive, the subtracter / comparator 88 compares the comparison results CJ (tt−1) and CJ (tt) immediately before switching. Are compared, and the subscript tt indicating the reference result from the LUT 87 closest to the CN is specified.
The code converter 85 uses the t and tt thus obtained to generate a code indicating the resolution shown above. The writing control unit 79 and the reading control unit 80 control the input / output of the storage means 74 to 78 for each resolution by the code from the code converter 85.

  As a method of sequentially calculating the scanning line position of the input image from the scanning line position of the output image in the image processing units 70 to 73, if the number of scanning lines of the input image is B and the number of scanning lines of the output image is A, the output The nth scanning line of the image is the calculation result of (n−1) × B / (A−1) +0.5, where N is the integer part, the scanning line of the input image shown by the N, N + 1th line Image processing can be performed.

  A block diagram for performing this calculation is shown in FIG. The arithmetic circuit includes a subtracting unit 89 that performs subtraction of (n−1), a subtracting unit 90 that performs subtraction of (A-1), a dividing unit 91 that divides B by the output of the subtracting unit 90, and this division The multiplication unit 92 that multiplies the output of the unit 91 and the output of the subtraction unit 89, and the addition unit 93 that adds 0.5 to the output of the multiplication unit 92.

  However, since the calculation result is a numerical value determined by the resolution of the input image as described above, a numerical value corresponding to a resolution assumed in advance is held as an LUT, and a numerical value of the LUT required for the detected resolution is obtained. By using it, it is not necessary to perform calculation every time the resolution is detected, and a logic circuit used for the calculation is not required, and the circuit scale can be reduced.

  The storage element used for the LUT can use a ROM such as a mask ROM to reduce the cost when mass-produced, but the contents cannot be changed. In the eighth embodiment, the number of pixels of the light modulation element changes (changes due to replacement of the light modulation element or a display method using only a part), and the display method itself does not change (when time-division display is not performed) As long as the contents of the LUT do not change. In addition, when a new resolution needs to be added, it is possible to cope by selecting a storage element that can be additionally written. As a rewritable storage element, an EEPROM, a flash ROM, an EPROM, or the like can be used. EPROM can be erased by ultraviolet irradiation and can be electrically written. The process of applying ultraviolet rays during erasure is complicated.

  On the other hand, it is very preferable to use an EEPROM or flash ROM that can be electrically written and erased, because the contents of the LUT can be rewritten from the outside as needed while being mounted on the substrate. Note that the ROM and rewritable storage elements used for these LUTs have a slow response speed when used alone, so that logic elements such as ASICs for realizing logic, PLDs such as gate arrays and FPGAs, and logic elements such as ASICs are used. It is very preferable that a storage element with a high response speed is provided therein and at least a necessary part is copied and used so that processing can be performed without being affected by the response speed of the storage element. In addition, when the capacity of a memory element having a high response speed inside the above-described logic element is sufficient, by using the memory element in the logic element directly as an LUT, high speed and a memory element to be mounted outside can be obtained. It is very preferable that the cost can be reduced by reducing the number of parts.

  As described above, according to the eighth embodiment, a method for controlling the input / output of the storage means 74 to 78 necessary for performing image processing in parallel for each resolution is stored in the LUTs 83 and 87 in advance, and the resolution of the input image is determined. The input / output of the storage means 74 to 78 can be controlled in accordance with the control method read from the LUTs 83 and 87 corresponding to the above, so that the circuit scale required for the control is reduced as compared with the case where the sequential control method is calculated according to the resolution. This can reduce the component cost.

  Next, a ninth embodiment of the present invention will be described. The ninth embodiment uses the image processing apparatus that processes the input image data in the above sixth to eighth embodiments to generate output image data, and performs display in which time division display is performed by dividing the output image data into a plurality of subframes. In this method, a light deflecting element vertically aligned using a ferroelectric liquid crystal was used as a light modulating element for deflecting an image of each sub-frame for time division display to a position corresponding to the image.

  In the ninth embodiment, the light deflection element deflects the light from the light modulation element to a position corresponding to each subframe and displays an image corresponding to the deflected position to display the image of the light modulation element in a time division manner. Displays an image with more pixels. As the light deflection element, the light modulation element shown in FIG. 11 of the fourth embodiment is used.

  Since this optical deflection element uses a ferroelectric liquid crystal, the response speed is fast. Further, since this optical deflecting element deflects in the state of the liquid crystal 50 aligned perpendicular to the substrates 47 and 48, the controllability of the deflection amount is good and it becomes possible to deflect it to a required position. Of course, in the ninth embodiment, since there are no moving parts by using liquid crystal, quietness can be realized.

In the ninth embodiment, two light deflection elements whose light shift directions are orthogonal to each other are used. By using a ferroelectric liquid crystal that is vertically aligned to the light deflection element, the deflection amount and the controllability by the electric signal are good, and the deflection of the light that does not generate the operation sound can be executed, and a good image can be obtained. I was able to get it.
In the ninth embodiment, the optical system shown in FIG. 13 of the fifth embodiment is used. A projection display device was configured using the light deflecting element and three reflective liquid crystals on silicon (hereinafter referred to as LCOS) that modulate reflected light as the light modulating element.

  In the ninth embodiment, a display device can be configured by using the image processing apparatus without using a storage element for subframes that has been necessary in the past, and the component cost of the storage element and the storage element are controlled. Therefore, the control circuit necessary for the system is no longer necessary, and the cost can be reduced by reducing the component cost and the circuit scale.

  According to the ninth embodiment, by using the image processing means 70 to 73 according to the sixth to eighth embodiments, the light modulation element and the light deflection element are used, and the resolution of the light modulation element is exceeded by time division display. A display device that displays an image having a resolution of 1 can be provided at low cost by reducing the capacity of a storage element used in a subframe for performing time-division display.

It is a block diagram which shows the example of a data control circuit of Embodiment 1 of this invention. It is a block diagram which shows the other example of a data control circuit of the same Embodiment 1. It is a figure which shows the display state in the pixel unit of the same Embodiment 1. FIG. It is a figure which shows the pixel of the input image of each Embodiment 1, and each sub-frame. It is a block diagram which shows the division means of Embodiment 1. It is a figure which shows the relationship between each select signal Sel1, Sel2, Sel3 of the division means, Sel1-3, and the pixel data of each sub-frame 1-4. It is a figure which shows the output state of the image decomposed | disassembled into the pixel shift of Embodiment 1. FIG. It is a figure which shows the timing of the method of performing the pixel shift of Embodiment 1. It is a figure which shows the timing of the method of performing the pixel shift of Embodiment 2 of this invention. It is a block diagram which shows after the processing circuit which performs the image processing of Embodiment 3 of this invention. It is sectional drawing which shows the structure of the optical deflection | deviation element in Embodiment 4 of this invention. It is a figure which shows the state of the liquid crystal of the same optical deflection | deviation element. It is a conceptual diagram which shows the optical system of Embodiment 5 of this invention. It is a block diagram which shows Embodiment 6 of this invention. It is a figure which shows the positional relationship of the pixel of the input image of Embodiment 6 and the pixel of an output image. It is a figure which shows the 1-frame output image of the same Embodiment 6, and the pixel of each sub-frame 1-4. 18 is a flowchart illustrating a write control flow for a line buffer of a write control unit according to the sixth embodiment. It is a figure showing operation of each line buffer of Embodiment 6. It is a figure which shows the relationship between the input pixel of the same Embodiment 6, and an output pixel. It is a flowchart which shows the line buffer 7 control flow of Embodiment 7 of this invention. It is a flowchart which shows a part of resolution detection flow of Embodiment 8 of this invention. It is a flowchart which shows a part of other resolution detection flow. It is a flowchart which shows another part of the same resolution detection flow. It is a block diagram which shows the resolution detection part of the said Embodiment 8. It is a figure which shows the arithmetic circuit which calculates the scanning line position of the input image of the said Embodiment 8. It is a figure which shows the relationship between the scanning line of each output image of the said Embodiment 6, and the scanning line of the input image required for a process. It is a figure which shows the relationship between the scanning line of each other output image of the said Embodiment 6, and the scanning line of the input image required for a process. It is a figure which shows the definition of each variable of the said Embodiment 6. FIG. It is a figure which shows the definition of each variable of the said Embodiment 7. It is a figure which shows the definition of each symbol of the said Embodiment 8.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11, 40 Combination means 12 Frame buffer 13, 41 Light modulation element display control part 14, 45 Light modulation element 15 Dividing means 16-23, 32-39, 74-78 Line buffer 24 Sub-frame division control part 25-27 Demultiplexer 28 to 31 processing circuit 42 subframe control unit 44 combination means controller 67, 68 storage means 69 storage means control means 70 to 73 image processing section 79 write control section 80 read control section 81 subframe selection section 82 horizontal synchronization signal counter 83 , 87 LUT
84, 88 Subtractor / Comparator 85 Code converter 86 Clock signal counter

Claims (15)

A data control circuit that divides a display frame into m (integers greater than or equal to 2) subframes, and outputs the m subframes in parallel for every n (integer greater than or equal to 2) subframes,
Dividing means for dividing the display frame into m subframes;
Combining means for combining the subframe divided into m pieces by the dividing means into the subframe divided into n pieces,
The subframe output in parallel is a combination of n subframes obtained by dividing the same display frame regardless of m and n (m ≠ n or m = n). Control circuit. The data control circuit according to claim 1,
The dividing means includes changing means for changing a combination of n subframes for each display frame,
The changing means includes means for indicating an order of n subframes, selects the subframe to be output in parallel according to the order of the subframes, and continues at the end of the order of the subframes. Returning to the head of the order, the order of the subframes is cyclically repeated, and the subframes divided from the display frames are used to maintain the order and create the subframe combinations. Data control circuit. The data control circuit according to claim 1 or 2,
A plurality of image processing means for processing the image data of the display frame;
The plurality of image processing means is used for each subframe obtained by dividing the display frame, and output data of the plurality of image processing means is pixel data of each subframe, and is processed in parallel for each subframe. Data control circuit. In the data control circuit according to any one of claims 1 to 3,
The display frame is composed of a plurality of scanning line data, and the scanning line data is composed of a plurality of pixel data.
A plurality of storage means for storing pixel data of m subframes divided by the dividing means for each subframe;
Input / output control means for controlling input / output of the storage means;
The input / output control means controls the operation for storing the pixel data of each subframe divided by the dividing means in the storage means and the operation for outputting from the storage means for each scanning line of the display frame. A characteristic data control circuit. In a display device that has a light modulation element that modulates light from a light source according to an input signal and a light deflection element that deflects light modulated by the light modulation element, and performs time-division display of an image,
A display control circuit for controlling display of the light modulation element;
The display control circuit is means for inputting a plurality of image data in parallel and sequentially outputting each image data to the light modulation element, and the data control circuit according to any one of claims 1 to 4. A display device characterized in that time-division display is performed by displaying each subframe corresponding to each deflection position by the light deflection element on the light modulation element. The display device according to claim 5,
A display device characterized in that a liquid crystal composed of a chiral smectic C phase having homeotropic alignment is used for the light deflection element. Each pixel data of the input image having the scanning line number M (M ≧ 1) is processed to generate each pixel data of the output image having the scanning line number N (N ≧ 1), and one frame of the output image is at least In an image processing apparatus that decomposes into a plurality of subframes and outputs pixel data of the output image for each subframe,
Each of the plurality of sub-frames is made up of pixels every number of scanning lines i (i ≧ 1) in the output image, and a plurality of images for simultaneously generating pixel data of the output image for each of the plurality of sub-frames. An image processing apparatus comprising: a processing unit; and an image input unit that inputs pixel data of the input image corresponding to each of the plurality of image processing units. The image processing apparatus according to claim 1.
Each of the plurality of sub-frames is composed of pixels in the output image data at every scanning line number i (i ≧ 1) and every pixel number j (j ≧ 1). Image processing device. The image processing apparatus according to claim 7 or 8,
The image input means includes
First storage means for storing input image data, comprising at least a plurality of storage means capable of independent writing and reading control;
A write control unit having a function of selecting the input pixel data corresponding to each of the plurality of image processing units and writing to the first storage unit;
An image processing apparatus comprising: the plurality of storage units; and an output control unit having a function of selecting the plurality of image processing units and outputting input pixel data corresponding to the plurality of image processing units. The image processing apparatus according to claim 9.
The image processing apparatus according to claim 1, wherein the input pixel data written to each storage means is at least input pixel data of one scanning line of the input image. The image processing apparatus according to claim 9 or 10,
In the writing control to the first storage unit, the writing control unit sequentially updates each time the storage unit generates image data of one scanning line of the subframe in the image processing unit. Performing the update of the designated number by designating the number of scanning lines of the input image to be newly written to the first storage means, which is necessary for the image processing apparatus to perform processing at the time of writing. An image processing apparatus. The image processing apparatus according to claim 11.
In the input control of the scanning line of the corresponding input image from the first storage unit to the image processing unit, the output control unit performs processing from one scanning line of the input image. In this case, the first storage means for storing the scanning lines necessary for the processing is designated, and the case where the image processing unit requires k scanning lines (k> 1) of the input image is applicable. An image processing apparatus for designating at least one of the plurality of storage means for storing scanning lines to be stored.   The image processing apparatus according to claim 9, further comprising a resolution detection unit that detects a resolution of an input image, wherein at least one of the write control unit and the output control unit is controlled. A control method is stored in advance in a lookup table corresponding to at least the resolution detected by the resolution detection unit, and the write control unit and the write control unit using the lookup table corresponding to the resolution detected by the resolution detection unit An image processing apparatus that controls one or both of the output control units. In the image processing device according to any one of claims 7 to 13,
A second storage unit having a storage capacity of at least one frame of the input image data; the input image data is once stored in the second storage unit; from the second storage unit 2 to the image An image processing apparatus for inputting the input image data to an input means. The image processing apparatus according to any one of claims 7 to 14, a light modulation element that modulates a reflection amount or a transmission amount of incident light by an image signal from the image processing apparatus, and the light modulation element A light source and an optical system for irradiating light, and a light deflection element for deflecting the light modulated by the light modulation element, and a subframe corresponding to a position deflected by the deflection element is formed by the light modulation element. A display device that displays images by time-division display.

Images