JP2006237471A - Semiconductor wafer, semiconductor element using the same, wafer level chip size package, and method for manufacturing semiconductor element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor wafer which can avoid any dangers of generation of chipping, cracking, burring or the like in the peripheral edge of a semiconductor chip, a semiconductor element using the wafer, a wafer level chip size package (WLCSP), and also a method for manufacturing the semiconductor element. <P>SOLUTION: The semiconductor wafer has a plurality of integrated circuit formation regions 23, 23 defined by a scribe region 22 on a surface 21a of a silicon substrate 21. Each of the integrated circuit formation regions 23, 23 is formed thereon with an integrated circuit 24. A resin sealing layer 25 is formed on the surface 21a including these integrated circuits 24, 24. A groove 26 wider than a width w of a cutting groove formed in the scribe region 22 is formed on the rear surface 21b of the silicon substrate 21 at a position corresponding to the scribe region 22. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor wafer, a semiconductor device using the same, a wafer level chip size package (WLCSP), and a method for manufacturing a semiconductor device, and more particularly, using a cutting device such as a dicing blade. This is related to a technology that can prevent chipping (shell-shaped chipping) or cracking at the periphery of the semiconductor chip when the semiconductor wafer is cut and separated into individual semiconductor chips at the scribe region. is there.

In recent years, as in notebook personal computers, digital camera-equipped mobile phones, etc., the progress of miniaturization, thinning, and weight reduction of electronic devices has been remarkable, replacing the conventional dual inline package (Dual Inline Package). Chip-sized semiconductor elements have been used.
As a chip size semiconductor element, for example, a chip size package (CSP: Chip Size Package) in which an integrated circuit is formed on the surface of a semiconductor substrate and a resin seal is formed so as to cover the integrated circuit is proposed and put into practical use. It is provided.

In this CSP, a plurality of integrated circuits are formed vertically and horizontally on the surface of a semiconductor substrate, a lattice-like region surrounding each integrated circuit is used as a scribe region, and resin sealing is performed so as to cover these integrated circuits. It is produced by dicing (cutting) the semiconductor substrate along the scribe region from the resin-sealed side using a dicing blade.
In this case, the semiconductor substrate may be warped or cracked during the dicing process. In order to prevent the warping or cracking, for example, wafers having the following structures (1) to (3) have been proposed.

(1) A wafer in which a boundary groove corresponding to the boundary line of an integrated circuit is formed on the back surface of a silicon substrate using a dicing blade, and the surface of the silicon substrate is sealed with a resin.
The silicon substrate is cut along the boundary groove from the surface side using the dicing blade described above to form a CSP (for example, see Patent Document 1).
(2) A wafer in which a groove or V groove having a rectangular cross section is formed in a scribe region on the surface of the silicon substrate, and the surface of the silicon substrate including the groove is resin-sealed.
Using a thin dicing blade, the silicon substrate is cut from the surface side along a rectangular groove or V-groove to obtain a CSP (see, for example, Patent Documents 2 and 3).
(3) A wafer in which a wide groove is formed in a scribe region on the surface of the silicon substrate, and the surface of the silicon substrate including the groove is resin-sealed.
By grinding (grinding) the back surface of this silicon substrate, this wide groove is exposed on the back surface side of the silicon substrate, and the above silicon substrate is cut along the groove from the front surface side using a thin dicing blade. CSP (see, for example, Patent Document 4).

FIG. 8 is a cross-sectional view showing the silicon wafer of the above (1). In the figure, 1 is a silicon substrate, 2 is a scribe region of the surface (one main surface) 1a of the silicon substrate 1, and 3 is a scribe region 2. Partitioned integrated circuit formation region, 4 is an integrated circuit formed in the integrated circuit formation region 3, 5 is a resin sealing layer covering the entire surface 1a including the integrated circuits 4 and 4, and 6 is a back surface (others) of the silicon substrate 1. 1 is a boundary groove formed at a position corresponding to 1b and the scribe region 2.
The boundary groove 6 is formed using a dicing blade having a thickness of approximately 100 μm.
When producing CSP using this silicon wafer, the method of cut | disconnecting the resin sealing layer 5 and the silicon substrate 1 from the surface side along the boundary groove | channel 6 using said dicing blade is taken.
JP 2000-124168 A JP 2000-195862 A JP-A-11-111896 JP 2001-085363 A

By the way, in the conventional wafer (1), when the CSP is manufactured, the silicon substrate 1 is cut from the surface 1a side by using a dicing blade having a thickness substantially the same as the width of the scribe region 2. As shown in FIG. 9, when the dicing is completed between the position of the dicing groove 12 cut by the dicing blade 11 from the front surface 1a side and the boundary groove 6 on the back surface 1b side, the dicing is completed. As shown in FIG. 10, there is a problem in that chipping (shell-shaped chipping) 13, cracks 14, burrs 15, and the like are generated at a portion where the dicing groove 12 and the boundary groove 6 are connected in the silicon substrate 1.
The problem that the chipping 13, the crack 14, the burr 15 and the like are generated in the conventional wafer (2) or (3) is the same problem in the wafer for manufacturing the CSP. is there.

  The present invention has been made in view of the above circumstances, and even when a semiconductor wafer is cut and separated in a scribe region by using a cutting device such as a dicing blade, this semiconductor chip is also used. It is an object of the present invention to provide a semiconductor wafer that does not cause chipping, cracks, burrs and the like in the peripheral edge of the semiconductor device, a semiconductor element using the semiconductor wafer, a wafer level chip size package, and a method for manufacturing the semiconductor element.

In order to solve the above-mentioned problems, the present invention provides the following semiconductor wafer, a semiconductor device using the same, a wafer level chip size package, and a method for manufacturing the semiconductor device.
That is, the semiconductor wafer of the present invention has a plurality of integrated circuit formation regions partitioned by a scribe region on one main surface of a semiconductor substrate, and an integrated circuit portion is formed in each of these integrated circuit formation regions. A semiconductor wafer in which a sealing layer made of an organic polymer compound is formed on the one main surface including an integrated circuit portion, and in a region corresponding to the scribe region on the other main surface of the semiconductor substrate, A groove having a width wider than that of the scribe region is formed.

In this semiconductor wafer, a groove wider than the scribe region is formed in a region corresponding to the scribe region on the other main surface of the semiconductor substrate, so that the scribe region is cut using a cutting device such as a dicing blade. When cutting, even if the cutting device is displaced with respect to the scribe region, the cutting groove formed by the cutting device will be within the range of the wide groove, and the cutting groove and the wide groove There is no risk of chipping, cracking, burrs, etc. occurring on the cut surface of the semiconductor substrate where the groove is connected.
This eliminates the possibility of chipping, cracks, burrs, etc. on the cut surface of the semiconductor substrate even when the semiconductor wafer is cut and separated in the scribe region using a cutting device such as a dicing blade. This increases the reliability of the semiconductor substrate.

The bottom of the groove is characterized in that the center is deeper than the side.
The longitudinal section of the bottom of the groove is preferably any one of a V shape, a U shape, and an arc shape.
Such a configuration further eliminates the possibility of chipping, cracks, burrs and the like occurring on the cut surface of the semiconductor substrate.

The width of the groove is 1.2 times or more and 1.4 times or less of the width of the cutting groove formed in the scribe region at the time of cutting.
The depth of the deepest portion of the groove is 20% or more and 70% or less of the thickness of the semiconductor substrate.
With such a configuration, there is no possibility that chipping, cracking, burrs, and the like are generated on the cut surface of the semiconductor substrate, and the mechanical strength of the semiconductor substrate can be sufficiently maintained.

The semiconductor device of the present invention is a semiconductor device using the semiconductor wafer of the present invention, wherein the semiconductor substrate and the sealing layer are cut at the scribe region.
With such a configuration, there is no possibility that chipping, cracks, burrs, and the like occur on the cut surface of the semiconductor substrate. Thereby, the product yield of the semiconductor element is improved and the reliability is also increased.

It is preferable that the peripheral part of the other main surface of the semiconductor substrate cut in the scribe region is inclined with respect to the side surface of the semiconductor substrate.
By adopting such a configuration, there is no possibility that chipping, cracks, burrs, etc. occur on the cut surface of the semiconductor substrate. Thereby, the product yield of the semiconductor element is further improved, and the reliability is further increased.

A wafer level chip size package according to the present invention comprises the semiconductor element according to the present invention.
With such a configuration, there is no possibility of occurrence of chipping, cracks, burrs, and the like, and a wafer level chip size package with high product yield and high reliability can be realized.

  The method for manufacturing a semiconductor device of the present invention has a plurality of integrated circuit formation regions partitioned by a scribe region on one main surface of a semiconductor substrate, and an integrated circuit portion is formed in each of these integrated circuit formation regions. A method of manufacturing a semiconductor device comprising a sealing layer made of an organic polymer compound on the one principal surface including the integrated circuit portion, and corresponding to the scribe region on the other principal surface of the semiconductor substrate A groove wider than the scribe region is formed in a region to be formed, and then a sealing layer made of an organic polymer compound is formed on the one main surface including the integrated circuit portion, and then the semiconductor substrate and the sealing are formed. The integrated circuit portions are individually separated by cutting a stop layer from the sealing layer side along the scribe region.

  In this method of manufacturing a semiconductor element, a groove wider than the scribe region is formed in a region corresponding to the scribe region on the other main surface of the semiconductor substrate, and then the main circuit including these integrated circuit portions. Since the integrated circuit portion is individually separated by forming a sealing layer made of an organic polymer compound on the surface and then cutting the scribe region and the groove from the one main surface side, the semiconductor substrate As a result, a semiconductor element can be obtained which is free from the occurrence of chipping, cracks, burrs and the like on the cut surface. Thereby, a semiconductor element with high product yield and reliability can be obtained.

  According to the semiconductor wafer of the present invention, since a groove wider than the scribe region is formed in a region corresponding to the scribe region on the other main surface of the semiconductor substrate, a cutting device such as a dicing blade is formed on the scribe region. Even when the cutting device is misaligned with respect to the scribe area, cutting, cracks, burrs, etc. can be prevented from occurring on the cut surface of the semiconductor substrate. The product yield and reliability of the subsequent semiconductor substrate can be improved.

  According to the semiconductor element of the present invention, since the semiconductor substrate and the sealing layer are cut at the scribe region, it is possible to prevent occurrence of chipping, cracks, burrs, and the like on the cut surface of the semiconductor substrate. . Therefore, the product yield of semiconductor elements can be improved and the reliability can be increased.

  According to the wafer level chip size package of the present invention, since the semiconductor element of the present invention is provided, it is possible to prevent chipping, cracks, burrs and the like from occurring on the cut surface of the semiconductor substrate. Therefore, a wafer level chip size package with high product yield and reliability can be realized.

  According to the method for manufacturing a semiconductor device of the present invention, a groove wider than the scribe region is formed in a region corresponding to the scribe region on the other main surface of the semiconductor substrate, and then the integrated circuit portion is included. By forming a sealing layer made of an organic polymer compound on one main surface and then cutting the scribe region and the groove from the one main surface side, the integrated circuit parts are individually separated, so that the cut surface of the semiconductor substrate Thus, a semiconductor element free from chipping, cracks, burrs and the like can be obtained. Therefore, a semiconductor element with high product yield and reliability can be obtained.

Embodiments of a semiconductor wafer, a semiconductor device using the same, a wafer level chip size package (WLCSP), and a method for manufacturing a semiconductor device will be described with reference to the drawings.
These embodiments are specifically described for better understanding of the gist of the invention, and do not limit the present invention unless otherwise specified.

“First Embodiment”
FIG. 1 is a cross-sectional view showing a silicon wafer (semiconductor wafer) used in manufacturing the WLCSP of the first embodiment of the present invention. In the figure, 21 is a silicon substrate (semiconductor substrate), and 22 is a silicon substrate 21. , A scribe region of the surface (one main surface) 21a, 23 is an integrated circuit formation region partitioned by the scribe region 22 of the surface 21a of the silicon substrate 21, 24 is an integrated circuit (part) formed in the integrated circuit formation region 23, 25 is a resin sealing layer covering the entire surface 21 a including the integrated circuits 24, 24, and 26 is formed at a position corresponding to the back surface (other main surface) 21 b of the silicon substrate 21 and the scribe region 22 and wider than the scribe region 22. The bottom surface of the groove 26 is a flat surface.

  In this silicon wafer, actually, a redistribution layer, a Cu post, a bump electrode, and the like are formed on the integrated circuits 24, 24. The explanation is omitted.

The width W of the groove 26 is preferably 1.2 times or more and 1.4 times or less the width w of the cutting groove formed in the scribe region 22 when cutting using a cutting device such as a dicing blade. Is 1.22 times or more and 1.33 times or less, more preferably 1.28 times.
For example, when the width w of the cutting groove is 25 to 83 μm, the width W of the groove 26 is 35 to 100 μm, and when the width w of the cutting groove is more preferably 30 to 45 μm, the width W of the groove 26 is 40 to 55 μm, Furthermore, when the width w of the cutting groove is 35 μm, which is more preferable, the width W of the groove 26 is 45 μm. The width of the scribe region 22 is approximately 120 μm, which is the width w of the cutting groove plus the amount of misalignment of the dicing blade.

  Here, the reason why the width W of the groove 26 is limited as described above is that if it is less than 1.2 times the width w of the cutting groove, there is a possibility that the displacement of the dicing blade cannot be absorbed. If it exceeds 1.4 times, there may be a problem in strength or the influence of interference with the horizontal line.

Further, the depth D of the deepest portion of the groove 26 is preferably 20% or more and 70% or less of the thickness t of the silicon substrate 21, more preferably 30% or more and 60% or less, and further preferably 50%.
Here, the reason why the depth D of the deepest portion of the groove 26 is limited as described above is that if the thickness is less than 20% of the thickness t, there is no difference in the effect whether or not the groove is provided. In addition, if it exceeds 70%, the strength is insufficient.

Next, a method for manufacturing the WLCSP of this embodiment will be described.
Here, the width of the cutting groove formed in the scribe region 22 by the dicing blade at the time of cutting will be described as w.
First, as shown in FIG. 2A, an integrated circuit 24 is formed in each of the integrated circuit formation regions 23 partitioned by the scribe region 22 on the surface 21a of the silicon substrate 21 by a normal WLCSP manufacturing process.

Next, as shown in FIG. 2B, a dicing blade 31 having a blade thickness larger than the width w of the cutting groove formed in the scribe region 22 is used to correspond to the scribe region 22 on the back surface 21 b of the silicon substrate 21. A groove 26 is formed at the position.
Here, it is assumed that a margin of misalignment of 5 to 25 μm, preferably a margin of misalignment of 15 μm or more is expected in each thickness direction with respect to the thickness of a dicing blade 34 described later.

Therefore, the thickness of the dicing blade 31 is 35 to 100 μm when the width w of the cutting groove is 25 to 83 μm, and 40 to 55 μm when the width w of the cutting groove is more preferably 30 to 45 μm. Further, when the width w of the cutting groove is more preferably 35 μm, the width is 45 μm.
The rotation speed of the dicing blade 31 is 20000 to 60000 rotations / minute, preferably 30000 rotations / minute.
The cutting speed is 30 to 70 mm / second, preferably 40 mm / second, with respect to the silicon substrate 21.
As a result, a groove 26 wider than the width w of the cutting groove formed in the scribe region 22 is formed.

Next, the back surface 21b of the silicon substrate 21 is ground using a grinder such as a grinder.
For example, the rotation speed of the grinder is 4000 to 8000 rotations / minute, preferably 5000 rotations / minute, and the grinding amount of the back surface 21b is 200 to 450 μm, preferably 225 μm.
Thereby, the burr | flash etc. which arose when forming the groove | channel 26 by the dicing blade 31 are scraped off, and the back surface 21b turns into a flat surface which has predetermined | prescribed flatness.

  Next, as shown in FIG. 2C, a liquid insulating resin 32 is applied so as to cover the entire surface 21a including the integrated circuits 24, 24, and then ultraviolet (UV) 33 or the like is applied to the insulating resin 32. Is cured by curing to form a resin sealing layer 25. The liquid insulating resin 32 is preferably a two-component epoxy resin or a polyimide resin in consideration of workability and the like, but may be a one-component resin depending on the process.

Next, the surface of the resin sealing layer 25 is polished by chemical mechanical polishing (CMP) or the like to expose the surface of the Cu post (not shown).
Next, as shown in FIG. 2D, the resin sealing layer 25 and the silicon substrate 21 are cut along the scribe region 22 using a dicing blade 34 having a width w of the cutting groove. Note that the width of the scribe region 22 is approximately 120 μm.

  In this case, even if the dicing blade 34 has a positional deviation d ′ (about 10 μm) in the direction of the arrow in the drawing, since the positional deviation d ′ is within the range of the groove 26, the cutting by the dicing blade 34 is performed. Even when the cutting groove 35 reaches the groove 26, there is no possibility that chipping, cracks, burrs, etc. occur on the cut surface of the silicon substrate 21 where the cutting groove 35 and the groove 26 are connected.

FIG. 3 is a cross-sectional view showing the WLCSP obtained in this manner. A notch 36 having a rectangular cross section constituting a part of the groove 26 is formed on the peripheral edge of the back surface 21b of the silicon substrate 21. FIG. ing.
In the notch 36, no chipping, cracks, burrs or the like due to cutting by the dicing blade 34 occur.
Therefore, a WLCSP free from chipping, cracks, burrs, etc. can be obtained on the cut surface of the silicon substrate 21, and a WLCSP with high product yield and reliability can be obtained.

  As described above, according to the silicon wafer of the present embodiment, the groove 26 wider than the scribe region 22 is formed at the position corresponding to the back surface 21b of the silicon substrate 21 and the scribe region 22, so that the scribe region 22 is When cutting with the dicing blade 34, even if the dicing blade 34 has a positional deviation d ′, the positional deviation d ′ can be accommodated within the groove 26, and the silicon substrate 21 can be cut. It is possible to prevent chipping, cracks, burrs and the like from occurring on the surface.

  According to the WLCSP manufacturing method of the present embodiment, the scribe region 22 is positioned at a position corresponding to the scribe region 22 on the back surface 21 b of the silicon substrate 21 using the dicing blade 31 that is thicker than the width w of the cutting groove of the scribe region 22. Since the wider groove 26 is formed, it is possible to obtain a WLCSP that is free from the occurrence of chipping, cracks, burrs, and the like on the cut surface of the silicon substrate 21, and thus it is possible to obtain a WLCSP with a high product yield and high reliability. it can.

“Second Embodiment”
FIG. 4 is a cross-sectional view showing a silicon wafer (semiconductor wafer) used in manufacturing the WLCSP of the second embodiment of the present invention. The silicon wafer of this embodiment is the silicon of the first embodiment described above. The difference from the wafer is that in the silicon wafer of the first embodiment, the bottom surface of the groove 26 is a flat surface, whereas in the silicon wafer of this embodiment, the bottom surface of the groove 41 is deepest at the center. It is the point made into the V-shaped cross section so that it may become a part.

The width W and the depth D of the deepest portion of the groove 41 are exactly the same as the width W and the depth D of the deepest portion of the first embodiment.
Further, the inclination angle (θ) of the bottom surface of the groove 41 is preferably 30 to 60 °, more preferably 40 to 50 °, and still more preferably 45 °.

FIG. 5 is a cross-sectional view showing a WLCSP manufactured using the silicon wafer of the present embodiment, and a notch having a trapezoidal cross section forming a part of the groove 41 on the peripheral portion of the back surface 21 b of the silicon substrate 21. A portion 42 is formed.
The inclination angle (θ) of the notch 42 coincides with the inclination angle (θ) of the bottom surface of the groove 41.

This WLCSP can be manufactured in the same manner as the WLCSP of the first embodiment.
In this case, if the cutting edge of the dicing blade is a convex shape (inverted V shape) complementary to the bottom surface of the groove 41, a groove having a V-shaped cross section is formed at a position corresponding to the scribe region 22 on the back surface 21b of the silicon substrate 21. 41 can be formed.
Also in this embodiment, the same operation and effect as in the first embodiment can be achieved.
Even if a U-shaped groove is formed instead of the V-shaped groove 41, the same operation and effect can be obtained.

“Third Embodiment”
FIG. 6 is a cross-sectional view showing a silicon wafer (semiconductor wafer) used in manufacturing the WLCSP of the third embodiment of the present invention, and the silicon wafer of this embodiment is the silicon of the first embodiment described above. The difference from the wafer is that in the silicon wafer of the first embodiment, the bottom surface of the groove 26 is a flat surface, whereas in the silicon wafer of this embodiment, the bottom surface of the groove 51 is the deepest at the center. It is the point which made the cross-sectional arc shape so that it might become a part.

The width W and the deepest depth D of the groove 51 are exactly the same as the width W and the deepest depth D of the groove 26 of the first embodiment.
The curvature radius (r) of the bottom surface of the groove 51 is preferably 30 to 250 μm, more preferably 100 to 150 μm, and still more preferably 125 μm.

FIG. 7 is a cross-sectional view showing a WLCSP manufactured using the silicon wafer of the present embodiment, and a cross-sectional arc-shaped notch that forms a part of the groove 51 at the peripheral portion of the back surface 21 b of the silicon substrate 21. A portion 52 is formed.
The curvature radius (r) of the notch 52 is the same as the curvature radius (r) of the bottom surface of the groove 51.

This WLCSP can be manufactured in the same manner as the WLCSP of the first embodiment.
In this case, if the cutting edge of the dicing blade has an arc shape complementary to the bottom surface of the groove 51, the groove 51 having an arc shape in cross section can be formed at a position corresponding to the scribe region 22 on the back surface 21b of the silicon substrate 21. .
Also in this embodiment, the same operation and effect as in the first embodiment can be achieved.

  In the present invention, since a groove 26 wider than the scribe region 22 is formed in a region corresponding to the scribe region 22 on the back surface 21b of the silicon substrate 21, not only WLCSP but also CSPs other than this type are used. The present invention can be applied to a semiconductor chip, and its industrial effect is very large.

It is sectional drawing which shows the silicon wafer of the 1st Embodiment of this invention. It is process drawing which shows the manufacturing method of WLCSP of the 1st Embodiment of this invention. It is sectional drawing which shows WLCSP of the 1st Embodiment of this invention. It is sectional drawing which shows the silicon wafer of the 2nd Embodiment of this invention. It is sectional drawing which shows WLCSP of the 2nd Embodiment of this invention. It is sectional drawing which shows the silicon wafer of the 3rd Embodiment of this invention. It is sectional drawing which shows WLCSP of the 3rd Embodiment of this invention. It is sectional drawing which shows the conventional silicon wafer. It is sectional drawing which shows a mode that a silicon wafer is cut | disconnected using the conventional dicing blade. It is sectional drawing which shows the problem by the conventional dicing, (a) is sectional drawing which shows a chipping and a crack, (b) is sectional drawing which shows a crack and a burr | flash.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 21 ... Silicon substrate, 21a ... Front surface, 21b ... Back surface, 22 ... Scribe area, 23 ... Integrated circuit formation area, 24 ... Integrated circuit, 25 ... Resin sealing layer, 26, 41, 51 ... Groove, 36, 42, 52 ... notch.

Claims (9)

The one main surface including a plurality of integrated circuit forming regions partitioned by a scribe region on one main surface of the semiconductor substrate, forming an integrated circuit portion in each of the integrated circuit forming regions, and including these integrated circuit portions A semiconductor wafer having a sealing layer made of an organic polymer compound formed thereon,
A semiconductor wafer, wherein a groove wider than the scribe region is formed in a region corresponding to the scribe region on the other main surface of the semiconductor substrate.   2. The semiconductor wafer according to claim 1, wherein the bottom of the groove has a deeper center than the side.   3. The semiconductor wafer according to claim 2, wherein a cross section in the longitudinal direction of the bottom of the groove is any one of a V shape, a U shape, and an arc shape.   4. The semiconductor according to claim 1, wherein a width of the groove is 1.2 times or more and 1.4 times or less of a width of a cutting groove formed in the scribe region at the time of cutting. Wafer.   The depth of the deepest part of the said groove | channel is 20% or more and 70% or less of the thickness of the said semiconductor substrate, The semiconductor wafer of any one of Claim 1 thru | or 4 characterized by the above-mentioned. A semiconductor device using the semiconductor wafer according to any one of claims 1 to 5,
A semiconductor element obtained by cutting the semiconductor substrate and the sealing layer at the scribe region.   7. The semiconductor element according to claim 6, wherein a peripheral portion of another main surface of the semiconductor substrate cut at the scribe region is inclined with respect to the side surface of the semiconductor substrate.   A wafer level chip size package comprising the semiconductor device according to claim 6. The one main surface including a plurality of integrated circuit forming regions partitioned by a scribe region on one main surface of the semiconductor substrate, forming an integrated circuit portion in each of the integrated circuit forming regions, and including these integrated circuit portions A method for producing a semiconductor element, wherein a sealing layer made of an organic polymer compound is formed thereon,
Forming a groove wider than the scribe region in a region corresponding to the scribe region on the other main surface of the semiconductor substrate;
Next, a sealing layer made of an organic polymer compound is formed on the one main surface including the integrated circuit portion,
Next, the semiconductor substrate and the sealing layer are cut from the sealing layer side along the scribe region, whereby the integrated circuit portions are individually separated.

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