JP2006227449A - Display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device capable of displaying a high-definitition video when inputted synchronizing signals are normal and displaying a stable video when the inputted synchronizing signals are out of standard. <P>SOLUTION: In an RGB signal display device in which RGB signals inputted from an analog RGB signal output equipment 1 are synchronized to the synchronizing signals simultaneously inputted, image processed in an image processing section 4 and displayed on a display device 6, the followings are provided between the analog RGB signal output equipment and the image processing section, that is, a plurality of input buffers made of an input buffer (high speed) 2-1 which makes the rising of normal synchronizing signals outputted from the analog RGB signal output equipment more sharp and outputs the signals and an input buffer (a Schmitt trigger) 2-2 which makes non-standard synchronizing signals into stable signals and outputs the signals, a high speed analog SW3 which selects the output from the plurality of input buffers and inputs the selected output to the image processing section and means (3, 7 and 8) which manually or automatically switches the high speed analog SW. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a display device for stably displaying an input analog RGB signal, which is a separate sync signal type, and more particularly to a display device that enables stable image processing by stabilizing an input sync signal.

Conventionally, an AFC circuit is generally used as a device for stabilizing an input synchronization signal.
Further, as a technique for stabilizing a synchronization signal that varies depending on an input source, there is a technique for switching a vertical deflection system time constant or a threshold level as disclosed in Patent Document 1 and Patent Document 2.

  In addition, as disclosed in Patent Document 3 and Patent Document 4, there is a technique for determining the fluctuation of the period of the vertical synchronization signal and switching the sensitivity of the AFC circuit.

  However, the band of the RGB signal is 162 MHz in the UXGA class, and in order to improve display performance, it is necessary to make the rising edge of the synchronization signal used for image processing as steep as possible.

  Therefore, conventionally, as shown in FIG. 3, the synchronization signal output from the analog RGB signal output device 1 is input to the image processing unit 4 ′ via the high-speed buffer 2, so that the synchronization signal used for image processing rises. The highest priority was to improve the display performance by sharpening the display.

However, in some analog RGB signal output devices, the waveform may be distorted depending on the output of a synchronization signal that is not within the signal standard, or the length and impedance of the cable connecting the analog RGB signal output device and the display device.
For example, as shown in FIG. 4B, a sync signal (including a sawtooth waveform) with a slow rise, a sync signal with a low level and a threshold level can be seen.
As described above, when a synchronization signal output from an output device that outputs a synchronization signal that is out of the signal standard is input to the high-speed buffer 2, as shown in FIG. 4C, the image processing unit 4 ′. There is a problem that an extra pulse is generated in the synchronization signal input to the input signal, the timing is shifted and the processing cannot be performed well, and a normal screen display cannot be performed.

Japanese Utility Model Publication No. 59-119671 (first page, FIG. 1) Japanese Utility Model Publication No. 62-152558 (1st page, FIG. 1) JP 63-48968 (page 2-4, Fig. 1) Japanese Patent Laid-Open No. 04-307872 (page 2-3, FIG. 1)

  In view of the above problems, the present invention enables high-definition video display when a normal sync signal is input, and stable video display even when a non-standard sync signal is input. It aims to make it possible.

The present invention relates to a display device in which an input synchronization signal is a separate type video signal, and an image processing unit performs image processing in synchronization with the synchronization signal and displays the image on a display device.
A first input buffer that outputs a normal synchronization signal that is input with a steep rising edge, a second input buffer that outputs a non-normal synchronization signal as a stable signal, the first input buffer, The display device includes switching means for selecting an output from the input buffer and inputting the output to the image processing unit.

  The second input buffer is a display device having hysteresis characteristics.

  The switching means includes a synchronization counter that counts the frequency of a synchronization signal input via the switching means, a memory that stores data of a normal synchronization frequency in advance, and the data stored in the memory and the synchronization The display device is composed of a control unit that switches the switching means by judging whether it is normal or not by comparing the synchronous frequency counted by the counter.

  As described above, according to the present invention, it is determined whether the input synchronization signal is a regular signal or a non-standard signal. If the synchronization signal is a regular synchronization signal, the image processing unit has a steep rise through the high-speed buffer. When a synchronization signal is input, a stable synchronization signal is input to the image processing unit via a Schmitt trigger buffer with hysteresis characteristics in the case of a non-standard synchronization signal. A stable video can be displayed, and a stable video can be displayed even when a non-standard sync signal is input.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail as examples based on the attached drawings.

  FIG. 1 is a schematic block diagram showing a first embodiment of a display device according to the present invention.

In FIG. 1, reference numeral 1 denotes an analog RGB signal output device such as a PC, STB, or DVD that outputs a synchronization signal and an RGB signal.
Reference numeral 10 denotes a display device that displays RGB signals input from the analog RGB signal output device 1.
The display device 10 includes the following blocks.
Reference numeral 2-1 denotes a high-speed buffer that handles regular signals with sharp rises.
2-2 provides hysteresis for the rising and falling voltages, so that extra pulses such as chattering even when a signal with a slow rising edge (including a sawtooth waveform) or a low level threshold signal is input. This is a Schmitt trigger buffer that does not generate
Reference numeral 3 denotes a high-speed analog SW for switching a signal from the high-speed buffer 2-1 and a signal from the Schmitt trigger buffer 2-2.
An image processing unit 4 digitizes the RGB signal input from the analog RGB signal output device 1 based on the synchronization signal input via the high-speed analog SW 3 and performs various image processing. The input synchronization signal And the function of measuring the frequency of the horizontal and vertical synchronizing signals.
Reference numeral 5 denotes an I / O that converts an image processed by the image processing unit 4 into a signal corresponding to the display device 6 and outputs the signal.
Reference numeral 6 denotes a display device such as a plasma display panel or a liquid crystal that displays a video signal input via the I / O 5.
A control unit 7 compares the synchronization frequency measured by the image processing unit 4 with data of the synchronization frequency stored in the flash ROM 8 in advance to determine whether it is normal or not, and switches the high-speed analog SW 3.
Reference numeral 8 denotes a flash ROM which previously stores various normal frequencies of the horizontal synchronizing signal and the vertical synchronizing signal.

Next, the operation of the above configuration will be described with reference to the operation flowchart of FIG.
The high-speed analog SW3 selects the synchronization signal input from the high-speed buffer 2-1 (ST2) so that the display device 10 inputs a normal synchronization signal when the power is turned on or when the input signal is switched (ST1). The data is input to the processing unit 4.
When an RGB signal and a synchronization signal are input from the analog RGB signal output device 1 to the display device 10, first, the image processing unit 4 receives the horizontal and vertical synchronization signals of the synchronization signal input via the high-speed analog SW3. Each frequency (fh, fv) is measured (ST3).
Then, the control unit 7 controls the measured horizontal and vertical synchronization signal frequencies (fh, fv) and the horizontal and vertical synchronization signal reference frequencies (fh0, fv0) stored in the flash ROM 8. (ST4).
In ST4, the comparison results (fh−fh0 = Δfh, fv−fv0 = Δfv) of the respective frequencies are within a predetermined range (Δfh1 to Δfh2, Δfv1 to Δfv2), that is, (Δfh1 <Δfh <Δfh2, Δfv1 <Δfv). In the case of <Δfv2), the selection of the high-speed analog SW3 is made on the high-speed buffer 2-1 side that is currently maintained.
As a result, when the synchronization signal input from the analog RGB signal output device 1 is a regular signal, the comparison result falls within a predetermined range. Therefore, the synchronization signal input to the image processing unit 4 is the high-speed signal. A synchronization signal having a steep rise is input via the buffer 2-1, and predetermined video performance is ensured.

If the comparison result in ST4 indicates that the respective frequencies are out of the predetermined range, the high-speed analog SW3 is switched to the Schmitt trigger buffer 2-2 side (ST5).
That is, when the synchronization signal input from the analog RGB signal output device 1 is not a normal signal, the high-speed analog SW 3 is switched to the Schmitt trigger buffer 2-2 side, and thereby input to the image processing unit 4. A stable frequency measurement result of the synchronization signal to be obtained is obtained, and a stable video can be displayed.

  In the above description, only one Schmitt trigger buffer is used. However, by providing a plurality of hysteresis characteristics and the like, more non-normal signals can be handled.

  As described above, it is determined whether the input synchronization signal is a regular signal or a non-regular signal. If it is a regular synchronization signal, a steep rising synchronization signal is input to the image processing unit via a high-speed buffer. In the case of a non-regular sync signal, a stable sync signal is input to the image processing unit via the Schmitt trigger buffer, so that a high-performance video can be displayed when a regular sync signal is input, Even when a signal is input, a stable video can be displayed.

It is a block diagram which shows one Example of the display apparatus by this invention. It is a flowchart figure for demonstrating operation | movement of one Example of the display apparatus by this invention. It is a block diagram which shows the conventional display apparatus. It is an output waveform diagram of a high-speed buffer in a conventional display device.

Explanation of symbols

1 Analog RGB signal output device 2-1 High-speed buffer 2-2 Schmitt trigger buffer 3 High-speed analog SW
4 Image processing section 5 I / O
6 Display device 7 Control unit 8 Flash ROM 10 Display device

Claims (3)

In the display device in which the input synchronization signal is a separate type video signal, the image processing unit performs image processing in synchronization with the synchronization signal and displays the image on the display device.
A first input buffer that outputs a normal synchronization signal that is input with a steep rising edge, a second input buffer that outputs a non-normal synchronization signal as a stable signal, the first input buffer, And a switching means for selecting and inputting the output from the input buffer to the image processing section.   The display device according to claim 1, wherein the second input buffer has a hysteresis characteristic. The switching means includes a synchronization counter that counts the frequency of a synchronization signal input via the switching means, a memory that stores data of a normal synchronization frequency in advance, data stored in the memory, and the synchronization counter 2. The display device according to claim 1, further comprising: a control unit that compares the counted synchronization frequency to determine whether or not the frequency is normal and switches the switching means.