JP2006208077A - Semiconductor integrated circuit and inspection method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily detect a delay trouble in inspection of a semiconductor integrated circuit. <P>SOLUTION: Gates 101-103, 106, 108, 110-112 in a non-inverter system are extracted out of the gates 101-112. The extracted gates are substituted with gates 101-1 to 103-1, 106-1, 108-1, 110-1 to 112-1 inverted in logics of output states. Inverters 101-2 to 103-2, 106-2, 108-2, 110-2 to 112-2 are added to rear stages of the substituted gates. Data flip-flops 201-204 connect the inverted outputs QN to an SI terminal. A toggle rate of a transmission signal is enhanced inside the circuit by this manner. The delay trouble is easily detected since a frequency of state transition gets high. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a technique for detecting a failure of a semiconductor integrated circuit, and more particularly to a technique that facilitates detection of a delay fault.

  In general, LSI (Large Scale Integrated Circuit) failures are classified into several types such as open / short failures on wiring, stuck-at failures (degenerate failures fixed to 0/1 logic), and the like. In the simulation performed at the time of design, a stack-at fault model is mainly assumed, and a test pattern for detecting the fault has been created.

  However, in recent years, with the miniaturization and speeding up of LSIs, it has become necessary to consider physical defects that affect the timing (delay) of signals. For example, it is a defect in which a certain wiring is in a state immediately before disconnection. Such a delay fault (AC fault) cannot be detected as a test pattern for detecting a stuck-at fault model in which the logic does not necessarily change because the signal line is in a high resistance state. It is necessary to provide a test pattern in which logic such as 0 transitions. A test that takes this into account is called an AC fault test (or Transition Delay test).

  A conventional technique for performing an AC fault test is described in Patent Document 1. In this technique, as described in paragraph No. 40 and FIG. 1 in the same document, a selector 2A that can input to the D input terminal by feeding back the inverted output QC of the scan flip-flop is added. Then, as described in paragraphs 46 and 47 of FIG. 5 and FIG. 5, in the actual operating frequency test, the output of the scan flip-flop is inverted before the step 22B for fetching the data of the combinational circuit into the scan flip-flop. Step 22A is added so that the state of the output of the scan flip-flop is reliably changed so that a delay fault can be inspected in the stack-at fault test.

  In addition, as described in paragraphs 55 to 57 and FIG. 9 in the same document, when generating a test pattern using an ATPG (automatic test pattern generation) tool, in addition to the scan test pattern 41 for detecting a stack-at fault. In addition, there is a method of generating scan test patterns 42 and 43 in which data inverted every one cycle is continued for the number of stages of the scan flip-flop, and detecting a delay fault using the scan test patterns 42 and 43. It is disclosed.

Patent Document 2 discloses a technique for configuring a diagnostic scan path in which shift data is inverted for each bid shift in a logical device to be diagnosed. Briefly described with reference to FIG. 1 in the document, an N-type flip-flop SF1 to SFN constitutes an inverted shift register-like scan path. Then, the cooperative operation of the JT flip-flop 108 and the counter 121 determines whether the scan path stage number N is an even number or an odd number, and the output signal Q of the final stage flip-flop SFN is output by the OR gate 105 and the AND gates 106 and 107 according to the determination result. Alternatively, the inverted output / Q is selected and output to the output terminal 5. By adopting such a configuration, in the scan-in or scan-out to the scan path, normal handling is sufficient without considering that the scan path is an inversion type. Further, when a stack-at failure has occurred in the flip-flops SF1 to SFN, the failed flip-flop can be identified by performing a scan-out operation after initializing all the flip-flops SF1 to SFN.
JP 2001-4710 A Japanese Examined Patent Publication No. 61-55133

  However, in the technique described in Patent Document 1, since it is necessary to separately perform an AC fault test in addition to a normal scan test for detecting a stack-at fault, there are problems such as an increase in man-hours in an inspection process and an increase in manufacturing cost. Produce.

  The technique described in Patent Document 2 is a technique specialized for detecting a stack-at fault in a sequential circuit, is not suitable for detecting an AC fault in a sequential circuit, and on the scan path without being conscious of the outside. Since the data is inverted every 1-bit shift, it is not suitable for an application in which a test pattern is given to the combinational circuit or the output of the combinational circuit is captured.

  In view of such circumstances, the present invention has a circuit configuration with a high toggle rate as a circuit to be inspected, and, for example, a delay fault can be detected in a stack-at fault inspection using a normal test pattern. It is an object to provide a technique for facilitating failure detection.

  In order to solve the above problems, the invention according to claim 1 is a logic circuit in which a non-inverter system gate is replaced with an inverter system gate in which the logic of the output stage is inverted, and an inverter is added to the subsequent stage of the inverter system gate. A semiconductor integrated circuit characterized in that is mounted.

  According to a second aspect of the present invention, in the semiconductor integrated circuit according to the first aspect, the scan chain circuit is formed by connecting a plurality of scan flip-flops, and the inverted output terminal of the preceding scan flip-flop is connected to the subsequent scan input. Provide what is connected to the terminal.

  According to a third aspect of the present invention, in the semiconductor integrated circuit according to the first aspect, the scan chain circuit is formed by connecting a plurality of scan flip-flops, and the output terminal and the inverted output of the preceding scan flip-flop via a selector. Provided is a semiconductor integrated circuit in which a terminal in which a terminal is selectively connected to a subsequent scan input terminal is mounted.

  According to a fourth aspect of the present invention, a semiconductor integrated circuit mounted with a scan chain circuit in which a plurality of stages of scan flip-flops are connected so that shift data is inverted at each shift is tested, and the test pattern is determined from the logic of the combinational circuit. And inverts even-numbered bits of the generated test pattern, and then scans into the scan chain circuit and propagates it to the combinational circuit.

  According to the present invention, the non-inverter system gate is replaced with an inverter system gate to improve the toggle rate in the logic circuit, and the state transition of each gate output frequently occurs at the time of signal propagation. There are advantages to be facilitated.

  In addition, if the even-numbered bits of the test pattern are inverted and then scanned into the scan chain circuit, the shift data is propagated to the combinational circuit with a scan chain circuit that inverts every shift. There is an advantage that the toggle rate of the circuit is improved and the detection of the delay fault of the sequential circuit is facilitated.

Embodiments of the present invention will be described below with reference to the drawings.
First, a first embodiment of the present invention will be described with reference to FIGS. In the first embodiment, a netlist is analyzed at the stage of logic synthesis in LSI circuit design, and a non-inverter logic circuit is replaced with an inverter logic circuit. Here, FIG. 1 shows a part of a scan chain circuit using a scan data flip-flop as an example of a circuit to be replaced. However, this replacement processing is performed not only on the scan chain circuit but also on an arbitrary logic circuit on the LSI.

  In FIG. 1, reference numeral 1 denotes a combinational circuit, which includes various gates 101 to 112. Reference numerals 201 to 204 denote data flip-flops constituting the scan chain circuit. In the data flip-flops 201 to 204, a terminal D is a data input terminal, SI is an input terminal at the time of shift operation, SE is an input terminal of an SE signal instructing switching between data input and shift operation, and CK is a clock input Q, Q is a positive output terminal, and QN is an inverted output terminal of Q. During the scanning operation, the shift operation is performed by enabling the SE signal.

  In the above replacement processing, the gates 101 to 112 that are previously defined as non-inverter systems are extracted. In this example, the gates 101 to 103, 106, 108, and 110 to 112 are extracted. Then, the extracted gate is replaced with a gate obtained by inverting the logic of the output stage, and a process of adding an inverter to the subsequent stage of the gate is sequentially performed.

  FIG. 2 shows a circuit configuration after the replacement process. The gate 101 in FIG. 1 is replaced with inverters 101-1 and 101-2 in FIG. A similar replacement process is performed on the gates 102, 103, 106, 108, and 110-112. The inverter gates 103 to 105, 107 and 109 are not changed.

  After the replacement process is completed, the process proceeds to the step of connecting the data flip-flop and configuring the scan chain circuit. Assuming that data flip-flops 201 to 204 are normally connected in order as shown in FIG. 1, in this embodiment, the inverted output terminal QN of the data flip-flop is connected to the data flip-flop of the next stage as shown in FIG. Connect to SI input terminal.

  Next, creation of a test pattern in this embodiment will be described. First, a test pattern is created using a normal stack-at fault model, and the obtained test pattern is subjected to masking processing to create a pattern in which all even-numbered bits are inverted and registered as a test pattern.

  At the time of a scan test, a scan-in operation is performed with the above-described scan chain circuit, and a registered test pattern is serially input to set a signal in each data flip-flop. In this scan-in operation, the shift data is inverted at every shift, so that the inverted signal is set in the even-numbered data flip-flop. Therefore, the even-numbered bits inverted by the masking process are rotated in the normal direction, and the test pattern before the masking process is set in the scan chain circuit. Thereafter, the set pattern is propagated to the combinational circuit, the output is taken into the data flip-flop, and the data flip-flop is caused to perform a scan-out operation to scan out the output result.

  When a signal propagates in the combinational circuit, the combinational circuit is basically composed of the gates of the inverter system as described above, so the toggle rate during signal propagation is high, and if there is a delay fault inside the combinational circuit, There is a high probability that a failure will be reflected in the output. Therefore, it becomes easy to detect the delay fault simultaneously with the inspection of the stack-at fault from the output result scanned out.

  Since the scan chain circuit also has a high toggle rate that shifts the inverted output of the data flip-flop to the subsequent stage, even if a delay fault occurs in the sequential circuit, the probability that the fault is reflected in the scanned-out output result above Therefore, the delay fault of the sequential circuit can be simultaneously checked from the output result scanned out.

  Next, a second embodiment of the present invention will be described. FIG. 3 is a circuit diagram showing a circuit configuration example according to the second embodiment. As shown in the figure, in the second embodiment, when configuring the scan chain circuit, selectors 301 to 303 are interposed between the output portion of the preceding data flip-flop and the input portion of the succeeding data flip-flop. Yes. The selectors 301 to 303 receive the output Q and inverted output QN of the preceding data flip-flop, select Q or QN according to the control signal SE2, and output it to the SI input terminal of the succeeding data flip-flop.

  With such a configuration, the connection of the data flip-flop can be switched between the normal shift mode and the reverse shift mode by switching the control signal SE2. In the normal shift mode, the output Q of the preceding data flip-flop is propagated to the SI input terminal of the succeeding data flip-flop and shifted. In the inverting shift mode, the inverted output QN of the preceding data flip-flop is propagated to the SI input terminal of the succeeding data flip-flop and shifted.

  In the second embodiment, it is not necessary to add a masking process when creating a test pattern, and a test pattern based on a normal stack-at fault model may be registered as it is. At the time of the scan test, the normal rotation shift mode is selected and the test is executed by the same procedure as usual.

  Thereafter, a delay fault test in the inverted shift mode is performed as necessary. In this test, a delay fault can be detected without using a special test pattern, for example, by simply scanning in “1” or “0” after resetting each data flip-flop.

  The first and second embodiments of the present invention have been described in detail above, but the specific configuration is not limited to this embodiment, and includes a design and the like within the scope not departing from the gist of the present invention.

It is a circuit diagram which shows the structure of an example of a logic circuit. 1 is a circuit diagram illustrating a configuration example of a logic circuit according to a first embodiment. It is a circuit diagram which shows the structural example of the logic circuit which concerns on 2nd Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Combination circuit 101-112 ... Gate 201-204 ... Data flip-flop 301-303 ... Selector

Claims (4)

  A semiconductor integrated circuit comprising a logic circuit in which a non-inverter system gate is replaced with an inverter system gate in which the logic of an output stage is inverted and an inverter is added after the inverter system gate.   2. The semiconductor according to claim 1, wherein a scan chain circuit is formed by connecting a plurality of scan flip-flops, wherein an inverted output terminal of a preceding scan flip-flop is connected to a subsequent scan input terminal. Integrated circuit.   A scan chain circuit consisting of multiple stages of scan flip-flops, with the output terminals and inverted output terminals of the preceding stage scan flip-flops selectively connected to the subsequent stage scan input terminals via a selector The semiconductor integrated circuit according to claim 1.   The test pattern is generated from the logic of the combinational circuit, and the test pattern is generated from the logic of the combinational circuit. The test pattern is a semiconductor integrated circuit mounted with a scan chain circuit in which multiple stages of scan flip-flops are connected so that the shift data is inverted every shift. A method for inspecting a semiconductor integrated circuit, wherein the even-numbered bits are inverted, scanned into the scan chain circuit, and propagated to the combinational circuit.

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