JP2006203071A - III-V compound semiconductor single crystal substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a group III-V compound semiconductor single crystal substrate in which the risk of cracking or chipping is reduced by appropriately selecting a peripheral cross-sectional shape even if it is thinner than a conventional standard specification.
A group III-V compound semiconductor single crystal substrate having a diameter D (mm) and a thickness t (mm) is (1/1000) D + 0.2 (mm) ≦ t ≦ (1/1000) D + 0. In the cross section satisfying the relationship of 4 (mm) and orthogonal to the peripheral edge of the substrate, both of the curvature radius Rf (mm) of the edge round of the front outer edge and the curvature radius Rb (mm) of the edge round of the back outer edge Satisfies the relationship of 0.08 (mm) ≦ (Rf, Rb) ≦ 0.4 t (mm).
[Selection] Figure 1

Description

  The present invention relates to a group III-V compound semiconductor single crystal substrate, and more particularly to a cross-sectional shape of the periphery of the substrate that can reduce the incidence of cracks and chips during processing even if the substrate is thinner than conventional standards.

  A compound semiconductor single crystal substrate is generally manufactured through the following steps. That is, first, a compound semiconductor raw material is melted in a crucible or boat, and a single crystal is grown by relatively moving a temperature gradient provided in a predetermined direction from the seed crystal. The grown single crystal has a predetermined crystallographic plane orientation and thickness using, for example, a rotating inner peripheral blade electrodeposited with diamond abrasive grains or a steel wire that travels while being supplied dropwise with abrasive grains. It is cut out into a thin plate called an as-cut (as cut) substrate.

  Since this as-cut substrate is contaminated with abrasive grains, cutting waste, cutting oil, etc., cleaning is performed in order to remove the contamination. Further, a work-affected layer containing fine cracks and strains resulting from cutting is formed on the surface of the as-cut substrate, and such a work-affected layer is preferably removed by wet chemical etching. .

  Next, as shown in the schematic plan view of FIG. 1 (A), the as-cut substrate is processed by diamond wheel grinding so as to form a substantially circular wafer 1 as a whole (Patent Document 1 and Patent Document 2). reference). Such a wafer is also provided with an orientation flat OF (or notch) indicating a specific crystal orientation, as also shown in FIG.

FIG. 1B shows an enlarged example of an edge shape generally adopted in a cross section taken along a broken line 1B-1B orthogonal to the periphery of the wafer 1 in FIG. (See SEMI standards, which are virtually standard in the semiconductor industry). In FIG. 1B, the center of the thickness t of the wafer 1 is represented by an alternate long and short dash line. On the upper side of the alternate long and short dash line, the edge portion of the wafer 1 includes a tapered portion having an angle θ _f with respect to the wafer upper surface in the direction of decreasing the wafer thickness, and an edge having a radius of curvature Rf smoothly connected to the tapered portion. It is processed so as to include a round and a straight portion L smoothly connected to the edge round and along the thickness direction.

Similarly, the lower side of the dashed line in FIG. 1 (B), the edge portion of the wafer 1, and a tapered portion having an angle theta _b on the wafer underside in a direction to reduce the wafer thickness, the tapered portion An edge round having a radius of curvature Rb that is smoothly connected to each other, and a straight portion L that is smoothly connected to the edge round and extends along the thickness direction. In general, from the viewpoint of simple processing, the upper side and the lower side of the alternate long and short dash line in FIG. That is, usually θ _f = θ _b and Rf = Rb.

  The wafer-like substrate 1 subjected to the circular processing as described above is put into the surface polishing step. For example, both main surfaces of the circular substrate 1 are pressure-polished between up-and-down rotating surface plates to which a polishing liquid in which free abrasive grains or a mechanical chemical abrasive is suspended in a solvent is supplied. Normally, after a plurality of double-sided polishing steps to sequentially increase the smoothness, a predetermined one side (surface) of the substrate 1 is finish-polished, and after final wet cleaning or surface treatment, the surface becomes highly sophisticated. A clean mirror polished substrate is obtained.

  Such a semiconductor single crystal mirror polished substrate is put into a device manufacturing process. An electronic operation layer is formed by epitaxially growing a specific semiconductor crystal layer on the front main surface of the substrate or implanting specific ions into the front main surface layer of the substrate. Next, a predetermined semiconductor device is manufactured using a fine processing technique such as resist layer coating, circuit pattern exposure, development, and etching. Thereafter, the substrate back main surface on which the semiconductor device is not usually formed is removed by polishing or grinding, and the substrate is thinned to a thickness of about 100 μm, for example. This is because heat dissipation is improved by thinning the substrate, and heat generated when the semiconductor device operates is efficiently dissipated.

Finally, individual devices manufactured in the substrate surface main surface layer are cut out as chips by dicing or cleaving, and each chip is mounted on a semiconductor device package to become a final product.
Japanese Patent No. 3368799 Japanese Patent Laid-Open No. 11-207583

  A semiconductor device is manufactured through the above-described steps. In particular, in a III-V compound semiconductor single crystal substrate represented by GaAs, InP, etc., the {110} plane is highly cleaved, and processing or handling is performed. There is a high risk of cracking and chipping due to impact inside. Therefore, in the group III-V compound semiconductor single crystal substrate, the risk of cracking or chipping has been avoided by increasing the thickness as compared with the Si substrate or the like. However, as a matter of course, the thick substrate is a factor that deteriorates the material cost of the semiconductor single crystal, the processing cost of the back surface polishing process after device fabrication, and the throughput.

  In view of the problems in the prior art as described above, the present invention pays attention to the fact that the part where the substrate is particularly susceptible to impact in any process of device fabrication is the peripheral part. An object of the present invention is to provide a group III-V compound semiconductor single crystal substrate in which the risk of cracking and chipping is reduced by appropriately setting the cross-sectional shape of the portion.

  According to the present invention, a III-V compound semiconductor single crystal substrate having a diameter D (mm) and a thickness t (mm) is (1/1000) D + 0.2 (mm) ≦ t ≦ (1/1000). In a cross section that satisfies the relationship of D + 0.4 (mm) and is orthogonal to the peripheral edge of the substrate, the curvature radius Rf (mm) of the edge round of the front outer edge and the curvature radius Rb (mm) of the edge round of the back outer edge All are characterized by satisfying the relationship of 0.08 (mm) ≦ (Rf, Rb) ≦ 0.4 t (mm).

  In the cross section orthogonal to the peripheral edge of the substrate, the outermost edge of the substrate includes a straight line portion parallel to the thickness direction, and both of the edge rounds of the front and back outer edge portions having curvature radii Rf and Rb, respectively. It is preferable that the straight portion of the outer end edge is smoothly connected.

  Further, in the cross section orthogonal to the peripheral edge of the substrate, the outermost edge of the substrate may include a convex curve portion having a curvature radius R1 ≧ 0.4 t (mm), and the front and back outer edges respectively having the curvature radii Rf and Rb. Any of the edge rounds of the part may be smoothly connected to the curved part of the outermost edge.

  Further, the edge rounds of the front and back outer edge portions each having the curvature radii Rf and Rb are respectively tapered portions having an angle in the range of 10 ° to 23 ° in the direction of decreasing the substrate thickness with respect to the front surface and the back surface of the substrate. It may be connected smoothly.

  Furthermore, as the III-V group compound semiconductor, either GaAs or InP can be preferably employed.

  According to the present invention, since the peripheral portion of the III-V compound semiconductor single crystal substrate is set to a specific cross-sectional shape, when a semiconductor device is manufactured using the substrate, cracking or chipping of the substrate is reduced. Yield can be improved, and throughput can be improved.

  In the present invention, a substrate that is at least 0.1 mm thinner than the nominal substrate thickness defined by SEMI standards M9.5-95, M9.6-95, and M9.7-2000, which are substantially standard in the semiconductor industry. An object of the present invention is to provide a III-V compound semiconductor single crystal substrate, particularly a GaAs or InP substrate, having a peripheral cross-sectional shape with improved impact resistance.

  At present, the nominal thickness of a GaAs or InP substrate is generally defined as follows according to its diameter specification.

  When the substrate diameter is 100.0 mm or 125.0 mm, the substrate thickness is 0.625 ± 0.025 mm.

  When the substrate diameter is 150.0 mm, the substrate thickness is 0.675 ± 0.025 mm.

On the other hand, in the present invention, the substrate diameter D (mm) is used as a parameter.
D / 1000 + 0.2 (mm) ≦ t ≦ D / 1000 + 0.4 (mm)
A thickness t (mm) defined in the range is proposed.

  More specifically, the substrate thickness according to the present invention can be reduced as follows.

  When the substrate diameter D is 100.0 mm, the thickness t can be reduced within a range of 0.300 to 0.500 ± 0.025 mm.

  When the substrate diameter D is 125.0 mm, the thickness t can be reduced within a range of 0.325 to 0.525 ± 0.025 mm.

  When the substrate diameter D is 150.0 mm, the thickness t can be reduced within a range of 0.350 to 0.550 ± 0.025 mm.

  By using such a thinned substrate, the amount of polishing of the back surface of the substrate after device fabrication described above can be reduced, and the processing cost required for back surface polishing can be reduced and the productivity can be improved.

  On the other hand, as means for reducing cracks and chipping of the substrate in the polishing process on the back surface of the substrate, the curvature radii Rf (mm) and Rb (mm) of the respective edge rounds of the front and back peripheral portions of the substrate are described later by diamond wheel grinding. Formed within the range. In addition, it is desirable to grind the orientation flat part or notch part which is not the circumferential part of the substrate into the same edge cross-sectional shape as the circumferential part. The diamond wheel grinding wheel is preferably made of diamond abrasive grains having a grain size defined by JIS-R6001 and finer than # 500, and more preferably made of abrasive grains finer than # 800.

  In the present invention, it is set within a range of 0.08 (mm) ≦ (Rf, Rb) ≦ 0.4 t (mm), where t is the above-described set substrate thickness.

  More specifically, when the substrate diameter D is 100.0 mm or 125.0 mm, the radius of curvature Rf and Rb of the edge round is set within a range of 0.080 to 0.200 mm. When the substrate diameter D is 150.0 mm, Rf and Rb are set in the range of 0.080 to 0.220 mm. In other words, the curvature radii Rf and Rb of the edge round are set within the range of a function of the substrate thickness t, but if set within the range of the curvature radius of about 0.100 to 0.150 mm, Most preferred for preventing cracks and chipping.

The radius of curvature Rf and Rb of the edge round according to the present invention is smaller than the radius of curvature of 0.250 to 0.300 mm that is generally used at present, and this makes it possible to realize difficulty in cracking and chipping of the substrate. It is. In order to prevent the occurrence of cracking and chipping of a substrate cut out from a single crystal, it is also important that the residual strain in the substrate is small. In the photoelastic strain evaluation such as SIRP (Scanning Infrared Polariscopy) measurement, the substrate main The in-plane average residual strain is preferably 1 × 10 ⁻⁵ or less (reference: M. Yamada et al. J. Crystal Growth 210 pp172-176 (2000) “Residual strain in annealed GaAs single-crystal wafers as determined by scanning infrared polariscopy, X-ray diffraction and topography ”). Further, it is desirable that the crystal defect density EPD (Etch Pit Density) is small in order to take advantage of small in-plane variation of residual strain. Specifically, it is preferable to satisfy EPD ≦ 10,000 cm ⁻² . Furthermore, it is desirable that the final finish on the front and back surfaces of the substrate is a double-sided mirror. It is clear that the effect of preventing the occurrence of cracks and chips by these measures becomes more prominent as the substrate diameter is larger.

  If the specific example of the cross-sectional shape of a board | substrate periphery is shown, with reference to FIG.1 (B), when thickness is set to t = 0.450mm with respect to the board diameter D = 100mm, the edge round of a board | substrate peripheral part will be shown, for example. If the curvature radii Rf and Rb are selected within the range of 0.100 to 0.150 mm, the straight portion L along the thickness direction at the central portion of the substrate thickness is set to about 0.120 to 0.160 mm. Can do. On the other hand, similarly, when the diameter D = 100 mm, the thickness t = 0.450 mm, and the curvature radii Rf and Rb of the edge round are conventionally set to, for example, 0.250 mm, the substrate thickness t is as shown in FIG. The outermost edge corresponding to the center of the lens has a convex shape with a sharp tip. Thus, the board | substrate which has the periphery of the cross-sectional shape where the front-end | tip sharpened increases the danger that a crack and a chip | tip will generate | occur | produce, when the front-end part receives an impact.

  Here, Table 1 shows a comparative evaluation result of the chipping occurrence rate when a double-sided mirror GaAs substrate having a diameter D = 100.0 mm and a nominal thickness t = 450 μm is polished. In the case of Table 1, the cross-sectional shape of the peripheral edge of the substrate is as shown in FIG. 1 (B) and FIG.

  From the results of Table 1, when the curvature radii Rf and Rb of the edge round are set to 0.10 mm as in the present invention, it is clear as compared with the conventional cases where the radii of curvature Rf and Rb are 0.25 mm. It can be seen that the incidence of chipping in the substrate is reduced.

  Next, the backside polishing for thinning the substrate after manufacturing the semiconductor device will be considered. For example, when the back surface is polished up to a thickness of 0.100 mm on the front surface side of the substrate, the substrate periphery at the end of the back surface polishing is extreme as shown in FIG. A knife edge can be avoided. That is, in FIG. 3, after the back surface polishing region BP of the substrate is removed, the bottom surface of the substrate becomes a surface indicated by a broken line. However, in the cross-sectional shape of the conventional typical substrate periphery, as shown in FIG. 4, the substrate periphery at the end of the back surface polishing is remarkably knife-edge shaped, and cracking starts from this knife-edge-shaped portion. The risk of occurrence is higher. That is, also in FIG. 4, after the back surface polishing region BP of the substrate is removed, the bottom surface of the substrate becomes a surface indicated by a broken line.

In the above-described embodiment described with reference to FIG. 1B, the outer peripheral edge corresponding to the central portion of the substrate thickness t is linear along the thickness direction. It may be a convex curve. An example of such a case is shown in FIG. That is, in the example of FIG. 5, the radius of curvature Rf and Rb of the edge round is connected to the curve C in the central portion of the thickness, and the curve C is equal to or greater than the radius of curvature C compared to the edge round. It is preferable that _R ≧ 0.4t (mm).

  Further, in the above-described embodiment described with reference to FIG. 1B, a taper portion having a taper angle θ of 10 ° to 23 ° may be provided, but the taper portion is omitted and the radius of curvature Rf is omitted. And Rb edge rounds may be directly connected to the front and back surfaces of the substrate. Such an example is shown in FIG.

  Further, in the embodiment of FIG. 6, the outer peripheral edge corresponding to the central portion of the substrate thickness is a straight portion L along the thickness direction. However, as in the case of FIG. Needless to say, it may be. An example of such a case is shown in FIG.

  Further, in the above-described embodiment, the curvature radius Rf of the edge round on the front surface side and the curvature radius Rb of the edge round on the back surface side are made equal, but if desired, the above-described 0.08 (mm) ≦ ( It goes without saying that they may be different from each other within a range satisfying the condition of Rf, Rb) ≦ 0.4 t (mm).

  As described above, according to the present invention, by setting the peripheral portion of the substrate to a specific cross-sectional shape, when manufacturing a semiconductor device, it is possible to reduce the cracking and chipping of the substrate and improve the yield and throughput. It is possible to provide a group III-V compound semiconductor single crystal substrate capable of improving the above.

(A) is a top view of a semiconductor substrate, (B) is an expanded sectional view along the broken line 1B-1B in (A). FIG. 6 is a peripheral cross-sectional view of a substrate having a thickness smaller than that of a conventional standard and having a conventional edge round. It is sectional drawing which suggests the shape of the board | substrate periphery in the state which grinded and removed the back surface side predetermined thickness of the board | substrate by this invention. It is sectional drawing which suggests the shape of the periphery of a board | substrate in the state which grinded and removed the back surface side predetermined thickness of the board | substrate which has thickness smaller than the conventional standard, and has the conventional edge round. In this invention, it is sectional drawing which shows an example of the board | substrate peripheral part changed in part from FIG. 1 (B). In this invention, it is sectional drawing which shows the other example of the board | substrate peripheral part partially changed from FIG.1 (B). In this invention, it is sectional drawing which shows the further another example of the board | substrate peripheral part partially changed from FIG.1 (B).

Explanation of symbols

1 Semiconductor substrate, OF orientation flat, t substrate thickness, radius of curvature of Rf, Rb edge round, θ _f , θ _b taper angle, L linear portion, C curved portion, _CR curved portion C radius of curvature.

Claims (5)

A III-V compound semiconductor single crystal substrate having a diameter D (mm) and a thickness t (mm),
(1/1000) D + 0.2 (mm) ≦ t ≦ (1/1000) D + 0.4 (mm) The radius of curvature of the edge round at the outer edge in the cross section orthogonal to the peripheral edge of the substrate Both Rf (mm) and the radius of curvature Rb (mm) of the edge round of the back outer edge portion are 0.08 (mm) ≦ (Rf, Rb) ≦ 0.4 t (mm)
The III-V compound semiconductor single crystal substrate characterized by satisfying the following relationship:   In the cross section orthogonal to the peripheral edge of the substrate, the outermost edge of the substrate includes a straight portion parallel to the thickness direction, and any of the edge rounds of the front and back outer edge portions having the curvature radii Rf and Rb, respectively. 2. The group III-V compound semiconductor single crystal substrate according to claim 1, wherein the substrate is smoothly connected to the straight line portion of the outermost edge. 3. In the cross section orthogonal to the peripheral edge of the substrate, the outermost edge of the substrate includes a convex curve portion having a radius of curvature C _R ≧ 0.4 t (mm), and the front and back outer edge portions having the curvature radii Rf and Rb, respectively. 2. The group III-V compound semiconductor single crystal substrate according to claim 1, wherein all of the edge rounds are smoothly connected to the curved portion of the outermost edge.   The edge rounds of the front and back outer edge portions having the curvature radii Rf and Rb respectively have a taper having an angle in the range of 10 ° to 23 ° in the direction of decreasing the substrate thickness with respect to the front surface and the back surface of the substrate. The group III-V compound semiconductor single crystal substrate according to any one of claims 1 to 3, wherein the substrate is smoothly connected to a portion.   5. The group III-V compound semiconductor single crystal substrate according to claim 1, wherein the group III-V compound semiconductor is either GaAs or InP.

Images