JP2006201892A - Programmable controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the visual confirmability in sequence program description by reducing the fluctuation of scan time of a sequence program depending on presence of processing. <P>SOLUTION: This programmable controller having a sequence arithmetic processor to execute a sequence instruction comprises a program storage memory storing a processing instruction described in a general language by a user, and a general processor processing the processing instruction in the background of processing of the sequence arithmetic processor. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a programmable controller that executes a sequence instruction, and more particularly to a programmable controller that realizes a reduction in scan time when executing a sequence instruction.

  For example, the following documents exist as prior art for measuring a scan time, which is an execution time of a sequence instruction, in a programmable controller.

JP-A-11-85220

  The technology described above is simply to measure the scan time several times to grasp or analyze the distribution, and there is no idea of actively reducing the scan time, and the scan time distribution status Only got what.

  Hereinafter, execution of a sequence command will be described with reference to the drawings. For example, a case where a sequence as shown in FIG. 5 is realized is assumed. This sequence is an example in which data is transmitted from a programmable controller to a personal computer via a communication line.

  That is, a series of processing is completed from the transmission data set step on the programmable controller side to the data transmission processing and the processing normality / abnormality determination step.

  Here, the “data transmission process” is a process according to a subroutine. Data is transmitted character by character while monitoring the timeout from the step where transmission is possible, and the transmission end-normal end process and abnormal end process are confirmed. Processing is complete.

  If the processing shown in FIG. 5 is described using a ladder language specific to the programmable controller field, the ladder diagram of FIG. 6 is obtained, and the detailed processing operation is as follows.

  When the relay “I00001” is set in step 00001, the transmission process “AAAA” starts. The content of the transmission process “AAAA” is as shown in FIG. 5, but data is obtained using the argument data register “D00001” and the register “D00002” in which return information (error code, etc.) is stored, and relay ( End bit) “I00002” is set.

  In Step 00002, the relay “I00002” set is confirmed, the transfer instruction “MOV” is activated, and the data “D00002” is transferred to the register “D00010” on the personal computer side.

  With the above flow, the sequence instruction data transfer process is executed. FIG. 7 is an actual flowchart that is similar to the ladder diagram shown in FIG.

  In the conventional programmable controller as described above, when the process “AAAA” is described by a sequence instruction, from the start of transmission of data to the end of transmission, every scan of execution of the sequence set in this programmable controller, It is necessary to perform this data transmission process.

  For this reason, the scan time of the entire sequence set in the programmable controller is influenced by whether the data transmission process is being performed or not, and the scan time changes, resulting in a large difference.

  In addition, no matter how fast the communication medium constituting the communication network is, it takes a long time to transmit only one character per scan time in sequence execution.

  Further, since the completion of the process “AAAA” is determined by a circuit different from the circuit that executes the process “AAAA”, the longer the set sequence program, the more the program on the display screen. There was also a problem that visibility deteriorated.

  The present invention has been made to solve the above-described problems, and it is an object of the present invention to reduce the variation in the scan time of the sequence program depending on the presence or absence of processing, and to improve the visibility when describing the sequence program. And

In order to solve such a problem, the configuration of the present invention is as follows.
(1) A programmable controller having a sequence arithmetic processor and executing a sequence instruction, a program storage memory for storing a processing instruction written by a user in a general-purpose language, and a processing background of the sequence arithmetic processor A programmable controller comprising a general-purpose processor for processing in
(2) The programmable controller according to (1), wherein the sequence arithmetic processor issues an activation request to the general-purpose processor when starting the processing instruction.
(3) The programmable controller according to any one of (1) and (2), wherein the general-purpose processor issues an end notification to the sequence arithmetic processor when the processing instruction is ended.
(4) The programmable controller according to any one of (1) to (3), wherein another instruction subsequent to the processing instruction is described in series to create a ladder diagram.
(5) The programmable controller according to any one of (1) to (4), wherein a bit indicating that the processing is completed is set in the processing instruction.

As is apparent from the above description, the present invention has the following effects.
The scan time of the entire sequence set in the programmable controller is not affected by the data transmission process or not, and the scan time does not change greatly.

  Further, by describing instructions to be processed in series, it is possible to improve visibility when describing a sequence program.

Hereinafter, the present invention will be described in detail with reference to the drawings.
FIG. 1 is a block diagram showing an embodiment of the present invention. In this figure, the programmable controller 1 of the present invention includes a CPU unit 11 as a central processing control unit, an input unit 12 for inputting data from the site, an output unit 13 for outputting data to the site, and a system bus B. The communication unit 14 is configured to communicate with a personal computer.

  Further, the CPU unit 11 includes a bus interface 111 connected to the system bus B, a sequence arithmetic processor 112 that reads and executes a sequence instruction from the sequence program storage memory m1, a general-purpose processor firmware storage memory m2, or a general-purpose processor program. The general-purpose processor 113 reads out and executes various system instructions or instructions describing processing contents from the storage memory m3.

  In the present invention, the sequence arithmetic processor 112 issues a process activation request S1 to the general-purpose processor 113 when the user starts the process described in the general-purpose language, and the general-purpose processor 113 Then, an end notification S2 is issued to the sequence arithmetic processor 112.

  FIG. 2 is a ladder diagram showing a description of sequence instructions executed by the programmable controller of the present invention.

  In this figure, when the relay “I01001” is set in step 00004, the process “BBBB” starts.

  In the process “BBBB”, data is obtained using the argument data register “D010001” and the register “D010002” in which return information (error code, etc.) is stored, and the relay (end bit) “I01002” is set.

  Thereafter, immediately after that, the transfer instruction “MOV” is activated to transfer the data “D010002” to the register “D01010” on the personal computer side.

  The feature of this processing is that the processing instruction “BBBB” can be any general-purpose programming language as long as the conventional processing instruction “AAAA” is described by a combination of sequence instructions. The desired contents are described regardless of the description language.

  In the present invention, the process “BBBB” sets the relay (end bit) “I0102” when the process ends, but immediately executes the next transfer instruction “MOV”. .

  Furthermore, when describing such a processing instruction as a ladder diagram, the processing instruction “BBBB” and the transfer instruction “MOV” following this processing instruction “BBBB” are arranged in one column as shown in FIG. Write in series.

  The processing instruction “BBBB” is executed not by the sequence calculation processor 112 but by the general-purpose processor 113 when the activation request S1 is issued. That is, the processing instruction “BBBB” is executed by the general-purpose processor 113 as a background process of the sequence process of the sequence arithmetic processor 112.

  That is, the general-purpose processor 113 is a processor that performs communication processing, input / output refresh processing, and the like, and is usually installed separately from the sequence arithmetic processor 112.

  Then, the instruction “MOV” following the processing instruction “BBBB” is automatically executed only once when the processing instruction “BBBB” is ended as the background processing.

  In this way, this series of processing can be described in one line of the processing command “BBBB” and the transfer command “MOV” that follows, so that the visibility is improved and the flow of processing can be grasped at a glance. it can.

  FIG. 3 is a diagram showing the process flow according to the present invention as described above. When the transmission start is activated, the transmission process “BBBB” starts as the background of the sequence process. On the other hand, normal sequence processing continues as it is.

  That is, when the transmission process “BBBB” is activated, the general-purpose processor 113 executes the process, and the sequence calculation processor 112 executes the sequence process. For this reason, the scan time of the entire sequence program is not affected.

  Returning to FIG. 2, when the processing instruction “BBBB” is completed, the relay bit “I010002” is set. After the processing “BBBB” starts, the transfer instruction “ MOV "is executed.

  On the other hand, the state of setting or resetting of the relay bit “I01002” is referred to in a step necessary for the processing other than the step I0004.

  FIG. 4 is a flowchart showing the contents of the process “BBBB”. As shown in this flowchart, since this program is described in a general language such as C language, there is no concept of “scan” unlike a sequence program, so that the original processing flow can be described as it is.

  In addition, the determination of the conditional branch step is not affected by the scan time, so that transmission processing can be performed at high speed.

It is a block diagram showing the programmable controller of the present invention. It is a figure showing the sequence command used with the programmable controller of this invention. It is a flowchart showing the sequence process used with the programmable controller of this invention. It is a flowchart showing the sequence process used with the programmable controller of this invention. It is a flowchart showing the data transfer process used for a general programmable controller. It is a ladder diagram in the conventional programmable controller. It is a flowchart showing the sequence process used with the conventional programmable controller.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Programmable controller 11 CPU unit 12 Input unit 13 Output unit 14 Communication unit B System bus 111 Bus interface 112 Sequence arithmetic processor 113 General-purpose processor m1 Sequence program storage memory m2 General-purpose processor firmware storage memory m3 General-purpose processor program storage memory

Claims (5)

  A programmable controller having a sequence arithmetic processor and executing a sequence instruction, a program storage memory for storing a processing instruction written by a user in a general-purpose language, and processing the processing instruction in the background of the processing of the sequence arithmetic processor A programmable controller comprising a general-purpose processor.   The programmable controller according to claim 1, wherein the sequence arithmetic processor issues a start request to the general-purpose processor when starting the processing instruction.   3. The programmable controller according to claim 1, wherein the general-purpose processor issues an end notification to the sequence arithmetic processor when the processing instruction is ended.   4. The programmable controller according to claim 1, wherein a ladder diagram is created by serially describing other instructions following the processing instruction. The programmable controller according to any one of claims 1 to 4, wherein a bit indicating that the processing is completed is set in the processing instruction.

Images