JP2006186118A - Solid-state imaging element, manufacturing method thereof, and imaging device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging element capable of largely reducing a gap level in a photoelectric conversion region, and improving an after-image or dark current caused by the gap level while keeping sensitivity improved by enlargement of an aperture ratio of a pixel, and to provide its manufacturing method and an imaging device. <P>SOLUTION: A laminate solid-state imaging element including a photoelectric conversion layer 20 laminated on an element chip is characterized in that the layer 20 is formed of single crystal silicon. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a solid-state imaging device, a method for manufacturing a solid-state imaging device, and an imaging apparatus, and more particularly to a stacked solid-state imaging device, a manufacturing method thereof, and an imaging apparatus using the stacked solid-state imaging device as an imaging device.

  Here, the imaging apparatus includes a solid-state imaging device as an imaging device, an optical system that forms image light of a subject on an imaging surface (light-receiving surface) of the solid-state imaging device, and a signal processing circuit of the solid-state imaging device. A camera module or a camera system equipped with the camera module is referred to.

  As a solid-state image sensor, a CCD (Charge Coupled Device) or MOS (Metal Oxide Semiconductor) is used only for the signal transfer path or switch to greatly increase the aperture ratio of the pixel (sensor unit) and improve sensitivity. There is a stacked solid-state imaging device in which a readout circuit portion is formed and a photoelectric conversion film is formed on the signal readout circuit portion to form a photoelectric conversion portion (see, for example, Patent Document 1).

  FIG. 8 is a cross-sectional view showing an example of a conventional stacked solid-state imaging device, for example, a solid-state imaging device having a PSID (Photoconductive Layered Solid-State Imaging Device) structure.

In FIG. 8, on the surface layer portion of a P-type silicon substrate 101, a charge storage portion 102 made up of N layers (actually N + and N ++ layers), a CCD buried channel portion 103 made up of N layers, and a channel stop layer made up of P + layers. 104 is formed, and a transfer electrode 105 is formed on the CCD buried channel portion 103. A part of the transfer electrode 105 is
It extends to above the charge storage portion 102 and also serves as a signal charge readout electrode.

  An interlayer insulating film 106 such as SiO 2 is formed on these, and a pixel electrode 107 such as tungsten silicide (WSi) electrically connected to the charge storage portion 102 is formed thereon. An insulating film 108 such as BPSG is formed on the entire surface, and after flattening, a lower electrode 109 made of titanium or the like connected to the pixel electrode is formed. A photoelectric conversion layer 110 is further formed of amorphous silicon on the top, and a transparent electrode 111 such as ITO is formed thereon.

Japanese Patent Publication No. 1-034509

  In the above-described prior art, since the photoelectric conversion layer 110 is formed of amorphous silicon, high-density localized levels (gap levels) in the amorphous silicon cause deterioration in image quality. The gap level acts as a carrier trap level in a state where free carriers are increased by external factors such as light. When the external factor is removed, the trapped carriers act as conduction carriers by thermal excitation. That is, when the current relaxation time constant has a large value with respect to an external factor, the image quality of the solid-state imaging device becomes a problem as an afterimage or a problem as a dark current component.

The present invention has been made in view of the above problems, and its object is to significantly reduce the gap level in the photoelectric conversion region and maintain the sensitivity improvement by increasing the aperture ratio of the pixel. It is another object of the present invention to provide a solid-state imaging device, a method for manufacturing the solid-state imaging device, and an imaging apparatus that can improve afterimages and dark current caused by gap levels.

  In order to achieve the above object, in the present invention, a charge accumulation portion is formed on a semiconductor substrate, and a pixel electrode electrically connected to the charge accumulation portion is formed on an upper layer portion of the charge accumulation portion. In a stacked solid-state imaging device including an element chip, a photoelectric conversion layer formed on the element chip, and a transparent electrode formed on the photoelectric conversion layer, the photoelectric conversion layer is formed of single crystal silicon Is adopted.

  In the stacked solid-state imaging device having the above configuration, since there is no defect in the single crystal silicon forming the photoelectric conversion layer, the gap level in the photoelectric conversion region is greatly reduced. As a result, it is possible to improve afterimages and dark current due to the gap level while maintaining the sensitivity improvement by increasing the aperture ratio of the pixel.

  According to the present invention, in the stacked solid-state imaging device, since the photoelectric conversion layer is formed of single crystal silicon, the gap level in the photoelectric conversion region can be greatly reduced. It is possible to improve afterimage and dark current due to the position.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[First Embodiment]
FIG. 1 is a cross-sectional view showing a configuration of a multilayer solid-state imaging device according to the first embodiment of the present invention. In FIG. 1, on a surface layer portion of a first conductivity type, for example, P type silicon substrate 11, a charge storage portion 12 made of an N layer, a CCD buried channel portion 13 made of an N layer, a channel stop made of a P + layer (element isolation). A layer 14 is formed, and a transfer electrode 15 made of polysilicon (Poly-Si) is formed on the CCD buried channel portion 13. A part of the transfer electrode 15 extends above the charge storage unit 12 and also serves as a signal charge readout electrode.

  An interlayer insulating film 16 such as SiO 2 is formed thereon, and a pixel electrode 17 such as tungsten silicide (WSi) or tungsten (W) connected to the charge storage portion 12 is formed thereon. Then, after an insulating film 18 such as BPSG or HDP-CVD is formed on the entire surface and flattened, a lower electrode 19 made of tungsten or the like electrically connected to the pixel electrode 17 is formed. Thus, an element (solid-state imaging element) chip is formed.

  Further, a photoelectric conversion layer 20 is formed with a desired thickness of single crystal silicon on the element chip. The photoelectric conversion layer 20 is preferably crystallized by laser annealing after deposition of amorphous silicon, for example, so that each pixel (sensor unit) is preferably partitioned by an insulating film (separation region) 22. It is formed by single crystallization by laser annealing. The insulating film 22 is made of at least a material having a melting point higher than that of silicon and having an electrical insulating property, such as SiN. A transparent electrode 21 such as ITO is formed on the photoelectric conversion layer 20.

  Here, the case where the insulating film 22 that forms the partition between the pixels is formed of SiN is taken as an example, but SiN has no problem in insulation, but the optical light shielding property is not sufficient. A substance having high light shielding properties (high reflectance and low transmittance) is preferable. It is also possible to form the insulating film 22 with a stacked structure of a plurality of films.

  As described above, in the stacked solid-state imaging device in which the photoelectric conversion layer 20 is stacked on the element chip, the photoelectric conversion layer 20 is formed of single crystal silicon so that there is no defect in the single crystal silicon. As a result, the gap level in the photoelectric conversion region can be greatly reduced, so that it is possible to improve afterimages and dark current due to the gap level while maintaining the improvement in sensitivity due to the increase in the aperture ratio of the pixel associated with the stacked structure. it can.

  In particular, by performing laser annealing on amorphous silicon to form a single crystal to form the photoelectric conversion layer 20, electron traps due to gap levels in the amorphous silicon can be improved. When laser annealing is performed, it is technically difficult to make a single crystal over a wide area without a seed crystal by laser annealing, but instead of making all the pixels in a chip or wafer into the same single crystal. At least the photoelectric conversion region in one pixel is made of single crystal silicon, not polycrystalline silicon or amorphous silicon.

  In order to make the photoelectric conversion region in one pixel into single crystal silicon, laser annealing is performed after forming the insulating film 22 which is a partition for separating pixels. This insulating film 22 also prevents optical color mixing between pixels. As described above, the insulating film 22 is preferably a substance having a higher melting point than silicon, insulating properties, and optically high light-shielding properties (high reflectance and low transmittance).

  Here, when amorphous silicon is crystallized by laser annealing, the effectiveness of annealing after dividing each pixel by an isolation region such as the insulating film 22 will be described with reference to FIG.

  When amorphous silicon is converted into a single crystal by laser annealing, it is difficult to make a wide region such as all pixel regions in a chip or a wafer into the same single crystal without a seed crystal, as shown in FIG. As shown in the figure, it is highly likely that the material is polycrystalline silicon and many grains, twins, crystal defects, etc. remain (however, the present invention is applied to a wide area such as a whole pixel area in a chip or a wafer in the same single crystal. It is not a denial of the method of

  On the other hand, by partitioning amorphous silicon for each pixel with an insulating film 22 or the like and then annealing the amorphous silicon in units of pixels, one single crystallized region is as narrow as about 1 to 5 μm square. The crystallinity of the single crystal silicon is improved, and one single crystal can be easily formed in the pixel as shown in FIG. However, one single crystal is formed in one pixel, but the crystal orientation is not necessarily the same as that of an adjacent pixel.

[Production method]
Next, the manufacturing method of the multilayer solid-state imaging device according to the first embodiment will be described with reference to the process diagrams of FIGS. 3, 4, and 5. 3 to 5, the same parts as those in FIG. 1 are denoted by the same reference numerals.

  In FIG. 3, after forming the insulating film 16 on the surface layer portion of the P-type silicon substrate 11, the charge storage portion 12 made of the N layer, the CCD buried channel portion 13 made of the N layer, and the channel stop 14 layer made of the P + layer are lithographed. This is partially formed by the ion implantation method using the resist and the resist 31 (step 1).

  Next, a transfer electrode 15 made of polysilicon for reading and transferring signal charges is partially formed using a polyetch resist 32 (step 2). Next, it is covered with an interlayer insulating film 16 such as SiO2, and a pixel electrode 17 such as tungsten silicide (WSi) or tungsten (W) is formed thereon and electrically connected to the charge storage portion 12 (step 3). .

  Next, in FIG. 4, an insulating film 18 such as BPSG or HDP-CVD is formed on the entire surface for planarization (if necessary, planarization is performed by etchback or CMP), and a lower portion made of tungsten or the like. An electrode 19 is formed and electrically connected to the pixel electrode 17 (step 4). Here, the lower electrode 19 is an example of planarization by etch back or CMP.

  Next, amorphous silicon 33 is deposited on the upper portion of the lower electrode 19 by a CVD method (step 5). Next, a trench is formed in the isolation region between the pixels by a dry etching method, and an insulating film 22 made of SiN or the like is formed in the trench by a CVD method (step 6). The groove at this time is formed by etching up to the lower electrode 19 in order to electrically isolate the lower electrode 19 by the insulating film 22 for each pixel.

  In forming the insulating film 22, by forming the film thickness t as thin as possible, the light receiving area of the pixel can be widened as much as the film thickness can be reduced, so that the sensitivity can be further improved. In addition, the insulating film 22 is not limited to a single layer structure, and as described above, the insulating film 22 may have a laminated structure of a plurality of films (for example, SiN and W).

  Next, in FIG. 5, SiN forming the insulating film 22 is planarized by etch back, CMP, or the like to expose the amorphous silicon layer 33 entirely, and then the amorphous silicon separated for each pixel by the insulating film 22. The layer 33 is single-crystallized by laser annealing (step 7).

  Here, when the single crystal is formed by the laser annealing method, as an example, as the laser, a gas laser such as an excimer laser that oscillates light having a wavelength of 400 nm or less, or a solid laser such as a YAG laser is used. The laser light may be either pulsed laser light, continuous wave laser light, or continuous light laser light, and the kind thereof is not limited. Further, the beam diameter is about 0.1 to several mm, and it is desirable to appropriately select and use an energy condition that provides a silicon melting point or more from a scanning speed range of 1 to 100 mm / sec according to the silicon film thickness.

  After forming the photoelectric conversion layer 20 by single crystallization by laser annealing, a transparent electrode 21 such as ITO is formed on the photoelectric conversion layer 20 (step 8). As described above, a series of processes for manufacturing the multilayer solid-state imaging device according to the first embodiment is completed.

  In some cases, an on-chip color filter is formed on the upper portion (not necessarily directly above) of the photoelectric conversion layer 20 or an on-chip lens is formed on the upper portion for colorization.

[Second Embodiment]
FIG. 6 is a cross-sectional view showing the configuration of the stacked solid-state imaging device according to the second embodiment of the present invention. In FIG. 6, the same parts as those in FIG.

  In the multilayer solid-state imaging device according to the present embodiment, the structure of the element (solid-state imaging device) chip up to the lower electrode 19 is the same as the structure of the element chip of the multilayer solid-state imaging device according to the first embodiment. The structure has carrier blocking films (for example, SiC films) 23 and 24 above and below the single crystal silicon photoelectric conversion layer 20 formed by laser annealing.

  For example, when the carrier blocking film 23 is formed of i-type amorphous silicon carbide immediately above the lower electrode 19, the carrier blocking film 23 functions as a layer that blocks carrier (hole) injection from the external electrode.

  Further, when the carrier blocking film 24 is formed of p-type amorphous silicon carbide immediately below the transparent electrode 21, the carrier blocking film 24 acts as a layer that blocks carrier (electron) injection from the external electrode.

  However, since the action of the carrier blocking films 23 and 24 is determined by the magnitude relationship of the band gap between the blocking films 23 and 24 and the photoelectric conversion layer 20, it is necessary to optimize these relations.

  Further, in the present embodiment, the carrier blocking films 23 and 24 are formed on both the upper and lower sides of the photoelectric conversion layer 20, but even when the configuration in which the carrier blocking film 23/24 is formed only on either one side is external. It may be sufficient to prevent carrier (hole / electron) injection from the electrode.

  In each of the above embodiments, the case where the present invention is applied to a CCD solid-state image sensor has been described as an example. However, the present invention is not limited to application to a CCD solid-state image sensor, and other charge transfer type solid-state image sensors may also be CMOS. (Complementary Metal Oxide Semiconductor) type solid-state imaging device (so-called CMOS sensor) and XY address type solid-state imaging device such as an amplification type solid-state imaging device can be similarly applied.

[Application example]
The stacked solid-state imaging device according to each embodiment described above is suitable for use as an imaging device in an imaging apparatus (camera module / camera system) such as a digital still camera or a video camera.

  FIG. 7 is a block diagram showing an example of the configuration of the imaging apparatus according to the present invention. As shown in FIG. 7, the imaging apparatus according to this example includes a lens 41, an imaging device 42, a signal processing circuit 43, a device driving circuit 44, and the like.

  The lens 41 forms image light from the subject on the imaging surface of the imaging device 42. The imaging device 42 outputs an image signal of one frame obtained by converting the image light imaged on the imaging surface by the lens 41 into an electrical signal in units of pixels under the driving of the device driving circuit 44, for example, in units of fields. To do. As the imaging device 42, the stacked solid-state imaging device (for example, a CCD solid-state imaging device) according to each of the above-described embodiments is used.

  The signal processing unit 43 includes a CDS (Correlated Double Sampling) circuit and an AGC (Automatic Gain Control) circuit. An image signal output from the imaging device 42 is imaged by the CDS circuit. The fixed pattern noise included in the signal is removed, and the AGC circuit stabilizes the signal level (gain adjustment).

  The device drive circuit 44 is photoelectrically converted by the photoelectric conversion layer 20 and stored in the charge storage unit 12 because the image pickup device 42 is the stacked solid-state image pickup device shown in FIG. Various timing pulses such as a read gate pulse for reading the signal charge to the CCD embedded channel section 13 and a vertical transfer pulse applied to the transfer electrode 15 to transfer and drive the CCD embedded channel section 13 are generated, and imaging is performed using these timing pulses. The device 42 is driven.

  As described above, in an imaging apparatus such as a digital still camera or a video camera, the stacked solid-state image sensor according to each of the embodiments described above is mounted as the imaging device. With this feature, it is possible to improve afterimages and dark current due to gap levels while maintaining sensitivity improvement by increasing the aperture ratio of the pixels, so that it is possible to obtain high-quality captured images with less afterimages and dark currents. it can.

It is sectional drawing which shows the structural example of the multilayer solid-state image sensor which concerns on 1st Embodiment of this invention. It is explanatory drawing of the effectiveness about annealing after dividing | segmenting into a separation area | region for every pixel. It is process drawing (the 1) which shows the procedure of the manufacturing method of the lamination type solid-state image sensor concerning a 1st embodiment. It is process drawing (the 2) which shows the procedure of the manufacturing method of the laminated | stacked solid-state image sensor which concerns on 1st Embodiment. It is process drawing (the 3) which shows the procedure of the manufacturing method of the multilayer solid-state image sensor which concerns on 1st Embodiment. It is sectional drawing which shows the structural example of the multilayer solid-state image sensor which concerns on 1st Embodiment of this invention. It is a block diagram which shows an example of a structure of the imaging device which concerns on this invention. It is sectional drawing which shows the structure of the laminated | stacked solid-state image sensor which concerns on a prior art example.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... Silicon substrate, 12 ... Charge storage part 12, 13 ... CCD embedded channel part, 14 ... Channel stop layer, 15 ... Transfer electrode, 16 ... Interlayer insulating film, 17 ... Pixel electrode, 18 ... Insulating film, 19 ... Lower electrode 20 ... photoelectric conversion layer, 21 ... transparent electrode, 22 ... insulating film, 23,24 ... carrier blocking film

Claims (14)

An element chip in which a charge storage portion is formed on a semiconductor substrate, and a pixel electrode electrically connected to the charge storage portion is formed on an upper layer portion of the charge storage portion;
A photoelectric conversion layer formed of single crystal silicon on the element chip;
A solid-state imaging device comprising: a transparent electrode formed on the photoelectric conversion layer. The solid-state imaging device according to claim 1, wherein the photoelectric conversion layer is single-crystallized by laser annealing after depositing amorphous silicon. The solid-state imaging device according to claim 2, wherein the photoelectric conversion layer has a separation region for each pixel and is single-crystallized for each pixel by laser annealing after depositing amorphous silicon. The solid-state imaging device according to claim 3, wherein the isolation region is made of a substance having a melting point higher than that of silicon and having an electrical insulating property. The solid-state imaging device according to claim 4, wherein the separation region is further made of a material that is optically highly light-shielding. The solid-state imaging device according to claim 1, wherein the photoelectric conversion layer has a carrier injection blocking layer on one side or both sides of the layer. An element chip having a charge accumulation portion formed on a semiconductor substrate and a pixel electrode electrically connected to the charge accumulation portion formed on an upper layer portion of the charge accumulation portion; and formed on the element chip A method for producing a solid-state imaging device comprising a photoelectric conversion layer and a transparent electrode formed on the photoelectric conversion layer,
The photoelectric conversion layer is formed of single crystal silicon. A method for manufacturing a solid-state imaging device, wherein: The method for manufacturing a solid-state imaging element according to claim 7, wherein after depositing amorphous silicon on the element chip, the amorphous silicon is single-crystallized by laser annealing to form the photoelectric conversion layer. The amorphous silicon is deposited on the element chip, the amorphous silicon is partitioned for each pixel, and then the amorphous silicon is single-crystallized for each pixel by laser annealing to form the photoelectric conversion layer. Item 9. A method for manufacturing a solid-state imaging device according to Item 8. The method for manufacturing a solid-state imaging device according to claim 7, wherein a carrier injection blocking layer is formed on one side or both sides of the layer of the photoelectric conversion layer. An element chip in which a charge accumulation portion is formed on a semiconductor substrate and a pixel electrode electrically connected to the charge accumulation portion is formed in an upper layer portion of the charge accumulation portion; and monocrystalline silicon on the element chip An image pickup apparatus comprising: a solid-state image pickup device including a photoelectric conversion layer formed as described above and a transparent electrode formed on the photoelectric conversion layer as an image pickup device. The imaging device according to claim 11, wherein the photoelectric conversion layer is single-crystallized by laser annealing after depositing amorphous silicon. The imaging device according to claim 12, wherein the photoelectric conversion layer has a separation region for each pixel, and is amorphousized for each pixel by laser annealing after depositing amorphous silicon. The imaging device according to claim 11, wherein the photoelectric conversion layer has a carrier injection blocking layer on one side or both sides of the layer.

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