JP2006179948A - Semiconductor device and method of manufacturing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve an insulation breakdown tolerance between wires, whose main conductive film is copper. <P>SOLUTION: Among a plurality of wiring layers N1 to Nx, in the wiring formation process of the wiring layer N1, which is relatively close to the principal plane of a wafer, a level difference is formed between the upper surface of an embedded wiring Ln and that of an insulation layer 12b. Among a plurality of wiring layers N1 to Nx, in the wiring formation process of the wiring layer Nx which is relatively distant from the principal plane of a wafer, without going through the process to form the level difference, the insulation film 15b is deposited with the upper surface of the main conductive film 18a almost matching that of the insulation film 12b. Since a time dependent dielectric breakdown (TDDB) lifetime is thereby enhanced and constraints on the process are fulfilled, a high reliable semiconductor device is provided on the whole. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device technology, and more particularly to a method for manufacturing a semiconductor device having an embedded wiring including a main conductor film containing copper as a main component, and a technology effective when applied to the semiconductor device. It is.

  The embedded wiring structure has Damascene technology (Single-Damascene technology and Dual-Damascene technology) in the wiring openings such as wiring grooves and holes formed in the insulating film. It is formed by embedding a wiring material by a so-called wiring forming technique. However, when the main wiring material is copper, copper is more easily diffused into the insulating film than a metal such as aluminum, so that the embedded wiring made of copper is not in direct contact with the insulating film. By covering the surface (bottom surface and side surface) of the embedded wiring with a thin barrier metal film, diffusion of copper in the embedded wiring into the insulating film is suppressed or prevented. Further, a wiring cap insulating film made of, for example, a silicon nitride film is formed on the upper surface of the insulating film in which the wiring opening is formed to cover the upper surface of the embedded wiring, so that the copper in the embedded wiring is covered. Is suppressed or prevented from diffusing from the upper surface of the buried wiring into the insulating film.

As the damascene wiring technique, for example, Japanese Patent Laid-Open No. 2000-323479 (see Patent Document 1) discloses an embedded wiring structure in which the upper surface of the copper wiring is shifted from the upper surface of the insulating film. Further, for example, Japanese Patent Application Laid-Open No. 11-111443 (see Patent Document 2) discloses an embedded wiring structure in which the upper surface of the copper layer in the embedded wiring is formed lower than the upper surface of the insulating film and the barrier insulating film is embedded therein. ing. Further, for example, in Japanese Patent Laid-Open No. 10-50632 (see Patent Document 3), the upper surface of the copper layer and the barrier metal in the embedded wiring is formed lower than the upper surface of the insulating film, and the embedded wiring in which the barrier insulating film is embedded therein A structure is disclosed. Further, for example, in Japanese Patent Laid-Open No. 2000-277612 (see Patent Document 4), the upper surface of the barrier metal and the metal film of the buried wiring is formed higher than the upper surface of the insulating film, so that the CMP (Chemical Mechanical Polishing) slurry remains. A technique for preventing the above is disclosed. Further, for example, Japanese Patent Laid-Open No. 10-189602 (see Patent Document 5) discloses a technique in which the upper surface of a tungsten plug is formed slightly higher than the upper surface of an insulating film and the embedded plug is rounded.
JP 2000-323479 A JP 11-1111843 A Japanese Patent Laid-Open No. 10-50632 JP 2000-277612 A JP-A-10-189602

  However, according to the examination results of the present inventors, it has been found that the embedded wiring technology using the copper as the main conductor layer has the following problems.

  That is, when copper is used as a wiring material, the TDDB (Time Dependence on Dielectric Breakdown) life is significantly shorter than other metal materials (for example, aluminum or tungsten). Furthermore, in addition to the trend toward finer wiring pitches and increased effective electric field strength, in recent years, insulating materials having a dielectric constant lower than that of silicon oxide have been used for insulating films between wirings from the viewpoint of reducing wiring capacity. However, since an insulating film having a low dielectric constant generally has a low withstand voltage, it is increasingly difficult to ensure the TDDB life.

  The objective of this invention is providing the technique which can improve the dielectric breakdown tolerance between the wiring which uses copper as a main conductor film.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  That is, according to the present invention, the main conductor film constituting the wiring is formed of copper, and the portion where the electric field concentrates in the main conductor film is formed so as to be away from the polishing surface of the surrounding insulating film.

  Further, according to the present invention, the main conductor film constituting the wiring is formed of copper, and a roundness is formed at a location where the electric field concentrates in the main conductor film.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  That is, the main conductor film constituting the wiring is formed of copper, and the portion where the electric field concentrates in the main conductor film is formed so as to be away from the polishing surface of the surrounding insulating film, so that the copper is separated from the main conductor film. It is possible to improve the dielectric breakdown resistance between the wirings to be performed.

  Before describing the present invention in detail, the meaning of terms in the present embodiment will be described as follows.

  1. TDDB (Time Dependence on Dielectric Breakdown) lifetime is a measure for objectively measuring the time dependency of dielectric breakdown, and a relatively high voltage is applied between electrodes under measurement conditions of a predetermined temperature (eg, 140 ° C.). In addition, a graph in which the time from voltage application to dielectric breakdown is plotted against the applied electric field is created, and the time (life) obtained by extrapolating from this graph to the actual electric field strength used (for example, 0.2 MV / cm) Say.

1 to 3 show an example of a sample used for TDDB lifetime measurement of the present application, FIG. 1 is a plan view, and FIGS. 2 and 3 are cross sections taken along line BB ′ and CC ′ in FIG. 1. Respectively. This sample is actually formed in a TEG (Test Equipment Group) region of the wafer. As shown in the figure, a pair of comb-shaped wirings L is formed in the second wiring layer M2 and connected to the uppermost pads P1 and P2. An electric field is applied between the comb-shaped wires L, and a current is measured. Pads P1 and P2 are measurement terminals. The wiring width, the wiring interval, and the wiring thickness of the comb-shaped wiring L are all 0.5 μm. Also, the wiring facing length was 1.58 × 10 ⁵ μm.

FIG. 4 is an explanatory diagram showing an outline of the measurement. The sample is held on the measurement stage S, and a current / voltage measuring device (I / V measuring device) is connected between the pads P1 and P2. The measurement stage S is heated by the heater H, and the sample temperature is adjusted to 140 ° C. The TDDB lifetime measurement includes a constant voltage stress method and a low current stress method. In this application, the constant voltage stress method is used in which the average electric field applied to the insulating film is constant. After voltage application, the current density decreases with the passage of time, and then a rapid current increase (dielectric breakdown) is observed. Here, the time when the leakage current density reached 1 μA / cm ² was defined as the TDDB life (TDDB life at 5 MV / cm). In the present application, the TDDB lifetime refers to a breakdown time (life) at 0.2 MV / cm unless otherwise specified. In a broad sense, the term “TDDB lifetime” refers to a predetermined electric field strength and the time until breakdown. May be used. Unless otherwise specified, the TDDB lifetime refers to the case where the sample temperature is 140 ° C. In addition, the TDDB life refers to the case where the measurement is performed with the comb-shaped wiring L, but it goes without saying that the breakdown life between the actual wirings is reflected.

  2. Plasma treatment means that the surface of a substrate, or when a member such as an insulating film or metal film is formed on the substrate, is exposed to the environment in a plasma state, and the chemical and mechanical properties of the plasma are exposed. (Bombardment) This refers to processing by applying an action to the surface. In general, plasma is generated by ionizing a gas by the action of a high-frequency electric field while replenishing the processing gas as needed in a reaction chamber substituted with a specific gas (processing gas). It cannot be replaced. Therefore, in this embodiment, for example, ammonia plasma is not intended to be complete ammonia plasma, and the presence of impurity gases (nitrogen, oxygen, carbon dioxide, water vapor, etc.) contained in the plasma is excluded. Not what you want. Similarly, it goes without saying that the inclusion of other dilution gas or additive gas in the plasma is not excluded.

3. Plasma in a reducing atmosphere (reducing plasma) refers to a plasma environment in which reactive species such as radicals, ions, atoms, and molecules that have a reducing action, that is, an action of extracting oxygen, exist predominantly. Includes atomic or molecular radicals or ions. In addition, the environment may contain not only a single reactive species but also a plurality of reactive species. For example, an environment in which hydrogen radicals and NH ₃ radicals exist simultaneously may be used.

  4). In this embodiment, for example, when expressed as copper, it is intended that copper is used as a main component. That is, even if it is generally high-purity copper, it is natural that impurities are included, and it does not exclude that additives and impurities are also included in a member made of copper. This applies not only to copper but also to other metals (such as titanium nitride).

  5. Chemical mechanical polishing (CMP) means that the surface to be polished is generally brought into contact with a polishing pad made of a relatively soft cloth-like sheet material, etc., and is moved relative to the surface while supplying slurry. In this embodiment, in addition, CML (Chemical Mechanical Lapping) for polishing by moving the surface to be polished relative to the hard grindstone surface, and other fixed abrasive grains are used. And abrasive-free CMP that does not use abrasive grains.

  6). Abrasive-free chemical mechanical polishing generally refers to chemical mechanical polishing using a slurry having an abrasive weight concentration of less than 0.5% by weight. Abrasive chemical mechanical polishing refers to an abrasive weight concentration of 0.5%. Chemical mechanical polishing using a slurry with a concentration higher than% weight. However, these are relative, and when the polishing in the first step is abrasive-free chemical mechanical polishing and the subsequent polishing in the second step is abrasive chemical mechanical polishing, the polishing concentration in the first step is If the polishing concentration in the second step is one digit or more, preferably two digits or less, the first step polishing may be referred to as abrasive-free chemical mechanical polishing. In this specification, the term “abrasive-free chemical mechanical polishing” refers to the case where the entire unit flattening process of the target metal film is performed by abrasive-free chemical mechanical polishing, and the main process is abrasive-free chemical mechanical polishing. This includes the case where the secondary process is carried out by abrasive chemical mechanical polishing.

  7). The polishing liquid (slurry) generally refers to a suspension in which abrasive grains are mixed with a chemical etching agent. In the present application, a slurry in which abrasive grains are not mixed is included in the nature of the invention.

  8). An anticorrosive agent is an agent that prevents or suppresses the progress of polishing by CMP by forming a protective film having corrosion resistance and / or hydrophobic properties on the surface of a metal. Generally, benzotriazole (BTA), etc. (For details, refer to Japanese Patent Laid-Open No. 8-64594).

  9. Scratch-free means a state in which a defect having a predetermined dimension or more is not detected within the entire polished surface of a wafer polished by the CMP method or within a predetermined unit area. Since this predetermined dimension varies depending on the generation and type of the semiconductor device, it cannot be generally specified. However, in this embodiment, in the in-line comparative defect inspection, for example, 0.3 μm in the polishing surface of a wafer having a diameter of 200 mm, for example. The above defects are not detected.

  10. The conductive barrier film is a conductive film having a diffusion barrier property that is relatively thinly formed on the side surface or bottom surface of the embedded wiring in order to prevent copper from diffusing into the interlayer insulating film or the lower layer. Generally, a refractory metal such as titanium (Ti) or tantalum (Ta) or a refractory metal nitride such as titanium nitride (TiN) or tantalum nitride (TaN) is used.

  11. A buried wiring or a buried metal wiring is generally conductive inside a wiring opening such as a groove or a hole formed in an insulating film, such as a single damascene or a dual damascene. A wiring that is patterned by a wiring formation technique for removing an unnecessary conductive film on an insulating film after the film is embedded. In general, single damascene refers to an embedded wiring process in which plug metal and wiring metal are embedded in two stages. Similarly, dual damascene generally refers to an embedded wiring process in which plug metal and wiring metal are embedded at once. In general, copper embedded wiring is often used in a multilayer configuration.

  12 In this application, the term “semiconductor device” refers to manufacturing of SOI (Silicon On Insulator) substrates and TFT (Thin Film Transistor) liquid crystals, not only those manufactured on a single crystal silicon substrate, but unless otherwise specified. Including those made on other substrates such as industrial substrates.

  13. A wafer is a silicon or other semiconductor single crystal substrate (generally disk-shaped, semiconductor wafer), a sapphire substrate, a glass substrate, other insulating, anti-insulating, or semiconductor substrates used in the manufacture of semiconductor integrated circuits, and their composites. Say the board.

  14 A semiconductor integrated circuit chip or a semiconductor chip (hereinafter simply referred to as a chip) refers to a wafer obtained by completing a wafer process (wafer process or previous process) and divided into unit circuit groups.

15. The term “silicon nitride, silicon nitride, or silicon nitride film” includes not only Si ₃ N ₄ but also an insulating film having a similar composition of silicon nitride.

  16. Examples of the low dielectric constant insulating film (Low-K insulating film) include an insulating film having a dielectric constant lower than that of a silicon oxide film (eg, TEOS (Tetraethoxysilane) oxide film) included in the passivation film. Generally, the dielectric constant ε = 4.1 to 4.2 or less of the TEOS oxide film is called an insulating film having a low dielectric constant.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say.

  Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Also, components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted.

  In the drawings used in the present embodiment, hatching may be added even in a plan view for easy understanding of the drawings.

  In the present embodiment, a MIS • FET (Metal Insulator Semiconductor Field Effect Transistor) representing a field effect transistor is abbreviated as MIS, a p-channel type MIS • FET is abbreviated as pMIS, and an n-channel type MIS • FET. Is abbreviated as nMIS.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
In the present embodiment, for example, when the technical idea of the present invention is applied to a manufacturing method of CMIS (Complementary MIS) -LSI (Large Scale Integrated circuit), the manufacturing flow diagram of FIG. Will be described. In addition, the process enclosed with the broken line of FIG. 5 has illustrated the process in the same process chamber.

  First, FIG. 6 is a plan view of an essential part in the manufacturing process of the CMIS-LSI, and FIG. A semiconductor substrate (hereinafter simply referred to as a substrate) 1S constituting the wafer 1W is made of p-type single crystal silicon having a specific resistance of, for example, about 1 to 10 Ωcm. A groove-shaped isolation part (SGI (Shallow Groove Isolation) or STI (Shallow Trench Isolation)) 2 is formed on the main surface (device forming surface) of the substrate 1S. For example, a silicon oxide film is embedded in the groove formed in the main surface of the substrate 1S. A p-type well PWL and an n-type well NWL are formed on the main surface side of the substrate 1S. For example, boron is introduced into the p-type well PWL, and phosphorus is introduced into the n-type well NWL, for example. In the active regions of the p-type well PWL and the n-type well NWL surrounded by the isolation part 2, nMISQn and pMISQp are formed, respectively.

The gate insulating film 3 of nMISQn and pMISQp is made of, for example, a silicon oxide film having a thickness of about 6 nm. The film thickness of the gate insulating film 3 here is a silicon dioxide equivalent film thickness and may not match the actual film thickness. The gate insulating film 3 may be composed of a silicon oxynitride film instead of the silicon oxide film. That is, a structure in which nitrogen is segregated at the interface between the gate insulating film 3 and the substrate 1S may be employed. The silicon oxynitride film can improve the hot carrier resistance of the gate insulating film 3 and can improve the insulation resistance. In addition, since the silicon oxynitride film is less likely to penetrate impurities than the silicon oxide film, the use of the silicon oxynitride film causes a threshold value due to diffusion of impurities in the gate electrode material to the substrate 1S side. Voltage fluctuation can be suppressed. In order to form the silicon oxynitride film, for example, the substrate 1S may be heat-treated in a nitrogen-containing gas atmosphere such as NO, NO ₂ or NH ₃ .

The gate electrodes 4 of nMISQn and pMISQp are formed, for example, by laminating, for example, a titanium silicide (TiSi _x ) layer or a cobalt silicide (CoSi _x ) layer on a low-resistance polycrystalline silicon film. However, the gate electrode structure is not limited to this. For example, a so-called polymetal gate structure including a laminated film of a low-resistance polycrystalline silicon film, a WN (tungsten nitride) film, and a W (tungsten) film. Also good. A side wall 5 made of, for example, silicon oxide is formed on the side surface of the gate electrode 4.

semiconductor region 6 for the source and drain of nMISQn is, n adjacent channels ^- -type semiconductor region, n ^- is connected to the semiconductor region, and, n ^- provided in a position away from the semiconductor region amount corresponding channel and an n ⁺ type semiconductor region. For example, phosphorus or arsenic is introduced into the n ⁻ type semiconductor region and the n ⁺ type semiconductor region. On the other hand, the semiconductor regions 7 for the source and drain of pMISQp is, p is adjacent to the channel ^- -type semiconductor region, p ^- is connected to the semiconductor region, and, p ^- provided in a position away from the semiconductor region amount corresponding channel P ⁺ -type semiconductor region. For example, boron is introduced into the p ⁻ type semiconductor region and the p ⁺ type semiconductor region. A silicide layer such as a titanium silicide layer or the cobalt silicide layer is formed on part of the upper surface of the semiconductor regions 6 and 7.

  An insulating film 8 is deposited on the substrate 1S. The insulating film 8 is made of a highly reflowable film capable of filling a narrow space between the gate electrodes 4 and 4, for example, a BPSG (Boron-doped Phospho Silicate Glass) film. Moreover, you may comprise by the SOG (SpinOn Glass) film | membrane formed by a spin coating method. A contact hole 9 is formed in the insulating film 8. A part of the upper surface (silicide layer surface) of the semiconductor regions 6 and 7 is exposed from the bottom of the contact hole 9. A plug 10 is formed in the contact hole 9. For example, the plug 10 is formed by depositing a titanium nitride (TiN) film and a tungsten (W) film on the insulating film 8 including the inside of the contact hole 9 by a CVD method or the like, and then forming an unnecessary titanium nitride film and tungsten on the insulating film 8. The film is formed by removing the film by a CMP method or an etch back method, and leaving these films only in the contact holes 9.

  On the insulating film 8, a first layer wiring L1 made of, for example, tungsten is formed. The first layer wiring L1 is electrically connected to the source / drain semiconductor regions 6 and 7 and the gate electrode 4 of the nMISQn and pMISQp through the plug 10. The first layer wiring L1 is not limited to tungsten and can be variously changed. For example, a single film such as aluminum (Al) or an aluminum alloy, or titanium (Ti) or titanium nitride (at least one of upper and lower layers of these single films) is used. A laminated metal film in which a metal film such as TiN) is formed may be used.

  On the insulating film 8, an insulating film 11a is deposited so as to cover the first layer wiring L1. The insulating film 11a is made of a low dielectric constant material (so-called Low-K insulating film, Low-K material) such as organic polymer or organic silica glass. Examples of the organic polymer include SiLK (manufactured by The Dow Chemical Co., USA, relative dielectric constant = 2.7, heat-resistant temperature = 490 ° C. or higher, dielectric breakdown voltage = 4.0-5.0 MV / Vm) or polyallyl ether ( There is FLARE (PAE) based material (manufactured by Honeywell Electronic Materials, relative permittivity = 2.8, heat-resistant temperature = 400 ° C. or more). This PAE material is characterized by high basic performance and excellent mechanical strength, thermal stability and low cost. Examples of the organic silica glass (SiOC-based material) include HSG-R7 (manufactured by Hitachi Chemical Co., Ltd., relative dielectric constant = 2.8, heat-resistant temperature = 650 ° C.), Black Diamond (manufactured by Applied Materials, Inc., relative dielectric constant). = 3.0-2.4, heat-resistant temperature = 450 ° C.) or p-MTES (manufactured by Hitachi Development Co., Ltd., relative permittivity = 3.2). Other SiOC materials include, for example, CORAL (manufactured by Novellus Systems, Inc., relative permittivity = 2.7 to 2.4, heat-resistant temperature = 500 ° C.), Aurora 2.7 (manufactured by Japan ASM Co., Ltd.) , Relative dielectric constant = 2.7, heat-resistant temperature = 450 ° C.).

Examples of the low dielectric constant material of the insulating film 11a include FSG (SiOF-based material), HSQ (hydrogen silsesquioxane) -based material, MSQ (methyl silsesquioxane) -based material, porous HSQ-based material, porous MSQ material, or porous organic-based material. Can also be used. Examples of the HSQ-based material include OCD T-12 (manufactured by Tokyo Ohka Kogyo Co., Ltd., dielectric constant = 3.4 to 2.9, heat-resistant temperature = 450 ° C.), FOx (manufactured by Dow Corning Corp., USA), dielectric constant = 2.9) or OCL T-32 (manufactured by Tokyo Ohka Kogyo Co., Ltd., relative permittivity = 2.5, heat-resistant temperature = 450 ° C.). Examples of the MSQ material include OCD T-9 (manufactured by Tokyo Ohka Kogyo Co., Ltd., relative dielectric constant = 2.7, heat-resistant temperature = 600 ° C.), LKD-T200 (manufactured by JSR, relative dielectric constant = 2.7-2. 5, heat-resistant temperature = 450 ° C., HOSP (manufactured by Honeywell Electronic Materials, relative dielectric constant = 2.5, heat-resistant temperature = 550 ° C.), HSG-RZ25 (manufactured by Hitachi Chemical, relative dielectric constant = 2.5, heat-resistant Temperature = 650 ° C.), OCL T-31 (manufactured by Tokyo Ohka Kogyo Co., Ltd., dielectric constant = 2.3, heat-resistant temperature = 500 ° C.) or LKD-T400 (manufactured by JSR, dielectric constant = 2.2-2, heat-resistant temperature) = 450 ° C.). Examples of the porous HSQ material include XLK (manufactured by Dow Corning Corp., relative dielectric constant = 2.5-2), OCL T-72 (manufactured by Tokyo Ohka Kogyo Co., Ltd., relative dielectric constant = 2.2-1.9). , Heat resistant temperature = 450 ° C), Nanoglass (manufactured by Honeywell Electronic Materials, relative dielectric constant = 2.2 to 1.8, heat resistant temperature = 500 ° C or higher) or MesoELK (US Air Products and Chemicals, Inc, relative dielectric constant = 2) There are following). Examples of the porous MSQ material include HSG-6221X (manufactured by Hitachi Chemical Co., Ltd., relative dielectric constant = 2.4, heat-resistant temperature = 650 ° C.), ALCAP-S (manufactured by Asahi Kasei Kogyo Co., Ltd., relative dielectric constant = 2.3-1). .8, heat resistant temperature = 450 ° C.), OCL T-77 (manufactured by Tokyo Ohka Kogyo Co., Ltd., relative dielectric constant = 2.2 to 1.9, heat resistant temperature = 600 ° C.), HSG-6210X (manufactured by Hitachi Chemical Co., Ltd., dielectric constant) Rate = 2.1, heat-resistant temperature = 650 ° C.) or silica aerogel (manufactured by Kobe Steel, relative dielectric constant: 1.4 to 1.1). Examples of the porous organic material include PolyELK (US Air Products and Chemicals, Inc., dielectric constant = 2 or less, heat-resistant temperature = 490 ° C.). The SiOC material and the SiOF material are formed by, for example, a CVD method (Chemical Vapor Deposition). For example, the Black Diamond is formed by a CVD method using a mixed gas of trimethylsilane and oxygen. The p-MTES is formed by, for example, a CVD method using a mixed gas of methyltriethoxysilane and N ₂ O. The other low dielectric constant insulating materials are formed by, for example, a coating method.

An insulating film 12a for a Low-K cap is deposited on the insulating film 11a made of such a Low-K material. The insulating film 12a is made of, for example, a silicon oxide (SiO _x ) film typified by silicon dioxide (SiO ₂ ), and secures the mechanical strength of the insulating film 11a during, for example, chemical mechanical polishing (CMP). It has functions such as surface protection and ensuring moisture resistance. The thickness of the insulating film 12a is relatively thinner than the insulating film 11a, and is, for example, about 25 nm to 100 nm, and preferably, for example, about 50 nm. However, the insulating film 12a is not limited to the silicon oxide film and can be variously changed. For example, a silicon nitride (Si _x N _y ) film, a silicon carbide (SiC) film, or a silicon carbonitride (SiCN) film is used. May be. These silicon nitride film, silicon carbide film, or silicon carbonitride film can be formed by, for example, a plasma CVD method. As a silicon carbide film formed by the plasma CVD method, for example, there is BLOk (manufactured by AMAT, relative permittivity = 4.3). In the formation, for example, a mixed gas of trimethylsilane and helium (or N ₂ , NH ₃ ) is used. In the insulating films 11a and 12a, a through hole 13 exposing a part of the first layer wiring L1 is formed. A plug 14 made of tungsten or the like is embedded in the through hole 13.

First, in the present embodiment, the insulating film 15a is deposited on the insulating film 12a and the plug 14 by a plasma CVD method or the like. The insulating film 15a is made of, for example, a silicon nitride film formed by plasma CVD, and has a thickness of, for example, about 25 nm to 50 nm, preferably about 50 nm. As another material of the insulating film 15a, for example, a silicon carbide film formed by plasma CVD, a SiCN film formed by plasma CVD, or a silicon oxynitride (SiON) film formed by plasma CVD is used. May be. When these films are used, the dielectric constant can be significantly reduced as compared with the silicon nitride film, so that the wiring capacitance can be reduced and the operation speed of the semiconductor device can be improved. An example of the silicon carbide film formed by the plasma CVD method is BLOk (manufactured by AMAT). The film forming gas is as described above. In forming the SiCN film, for example, a mixed gas of helium (He), ammonia (NH ₃ ), and trimethylsilane (3MS) is used. Moreover, as a silicon oxynitride film formed by the plasma CVD method, for example, PE-TMS (manufactured by Canon, dielectric constant = 3.9) is available. The film thickness in the case of using the silicon oxynitride film is, for example, about 25 nm to 50 nm, preferably, for example, about 50 nm. In forming the film, for example, trimethoxysilane (TMS) gas and nitrogen oxide (N ₂ O) are used. A gas mixture with gas is used.

  Subsequently, insulating films (first insulating films) 11b and 12b are sequentially deposited from the lower layer on the insulating film 15a. The insulating film 11b is made of the same low dielectric constant insulating film as the insulating film 11a. The upper insulating film 12b is made of the same insulating film as the insulating film 12a and functions as an insulating film for the same Low-K cap. Thereafter, the insulating films 11b and 12b are selectively removed by a dry etching method using the photoresist film as a mask to form a wiring groove (wiring opening) 16a (step 100 in FIG. 5). In order to form the wiring trench 16a, when the insulating films 11b and 12b exposed from the photoresist film are removed, the etching selectivity ratio between the insulating films 11b and 12b and the insulating film 15a is increased, whereby the insulating film 15a is formed. To function as an etching stopper. That is, after the etching is temporarily stopped on the surface of the insulating film 15a, the insulating film 15a is selectively removed by etching. Thereby, the formation depth precision of the wiring groove | channel 16a can be improved, and the excessive dug of the wiring groove | channel 16a can be prevented. Such a wiring groove 16a is formed in a band shape, for example, as shown in FIG. The upper surface of the plug 14 is exposed from the bottom surface of the wiring groove 16a.

  Next, FIG. 8 shows a cross-sectional view of a portion corresponding to line X1-X1 in FIG. 6 during the manufacturing process of the semiconductor device following FIG. 7, and FIG. 9 shows the semiconductor device during the manufacturing process following FIG. Sectional drawing of the part corresponded to the X1-X1 line | wire of FIG. 6 is shown.

  First, as shown in FIG. 8, a thin conductive barrier film (first conductor film) 17a made of titanium nitride (TiN) or the like and having a thickness of about 50 nm is formed on the entire main surface of the substrate 1S by sputtering or the like. Deposit (Step 101 in FIG. 5). The conductive barrier film 17a has, for example, a function of preventing diffusion of copper for forming a main conductor film, which will be described later, a function of improving adhesion between the main conductor film and the insulating films 11b, 12a, 12b, and 15a, and a main conductor. It has a function of improving the wettability of copper when the film is reflowed. As such a conductive barrier film 17a, it is preferable to use a refractory metal nitride such as tungsten nitride (WN) or tantalum nitride (TaN), which hardly reacts with copper, instead of the titanium nitride. Further, instead of the titanium nitride, a material obtained by adding silicon (Si) to a refractory metal nitride, tantalum (Ta), titanium (Ti), tungsten (W), titanium tungsten (TiW) which does not easily react with copper. A refractory metal such as an alloy can also be used. Further, according to the first embodiment, good TDDB characteristics can be obtained even when the thickness of the conductive barrier film 17a is, for example, 10 nm, which is 6 to 7 nm or 5 nm or less.

  Subsequently, a main conductor film (second conductor film) 18a made of relatively thick copper having a thickness of, for example, about 800 to 1600 nm is deposited on the conductive barrier film 17a (step 101 in FIG. 5). In the first embodiment, the main conductor film 18a is formed by, for example, a plating method. By using the plating method, the main conductor film 18a having good film quality can be formed with good embeddability and at low cost. In this case, first, a thin conductor film made of copper is deposited on the conductive barrier film 17a by a sputtering method, and then a relatively thick conductor film made of copper is deposited thereon by, for example, an electrolytic plating method or an electroless plating. The main conductor film 18a was deposited by growing by the method. In this plating process, for example, a plating solution based on copper sulfate was used. However, the main conductor film 18a can also be formed by a sputtering method. As a sputtering method for forming the conductive barrier film 17a and the main conductor film 18a, a normal sputtering method may be used. However, in order to improve embedding property and film quality, for example, a long throw sputtering method, a collimated sputtering method, or the like. It is preferable to use a sputtering method with high directivity as described above. Also, the main conductor film 18a can be formed by a CVD method. Thereafter, the main conductor film 18a is reflowed by heat-treating the substrate 1S in a non-oxidizing atmosphere (for example, hydrogen atmosphere) of about 475 ° C., for example, and copper is embedded in the wiring groove 16a without a gap.

  Next, the main conductor film 18a and the conductive barrier film 17a are polished by CMP (step 102 in FIG. 5). For this CMP process, a general abrasive grain CMP process may be employed. However, in the first embodiment, for example, the above-described abrasive-free CMP (first step) and abrasive grain CMP (second step). The two-step CMP method is employed. That is, for example, as follows.

First, the first step is intended to selectively polish the main conductor film 18a made of copper. The polishing liquid (slurry) contains an anticorrosive agent for forming a protective film, a copper oxidizing agent, and a component for etching the copper oxide film, but does not contain abrasive grains. The content of abrasive grains in the polishing liquid is preferably, for example, 0.5% by weight or less or 0.1% by weight or less, and more preferably 0.05% by weight or less or 0.01% by weight or less. However, about 3 to 4% of abrasive grains may be included. As the polishing liquid, a liquid whose pH is adjusted so as to belong to a copper corrosion area is used, and the polishing selectivity of the main conductor film 18a to the conductive barrier film 17a is, for example, at least 5 or more. The one whose composition is adjusted is used. As such a polishing liquid, a slurry containing an oxidizing agent and an organic acid can be exemplified. Examples of the oxidizing agent include hydrogen peroxide (H ₂ O ₂ ), ammonium hydroxide, ammonium nitrate, and ammonium chloride. Examples of the organic acid include citric acid, malonic acid, fumaric acid, malic acid, and adipic acid. Examples thereof include benzoic acid, phthalic acid, tartaric acid, lactic acid, succinic acid, and oxalic acid. Of these, hydrogen peroxide does not contain a metal component and is not a strong acid, and therefore is a suitable oxidizing agent for use in the polishing liquid. Citric acid is also generally used as a food additive, has low toxicity, low waste damage, no odor, and high solubility in water, so it is a suitable organic acid for use in polishing liquids. . In this embodiment, for example, a polishing liquid in which 5% by volume of hydrogen peroxide and 0.03% by weight of citric acid are added to pure water so that the content of abrasive grains is less than 0.01% by weight is used. For example, BTA is used as the corrosion inhibitor.

  In this first-step abrasive-free CMP, the main conductor film 18a is polished mainly by chemical elements while producing both the protective action and the etching action of the main conductor film 18a. That is, when chemical mechanical polishing is performed with the above polishing liquid, the copper surface is first oxidized by an oxidizing agent, and a thin oxide layer is formed on the surface. Next, when a substance for water-solubilizing the oxide is supplied, the oxide layer is eluted as an aqueous solution, and the thickness of the oxide layer is reduced. The thinned portion of the oxide layer is again exposed to the oxidizing substance to increase the thickness of the oxide layer, and this reaction is repeated to advance chemical mechanical polishing. The protective film is removed mainly by contact with the polishing pad. The chemical mechanical polishing using the abrasive-free polishing liquid as described above is described in detail in Japanese Patent Application Nos. 9-299937 and 10-317233 by the present inventors.

The subsequent second step is intended to selectively polish the conductive barrier film 17a. In this second step, the conductive barrier film 17a is polished mainly by mechanical elements by contact with the polishing pad. Here, abrasive grains are contained as a polishing liquid in addition to the anticorrosive, the oxidant, and the component for etching the oxide film. In the first embodiment, as the polishing liquid, for example, pure water mixed with 5% by volume of hydrogen peroxide, 0.03% by weight of citric acid and 0.5 to 0.8% by weight of abrasive grains is used. However, the present invention is not limited to this. The amount of the abrasive grains is set so that the underlying insulating film 12b is not etched, and the amount is, for example, 1% by weight or less. For example, colloidal silica (SiO ₂ ) is used as the abrasive grains. By using this colloidal silica, damage to the polished surface of the insulating film 12b due to CMP treatment can be greatly reduced, and scratch-free can be realized. However, alumina (Al ₂ O ₃ ) can also be used for the abrasive grains instead of colloidal silica. In the second step, the amount of the oxidant is reduced from the amount of the oxidant in the first step. That is, the amount of the corrosion inhibitor in the polishing liquid is relatively increased. Then, the polishing is performed under the condition that the polishing selection ratio of the main conductor film 18a to the conductive barrier film 17a is lower than that of the abrasive-free chemical mechanical polishing, for example, the selection ratio is 3 or less. By polishing under such conditions, in the second step, since the protection can be enhanced while suppressing the oxidation of the copper-based main conductor film 18a, the main conductor film 18a can be prevented from being excessively polished, and dishing, erosion, etc. can be performed. Can be suppressed or prevented. For this reason, an increase in wiring resistance and variations can be suppressed or prevented, so that the performance of the semiconductor device can be improved.

  By the CMP process as described above, the buried second layer wiring (wiring) L2 is formed in the wiring groove 16a as shown in FIG. The buried second layer wiring L2 has a relatively thin conductive barrier film 17a and a relatively thick main conductor film 18a, and is electrically connected to the first layer wiring L1 through the plug. Yes. According to the first embodiment, in the polishing process for forming the buried second layer wiring L2, the CMP method as described above is employed, so that the polishing surface of the insulating film 12b is significantly damaged by the CMP process. The scratch-free polishing is possible. In the above example, the insulating film 12b for the insulating cap is provided on the insulating film 11b of the Low-K material. However, since the scratch-free polishing is possible according to the CMP method of the first embodiment, the insulating cap is used. The insulating film (for example, the insulating film 12b) may not be provided. That is, the insulating film 11b can be exposed on the CMP surface. The Low-K barrierless technology is disclosed in Japanese Patent Application No. 2001-316557 (application date; October 15, 2001) including the inventors of the present application.

  The surface of the substrate 1S after the polishing treatment is subjected to a corrosion prevention treatment. This anticorrosion processing unit has a configuration similar to the configuration of the polishing processing unit. Here, the main surface of the substrate 1S is first pressed against the polishing pad attached to the surface of the polishing board (platen), and the polishing slurry is machined. After the removal, the chemical solution containing an anticorrosion agent such as benzotriazole (BTA) is supplied to the main surface of the substrate 1S, so that the surface of the copper wiring formed on the main surface of the substrate 1S becomes hydrophobic. A protective film is formed. The substrate 1S after the anticorrosion treatment is temporarily stored in the immersion treatment section in order to prevent the surface from drying. The immersion treatment unit is for maintaining the surface of the substrate 1S after the anticorrosion treatment so that it does not dry until post-cleaning. For example, a predetermined number of pieces are placed in an immersion tank (stocker) overflowed with pure water. The substrate 1S is immersed and stored. At this time, by supplying pure water cooled to such a low temperature that the electrochemical corrosion reaction of the embedded second layer wiring L2 does not substantially proceed to the immersion bath, the embedded second layer wiring L2 is further corroded. This can be prevented more reliably. As long as at least the surface of the substrate 1S can be kept in a wet state, such as supply of pure water shower, prevention of drying of the substrate 1S may be performed by a method other than the above storage in the immersion bath. This immersion processing part (substrate storage part) can be made to have a light-shielding structure so that the surface of the substrate 1S being stored is not irradiated with illumination light or the like. Thereby, generation | occurrence | production of the short circuit current by a photovoltaic effect can be prevented. The CMP process and apparatus as described above are described in, for example, Japanese Patent Application No. 11-226876 and Japanese Patent Application No. 2000-300853 by the present inventor.

  Thereafter, the process immediately proceeds to the post-CMP cleaning process while the surface of the substrate 1S is kept wet. First, an alkali cleaning process is performed on the substrate 1S. This treatment has the purpose of removing foreign matters such as slurry during the CMP treatment, neutralizes the acidic slurry adhering to the substrate 1S by the CMP treatment, and the substrate 1S, the foreign matter, and the cleaning brush. In order to align the zeta potential and eliminate the adsorption force between them, the surface of the substrate 1S is scrubbed (or brushed) while supplying a weak alkaline chemical solution of about 8 or more ph (pH), for example. To do.

10 is a cross-sectional view of a portion corresponding to the X1-X1 line in FIG. 6 during the manufacturing process of the semiconductor device subsequent to FIG. Here, first, reduction processing is performed on the substrate 1S (particularly, the CMP polished surface from which the embedded second layer wiring L2 is exposed). That is, the substrate 1S (particularly the CMP polished surface) is subjected to heat treatment, for example, in a hydrogen gas atmosphere, for example, 200 to 475 ° C., preferably 300 ° C., for example, 0.5 to 5 minutes, preferably about 2 minutes. (Hydrogen (H ₂ ) annealing treatment, step 103 in FIG. 5). Thereby, the copper oxide film on the surface of the buried second layer wiring L2 generated during CMP can be reduced to copper, and the etching of the buried second layer wiring L2 by the subsequent acid cleaning can be suppressed or prevented. For this reason, it is possible to simultaneously suppress or prevent the increase in wiring resistance, the variation in wiring resistance and the generation of steps, and further suppress or prevent the occurrence of etch corrosion. Further, when the reduction process is not performed, an organic substance such as BTA attached to the surface of the substrate 1S during the CMP process may become a mask during the cleaning process, and the surface layer of the insulating film 12b may not be satisfactorily scraped. By performing the reduction treatment as in the first embodiment, organic substances such as BTA adhering at the time of CMP can be removed, so that the surface layer of the insulating film 12b can be sufficiently and uniformly removed. As a result, the TDDB life of the semiconductor device can be significantly improved. This hydrogen annealing method is particularly suitable when a copper-based main conductor film for buried wiring is formed by a plating method. By performing the hydrogen annealing treatment in this manner, copper formed by the plating method can be recrystallized, so that the wiring resistance can be lowered. Further, by performing the hydrogen annealing treatment, it is possible to suppress or prevent the cap film from being peeled off due to thermal stress. However, depending on the case, the above-described hydrogen annealing may not be performed. Further, this hydrogen annealing treatment may be performed, for example, after a post-CMP cleaning process (including an acid cleaning and drying process described later) and before a reducing plasma process described later.

  Subsequently, an acid cleaning process is performed on the substrate 1S. This treatment has the purposes of improving TDDB characteristics, removing residual metal, reducing dangling bonds on the surface of the insulating film 12b, and removing irregularities on the surface of the insulating film 12b, and supplying a hydrofluoric acid aqueous solution to the surface of the substrate 1S. Then, foreign particles (particles) are removed by etching. TDDB characteristics can be improved by simply inserting hydrofluoric acid cleaning. This is presumably because the damaged layer on the surface was removed by the acid treatment and the adhesion at the interface was improved. Thereafter, a drying process such as a spin dryer is performed on the substrate 1S, and the process proceeds to the next step.

  In the above example, the case has been described in which the alkali cleaning treatment is performed, the reduction treatment is performed, and the acid cleaning is further performed. According to this, the TDDB characteristics can be improved by about two orders of magnitude compared with the TDDB characteristics of the continuous sequence of alkali cleaning and acid cleaning. However, the sequence is not limited to this, and can be variously changed. For example, after the CMP process, the reduction process may be performed, and then the post-cleaning process may be performed in the order of an alkali cleaning process and an acid cleaning process. Further, a sequence of CMP treatment, reduction treatment, and acid cleaning treatment may be used. Even if only the acid cleaning is performed, the TDDB characteristics are improved. Prior to or in parallel with the post-CMP cleaning process, the surface of the substrate 1S is cleaned with pure water scrub, pure water ultrasonic cleaning, pure water running water cleaning or pure water spin cleaning, and the back surface of the substrate 1S is cleaned with pure water scrub. It may be washed. The actions and effects of the above-described cleaning treatment method, hydrogen annealing treatment method, and the sequence of these treatments will be described in detail, for example, in Japanese Patent Application No. 2001-131941 (filing date; April 27, 2001) by the present inventor. Has been.

  Next, the wafer 1W after the drying process is carried into a plasma CVD apparatus for forming an insulating film for a wiring cap. The plasma CVD apparatus is not particularly limited. For example, a parallel plate type plasma CVD apparatus is used.

Here, in the first embodiment, first, for example, nitrogen gas (N ₂ ) is introduced into the processing chamber of the plasma CVD apparatus, and the wafer 1W is held and subjected to heat treatment. That is, the main surface (CMP surface) of the wafer 1W is annealed in a nitrogen gas flow atmosphere. As a result, a roundness is formed in the upper surface (CMP surface, first surface) of the main conductor film 18a of the embedded second layer wiring L2, particularly the contact portion (upper corner) with the conductive barrier film 17a (step of FIG. 5). 104). 11 is a cross-sectional view of a portion corresponding to the X1-X1 line of FIG. 6 during the manufacturing process of the semiconductor device after such processing, and FIG. 12 is an enlarged cross-sectional view of a main part of FIG. According to the first embodiment, the upper corner on the CMP surface side of the main conductor film 18a in the embedded second layer wiring L2 is chamfered to form a round taper. That is, the upper portion of the main conductor film 18a on the CMP surface side has a cross-sectional shape that gradually separates from the conductive barrier film 17a as it goes upward in FIGS. The size of the round taper at the upper corner of the main conductor film 18a is defined (especially by the normal slope) from the width and height of the wiring groove 16a. The width of the round taper (the width in the direction horizontal to the upper surface of the main conductor film 18a) is larger than the thickness of the gate insulating film 3.

  In such a heat treatment in a nitrogen gas atmosphere, the temperature of the susceptor on which the wafer 1W is placed (that is, substantially the temperature of the wafer 1W) is, for example, about 360 ° C. to 400 ° C. The heat treatment time is, for example, about 1 minute. The roundness of the main conductor film 18a can be easily formed by increasing the pressure during the heat treatment. Although hydrogen gas can be selected as the processing gas, a favorable round taper can be formed in a relatively low temperature range by selecting nitrogen gas. As shown in FIG. 12, a taper is formed on the side surface of the embedded second layer wiring L2 so that the wiring width gradually increases from the bottom to the top. The angle α formed between the side surface of the buried second layer wiring L2 and the upper surface of the insulating film 11a is, for example, in the range of 80 ° to 90 °, specifically about 88.7 °, for example. The width of the upper side of the buried second layer wiring L2 (the upper side width of the wiring groove 16a) and the interval between the upper sides of the buried second layer wiring L2 adjacent to each other (of the buried second layer wiring L2 buried adjacent to each other) The distance between the upper corners) is, for example, 0.25 μm or less, or 0.2 μm or less. Further, the minimum adjacent pitch of the embedded second layer wirings L2 adjacent to each other is, for example, 0.5 μm or less. The aspect ratio of the wiring trench 16a is 1, for example.

  Subsequently, after exhausting nitrogen gas from the processing chamber of the plasma CVD apparatus and turning off the plasma power source, the following reducing plasma processing is performed on the wafer 1W (step 105 in FIG. 5). 13 and 14 are cross-sectional views of a portion corresponding to the X1-X1 line of FIG. 5 of the wafer 1W during the reducing plasma process.

Here, first, hydrogen gas is introduced into the processing chamber of the plasma CVD apparatus, and then a plasma power source is applied. As a result, as shown in FIG. 13, the substrate 1S (especially, the embedded second layer wiring L2 is exposed) Surface) is subjected to hydrogen plasma treatment. For example, when the diameter of the substrate 1S is 8 inches (about 200 mm), the processing pressure is 5.0 Torr (= 6.6661 × 10 ² Pa), the radio frequency (RF) power is 600 W, the substrate temperature Was 400 ° C., the hydrogen gas flow rate was 500 cm ³ / min, and the treatment time was 10 to 30 seconds. The distance between the electrodes was 600 mils (15.24 mm). As the processing gas, for example, a single gas of hydrogen (H) or a mixed gas of hydrogen (H) and nitrogen (N) was used.

  By performing such hydrogen plasma treatment, as described in Japanese Patent Application Nos. 11-226876 and 2000-300853 by the present inventors, etc., the organic removal ability is extremely high (ammonia described later). Therefore, BTA contained in the slurry in CMP, slurry components, organic acid cleaned after CMP, and residual organic substances generated during the process are almost completely removed, and leakage current at the interface is reduced. Since it can be reduced, the TDDB life can be further improved.

Subsequently, after exhausting the hydrogen gas in the processing chamber of the plasma CVD apparatus and turning off the plasma power supply, the ammonia gas is continuously flowed into the processing chamber of the plasma CVD apparatus without applying the atmosphere, and the plasma power supply is applied. Thus, ammonia (NH ₃ ) plasma treatment is performed on the substrate 1S (particularly, the CMP surface on which the buried second layer wiring L2 is exposed). For example, when the substrate 1S has a diameter of 8 inches (about 200 mm), the ammonia plasma processing conditions are such that the processing pressure is about 0.5 to 1.0 Torr (= 66.6612 to 133.332 Pa) and the upper part of the plasma processing apparatus. The applied power of the electrode is about 500 to 1000 W, the applied power of the lower electrode of the plasma processing apparatus is about 0 to 1000 W (preferably 0), the substrate temperature is about 300 ° C. to 400 ° C., and the ammonia gas flow rate is 500 to 1500 cm ³ / min. The processing time was about 5 to 60 seconds. The distance between the electrodes was 300 to 600 mils (7.62 to 15.24 mm).

In such ammonia plasma treatment, copper oxide (CuO, CuO ₂ ) on the surface of the copper wiring oxidized by CMP is reduced to copper (Cu). In addition, a copper nitride (CuN) layer that prevents silicidation of copper during the set flow is formed on the surface (very thin region) of the buried second layer wiring L2. On the upper surface (very thin region) of the insulating film 12b between the wirings, SiN or SiH is advanced, so that dangling bonds on the surface of the insulating film 12b are compensated, and a cap insulating film and a buried second layer described later are used. The adhesion between the wiring L2 and the insulating film 12b can be improved, and the leakage current at the interface can be reduced. Thereby, the TDDB life can be improved.

  By sequentially performing such hydrogen plasma treatment and ammonia plasma treatment, reduction of the surface of the buried second layer wiring L2 mainly composed of copper, formation of a silicide-resistant barrier layer, cleaning of the interface of the insulating film 12b, and SiH effect and SiN effect can be obtained, and further improvement in reliability can be realized. In the case where the interlayer insulating film is configured by depositing a silicon nitride film formed by a plasma CVD method on a silicon oxide film formed by a plasma CVD method using, for example, TEOS (Tetraethoxysilane) gas, hydrogen plasma It has been clarified by the present inventor that the TDDB life is improved by about two orders of magnitude in the sample obtained by combining ammonia plasma with ammonia plasma treatment alone. Further, even when SiLK is used as an interlayer insulating film, sufficient reliability is ensured even in an operating environment of about 0.13 to 0.17 MV / cm, for example, when hydrogen plasma and ammonia plasma are used. It was clarified by experiments of the present inventor that this can be done.

Of course, the above-described reducing plasma processing conditions are not limited to these exemplified conditions. It has been clarified by the present inventors that plasma damage can be reduced as the pressure is increased, and that variation in the TDDB lifetime in the substrate is reduced and the lifetime is increased as the substrate temperature is increased. Further, it has been found that the higher the substrate temperature, the higher the RF power, and the longer the processing time, the more hillocks are likely to occur on the copper surface. Considering these knowledge and variations in conditions depending on the apparatus configuration, for example, the processing pressure is 0.5 to 6 Torr (= 0.66661 × 10 ^{2 to} 7.99932 × 10 ² Pa), the RF power is 300 to 600 W, the substrate The temperature is 350 to 450 ° C., the hydrogen gas flow rate is 50 to 1000 cm ³ / min, the ammonia gas flow rate is 20 to 500 cm ³ / min, the treatment time is 5 to 180 seconds, and the distance between the electrodes is 150 to 1000 mils (3.81 to 25). .4 mm).

  In the above example, the case where the ammonia plasma treatment is performed after the hydrogen plasma treatment has been described. However, the present invention is not limited to this, and various modifications are possible. For example, the hydrogen plasma is maintained while the vacuum state is maintained after the ammonia plasma treatment. You may transfer to processing continuously. Moreover, you may perform only an ammonia plasma process as a reduction process. Even in these cases, the TDDB life could be improved.

  Furthermore, in the above example, the case where the reducing plasma treatment is performed after the round taper forming step has been described. This is to ensure the effect of stabilizing the surface of the main conductor film 18a by the reducing plasma treatment, but the round taper can be formed after the reducing plasma treatment. Alternatively, the round taper may be formed after the hydrogen plasma treatment, and then the ammonia plasma treatment may be performed. Or you may form a reducing process and a round taper simultaneously. The susceptor temperature (ie, the temperature of the wafer 1W) when the reducing process and the round taper are simultaneously formed is, for example, about 350 ° C. to 400 ° C., and the processing time is, for example, about 1 to 3 minutes, preferably about 2 minutes. is there.

  Subsequently, after the ammonia gas in the processing chamber of the plasma CVD apparatus is exhausted and the plasma power supply is turned off, an insulating film for a wiring cap is formed on the main surface of the wafer 1W by plasma CVD through a set flow (step 106 in FIG. 5). It deposits by the method etc. (process 107 of FIG. 5). FIG. 15 shows a portion corresponding to the X1-X1 line of FIG. 5 of the wafer 1W after depositing a wiring cap insulating film (second insulating film, which will also be a first insulating film in a later step) 15b. A cross-sectional view is shown. The insulating film 15b is formed with the same material and thickness as the insulating film 15a.

The set flow is also called “stabilization” and is a preparatory stage mainly aimed at improving the stability of the film forming process prior to the formation of the insulating film for the wiring cap. The film forming process is performed through this set flow. That is, first, after flowing the carrier gas into the processing chamber of the plasma CVD apparatus for about several tens of seconds, the processing gas is flowed into the processing chamber with the carrier gas flowing, and the state is maintained for about several seconds (set flow). Then, the plasma power supply is applied to start the film forming process. When the insulating film 15b is formed of a silicon nitride film, for example, nitrogen gas is used as the carrier gas during the set flow, and ammonia gas (NH ₃ ) and silane gas (SiH ₄ ) are used as the processing gas. When the insulating film 15b is formed of a silicon carbide film, for example, helium gas (He) is used as the carrier gas during the set flow, and for example, trimethylsilane gas (3MS) is used as the processing gas. When the insulating film 15b is formed of SiCN, for example, helium gas (He) is used as the carrier gas during the set flow, and ammonia gas (NH ₃ ) and trimethylsilane gas (3MS) are used as the processing gas. When the insulating film 15b is formed of a silicon oxynitride film, trimethoxysilane gas (TMS) and nitrogen oxide (N ₂ O) are used as the processing gas at the time of set flow.

  Next, FIG. 16 is a plan view of an essential part in the manufacturing process of the semiconductor device subsequent to FIG. 15, and FIG. 17 is a sectional view taken along line X2-X2 of FIG. Here, a buried third layer wiring (wiring) L3 is illustrated. An insulating film (first insulating film) 11c is deposited on the insulating film 15b for the wiring cap. The material and formation method of the insulating film 11c are the same as those of the insulating films 11a and 11b made of the Low-K material. An insulating film (first insulating film) 12c is deposited on the insulating film 11c. The material, formation method and function of the insulating film 12c are the same as those of the insulating films 12a and 12b. An insulating film 15c is deposited on the insulating film 12c. The material, forming method and function of the insulating film 15c are the same as those of the insulating films 15a and 15b. An insulating film (first insulating film) 11d is deposited on the insulating film 15c. The material and formation method of the insulating film 11d are the same as those of the insulating films 11a to 11c made of the Low-K material. An insulating film (first insulating film) 12d is deposited on the insulating film 11d. The material, formation method and function of the insulating film 12d are the same as those of the insulating films 12a to 12c. As described above, according to the first embodiment, by forming the insulating films of the plurality of wiring layers with a material having a low dielectric constant as a whole, the overall wiring capacity can be reduced, and the copper-based embedded wiring The operation speed of the semiconductor device having the structure can be improved.

  In the insulating films 15c, 11d, and 12d, a planar belt-like wiring groove (wiring opening) 16b is formed. A conductive barrier film 17b and a main conductor film 18b are embedded in the wiring groove 16b, thereby forming an embedded third layer wiring L3. Further, in the insulating films 15b, 11c, and 12c, a planar substantially circular through hole (wiring opening) 19 extending from the bottom surface of the wiring groove 16b to the top surface of the embedded second layer wiring L2 is formed. The buried third layer wiring L3 is electrically connected to the buried second layer wiring L2 through the conductive barrier film 17b and the main conductor film 18b buried in the through hole 19. The buried third layer wiring L3 is formed by a dual damascene method. That is, after forming the wiring groove 16b in the insulating films 15c, 11d, and 12d and forming the through hole 19 in the insulating films 15b, 11c, and 12c, the conductive barrier film 17b and the main conductor film (second conductor film) 18b are formed. Are deposited in order. That is, the wiring trench 16b and the through hole 19 are simultaneously filled with the conductive barrier film 17b and the main conductor film 18b. The deposition method of the conductive barrier film 17b and the main conductor film 18b is the same as the conductive barrier film 17a and the main conductor film 18a of the buried second layer wiring. The materials of the conductive barrier film 17b and the main conductor film 18b are the same as those of the conductive barrier film 17a and the main conductor film 18a, respectively. Thereafter, the conductive barrier film 17b and the main conductor film 18b are polished by the CMP method in the same manner as the formation of the buried second layer wiring L2, and then subjected to the same process as that of the buried second layer wiring L2. The embedded third layer wiring L3 is formed. A round taper is formed at the upper corner of the buried third layer wiring L3 as well as the buried second layer wiring L2. On the insulating film 12d and the buried third layer wiring L3, a wiring cap insulating film (second insulating film, which also becomes a first insulating film in a later step) 15d is deposited. The insulating film 15d is the same as the insulating films 15a and 15b.

  FIG. 18 shows an enlarged cross-sectional view of the main part of the buried second layer wiring L2 and the buried third layer wiring L3. According to the present embodiment, a round taper is formed at the upper corners of the main conductor films 18a and 18b of the buried second layer wiring L2 and the buried third layer wiring L3. For this reason, the electric field applied to the portion corresponding to the upper corners of the main conductor films 18a and 18b (in the vicinity of the conductive barrier films 17a and 17b) can be relaxed. According to the study of the present inventor, the ratio of the electric field E1 corresponding to the upper corners of the main conductor films 18a and 18b to the electric field E2 of the upper corners of the conductive barrier films 17a and 17b can be 1: 2. That is, the electric field strength at the portion corresponding to the upper corners of the main conductor films 18a and 18b can be made half of the electric field strength at the upper corners of the conductive barrier films 17a and 17b. Further, the main conductor films 18a and 18b made of copper having a high diffusion coefficient can be kept away from the CMP surface (second surface) of the insulating films 12b and 12d where a leak path is easily formed. Therefore, it is possible to suppress or prevent the formation of leak paths between the buried second layer wirings L2 and L2 adjacent to each other and between the buried third layer wirings L3 and L3. Therefore, the TDDB life can be improved.

(Embodiment 2)
FIG. 19 is a flowchart of a manufacturing process of a semiconductor device according to another embodiment of the present invention. In the second embodiment, as shown in FIG. 19, the round taper of the main conductor film of the embedded wiring is performed during the set flow process 106. That is, when the insulating film for the wiring cap is, for example, a silicon nitride film, a silicon carbide film, SiCN, or a silicon oxynitride film, before flowing the processing gas in the set flow as described above, it is necessary to use nitrogen, helium, or the like. The flow from the start of the flow of the carrier gas to the start of the flow of the treatment gas is longer than the normal set flow, and is performed during the introduction period of the carrier gas alone, and the stage temperature is set as described above. The upper temperature of the main conductor films 18a and 18b of the buried wiring is set by performing the same annealing process as described in the round forming process of the first embodiment on the wafer 1W by setting the temperature described in the first embodiment. A round taper is formed at the corner. In this case, since a round taper process is not newly added, simplification of the manufacturing process and reduction of manufacturing time can be promoted. The rest is the same as in the first embodiment.

(Embodiment 3)
In the third embodiment, a case will be described in which the insulating film for the wiring cap is multilayered. For example, when an SiON film such as PE-TMS (manufactured by Canon) is used as an insulating film for a wiring cap, the inventor says that the conductive barrier film is oxidized during the film formation. This is to solve the problem found for the first time. FIG. 20 is a fragmentary cross-sectional view of the semiconductor device according to another embodiment of the present invention during the manufacturing process.

First, after the ammonia plasma treatment, an insulating film (second insulating film) 15b for a wiring cap is continuously formed on the upper surfaces of the buried second layer wiring L2 and the insulating film 12b by the CVD method or the like without opening to the atmosphere. At the time of deposition, in the present third embodiment, the insulating film 15b is deposited so that the exposed portion of the conductive barrier film 17a of the buried second layer wiring L2 is not oxidized. Therefore, first, the oxidation of the conductive barrier film 17a is suppressed or prevented, that is, the oxidation barrier insulating film (third insulating film) 15b1 that protects against oxidation is formed on the insulating film 12b and the buried second layer wiring L2. After being deposited on the substrate, it is not opened to the atmosphere and continuously maintained in a vacuum state, for example, trimethoxysilane (TMS, chemical formula: SiH (OCH ₃ ) ₃ ) gas and nitrogen oxide (N ₂ O) gas. An insulating film (fourth insulating film) 15b2 made of a silicon oxynitride (SiON) film such as PE-TMS (manufactured by Canon, dielectric constant = 3.9) or the like is formed by a plasma CVD method using a mixed gas with accumulate. As a result, the oxidation of the conductive barrier film 17a can be suppressed or prevented during the silicon oxynitride (SiON) film deposition process, so that the copper in the main conductor film 18a diffuses due to the oxidation of the conductive barrier film 17a. Can be suppressed or prevented, and the TDDB life can be improved. Further, by forming most or all of the insulating film 15b for the wiring cap with a material having a dielectric constant lower than that of the silicon nitride film, the wiring capacity can be reduced, so that the operation speed of the semiconductor device can be improved. . Furthermore, since PE-TMS or the like having excellent moisture resistance can be used as the insulating film for the wiring cap of the buried second layer wiring L2, the reliability of the semiconductor device can be improved. A method for forming such an antioxidant film is, for example, as follows.

In the first method, the insulating film 15b1 for the oxidation barrier is an insulating film having a function of suppressing or preventing copper diffusion, such as a silicon nitride (SiC) film, a silicon carbide (SiCN) film, or a silicon carbonitride film. It is a method of forming by a film. The thickness of the insulating film 15b1 for the oxidation barrier in this case is, for example, 1 nm or more, but is formed thinner than the insulating film 15b2 in order to keep the overall dielectric constant of the wiring structure low. The thickness of the insulating film 15b2 is about 50 nm or less, for example. The nitrogen content in the insulating film 15b2 is, for example, about 1 to 8%. The pressure in the processing chamber when forming the insulating film 15b2 is, for example, about 0.5 to 1.0 Torr (= 66.6612 to 133.332 Pa), and the flow rate of the trimethoxysilane gas is, for example, about 100 to 150 cm ³ / min. The gas flow rate of N ₂ O is, for example, about 4000 cm ³ / min or less, and the applied power to the upper electrode and the lower electrode of the plasma CVD apparatus is, for example, about 500 to 1000 W. By using, for example, a silicon carbide film or a silicon carbonitride film as the oxidation barrier insulating film 15b1, the dielectric constant can be reduced and the wiring capacitance can be reduced as compared with the case where the insulating film 15b1 is formed of a silicon nitride film. The operating speed of the semiconductor device can be improved.

In the second method, the insulating film 15b1 for the oxidation barrier is deposited by PE-TMS (Canon) deposited by a plasma CVD method or the like under a gas condition that does not use oxygen, in particular, a condition that does not use highly oxidizing N ₂ O gas. In this method, a silicon oxynitride (SiON) film or the like such as manufactured by, dielectric constant = 3.9) is used. The insulating film 15b1 in this case also has a function of suppressing or preventing copper diffusion.

Examples of gas conditions that do not use oxygen include a mixed gas of trimethoxysilane (TMS) gas and ammonia (NH ₃ ) gas, or a mixed gas of trimethoxysilane (TMS) gas and nitrogen (N ₂ ) gas. Can be illustrated. In this case, the thickness of the oxidation barrier insulating film 15b1 is, for example, about 1 to 10 nm. The thickness of the upper insulating film 15b2 is the same as that described in the first method. The nitrogen content in the insulating films 15b1 and 15b2 is, for example, about 1 to 8%. The pressure in the processing chamber when forming the insulating film 15b1 is, for example, about 0.5 to 1.0 Torr (= 66.6612 to 133.332 Pa), and the flow rate of the trimethoxysilane gas is, for example, about 100 to 150 cm ³ / min. The flow rate of N ₂ O gas is, for example, 0 (zero) cm ³ / min, the flow rate of gas when N ₂ gas is used is, for example, about 4000 cm ³ / min or less, and the flow rate of gas when NH ₃ gas is used. Is, for example, about 1500 cm ³ / min or less, and the power applied to the upper electrode and the lower electrode of the plasma CVD apparatus is the same as in the first method. The film formation conditions for the insulating film 15b2 are the same as those described in the first method. In this second method, both of the insulating films 15b1 and 15b2 can be formed of a silicon oxynitride film having a low dielectric constant, such as PE-TMS, so that the wiring is more than in the case of using the first method. The capacity can be reduced and the operation speed of the semiconductor device can be improved. Further, by forming the entire insulating film 15b (insulating films 15b1 and 15b2) with a silicon oxynitride film such as PE-TMS having excellent moisture resistance, the reliability of the semiconductor device can be improved. .

In the third method, the insulating film 15b1 for the oxidation barrier is used under gas conditions in which, for example, N ₂ / O ₂ having low oxidizability is used in the film forming process, and oxygen (particularly highly oxidizable N ₂ O) is reduced. This is a method of forming with a silicon oxynitride film or the like such as PE-TMS deposited by the plasma CVD method or the like. Also in this case, the insulating film 15b1 has a function of suppressing or preventing copper diffusion. Examples of gas conditions with reduced oxygen include a mixed gas of trimethoxysilane gas, N ₂ gas, and O ₂ gas, a mixed gas of trimethoxysilane gas, NH ₃ gas, and O ₂ gas, trimethoxysilane gas, and NH ₃ gas. Examples thereof include a mixed gas of N ₂ gas and O ₂ gas or a mixed gas of trimethoxysilane gas, N ₂ O gas, and NH ₃ gas. In this case, N ₂ gas or NH ₃ gas has a role as a dilution gas in the mixed gas.

In this case, the thicknesses of the insulating films 15b1 and 15b2 and the nitrogen content are the same as those described in the second method. The pressure in the processing chamber during the formation of the insulating film 15b1 and the power applied to the upper electrode and the lower electrode of the plasma CVD apparatus are the same as described in the first and second methods. For example, when the mixed gas of trimethoxysilane gas, N ₂ gas, and O ₂ gas is used as the film forming process gas, the flow rate of trimethoxysilane gas is, for example, about 75 to 150 cm ³ / min, and the flow rate of N ₂ gas is for example 4000cm ³ / min of about or less, the flow rate of _{O 2} gas, for example, 4000cm or less about ³ / min. Further, when a mixed gas of trimethoxysilane gas, NH ₃ gas and O ₂ gas is used, the flow rate of trimethoxysilane gas is, for example, about 75 to 150 cm ³ / min, and the flow rate of NH ₃ gas is, for example, 1500 cm ³ / min. The flow rate of O ₂ gas is, for example, about 4000 cm ³ / min. When a mixed gas of trimethoxysilane gas, NH ₃ gas, N ₂ gas, and O ₂ gas is used, the flow rate of trimethoxysilane gas is, for example, about 75 to 150 cm ³ / min, and the gas flow rate of NH ₃ is, for example, 1500 cm ^3. For example, the flow rate of N ₂ gas is about 4000 cm ³ / min, and the flow rate of O ₂ gas is about 4000 cm ³ / min, for example. Furthermore, when the mixed gas of trimethoxysilane gas, N ₂ O gas, and NH ₃ gas is used, the flow rate of trimethoxysilane gas is, for example, about 75 to 150 cm ³ / min, and the flow rate of N ₂ O gas is, for example, 4000 cm ^3. For example, the flow rate of NH ₃ gas is about 1500 cm ³ / min. The film formation conditions for the insulating film 15b2 are the same as those in the first and second methods. As an application of the third method, the entire insulating film 15b may be formed by the third method. That is, the insulating film 15b may be formed of a single film of a silicon oxynitride film deposited by a plasma CVD method or the like under a gas condition with reduced oxygen. In this case, since it is possible to eliminate the gas change and the control for it in the film forming process of the insulating film for the wiring cap, the film forming control can be facilitated and the film forming process time can be shortened.

However, in the above description, the case where trimethoxysilane gas is used for the formation of a silicon oxynitride (SiON, nitrogen content of about 1 to 8%) film has been described. However, the present invention is not limited to this and can be variously changed. It is. For example, the insulating film 15b2 of the first method and the insulating films 15b1 and 15b2 of the second method are formed by a gas selected from, for example, monosilane, disilane, or TEOS, ammonia gas, oxygen (or A mixed gas with N ₂ O or ozone (O ₃ ) gas or a mixed gas in which nitrogen is introduced into this mixed gas may be used. Further, a mixed gas of a gas selected from trimethylsilane (3MS) gas or tetramethylsilane (4MS) gas and nitrogen oxide (N ₂ O) gas (or nitrogen oxide gas and ammonia gas (NH ₃ )). Alternatively, a mixed gas obtained by adding a mixed gas of nitrogen (N ₂ ) gas, nitrogen (N ₂ ) gas and oxygen (O ₂ ) gas or a mixed gas of nitrogen gas, oxygen gas and ammonia gas to the mixed gas may be used. . Also in these cases, since oxidation of the exposed portion of the conductive barrier 17a can be suppressed or prevented, copper diffusion can be suppressed or prevented, and the TDDB life can be improved. The problem that the conductive barrier film is oxidized and the means for solving the problem are disclosed in, for example, Japanese Patent Application No. 2001-341339 (filing date: November 7, 2001) by the present inventor.

(Embodiment 4)
In the fourth embodiment, a structure in which the insulating cap insulating film described in the first embodiment is not provided will be described. FIG. 21 is a fragmentary cross-sectional view of the semiconductor device according to another embodiment of the present invention during the manufacturing process. The insulating cap insulating film is not formed on the upper surface of the insulating film 11b made of the Low-K material, and the wiring cap insulating film 15b is directly deposited on the upper surface (CMP surface, second surface) of the insulating film 11b. ing. Also in the fourth embodiment, the insulating film 15b for the wiring cap may have a multilayer structure as in the third embodiment. In the fourth embodiment, in addition to the improvement of the TDDB life, the wiring capacity can be reduced as much as the insulating film for the insulating cap is not provided, and the operation speed of the semiconductor device can be improved.

(Embodiment 5)
In the fifth embodiment, a structure (barrierless embedded wiring structure) in which the conductive barrier film of the embedded wiring is eliminated will be described. FIG. 22 is a fragmentary cross-sectional view of the semiconductor device according to another embodiment of the present invention during the manufacturing process. The main conductor film 18a made of copper is in direct contact with the insulating films 11b, 12a, 12b, and 15a in the wiring groove 16a. Also in the fifth embodiment, the insulating film for the insulating cap may be eliminated as in the fourth embodiment. According to the fifth embodiment as described above, the wiring resistance of the buried second layer wiring L2 can be greatly reduced. Also, since different layer wirings are directly connected without a conductive barrier film, the contact resistance between the different layer wirings can be greatly reduced, and the resistance in fine through-holes can be reduced. it can. Accordingly, the performance of the semiconductor device can be improved even if the wiring trench 16a and the through hole 9 are miniaturized, and therefore the miniaturization of the wiring constituting the semiconductor device can be promoted.

  In the fifth embodiment, a round taper is formed at the upper corner of the main conductor film 18a. Then, the upper corner of the main conductor film 18a made of copper is disposed away from the upper surface (CMP surface, second surface) of the insulating film 12b adjacent thereto. By these, as in the first to fourth embodiments, it is possible to further suppress or prevent the formation of a leak path between the adjacent buried second layer wirings L2 and L2, thereby further improving the TDDB life. It becomes possible. Such a barrierless buried wiring structure is disclosed in, for example, Japanese Patent Application No. 2000-104015, Japanese Patent Application No. 2000-300853 or Japanese Patent Application No. 2001-131941 (application date: April 27, 2001) by the present inventor. It is disclosed.

(Embodiment 6)
In the sixth embodiment, a technique for selectively using the embedded wiring structure as described above for each wiring layer will be described. In a wiring layer of a semiconductor device, in a lower wiring layer close to a fine element formed on a substrate, the interval between adjacent wirings is narrow and tends to become narrower in the future. . Compared to this, in the upper wiring layer that is relatively distant from the element, the interval between adjacent wirings is relatively wide, and there is a certain margin against the deterioration of the TDDB life due to the diffusion of copper. On the other hand, in the manufacturing process of a semiconductor device, there are process restrictions such as an increase in the number of processes, addition of heat treatment, or addition of a process that causes a step.

  Therefore, in the sixth embodiment, the lower wiring layer with a small margin has the embedded wiring structure described in the first embodiment, while the upper wiring layer with a large margin has a normal embedded wiring structure. The structure. FIG. 23 is a fragmentary cross-sectional view schematically showing the semiconductor device of the sixth embodiment. The wiring layer N1 is a lower wiring layer having a relatively small wiring width and wiring interval, such as the first and second wiring layers, and the wiring layer Nx is, for example, the fifth and sixth wiring layers. An upper wiring layer having a relatively large wiring width and wiring interval is shown. Taking the 0.13 μm generation as an example, the wiring width and the wiring interval of the embedded wiring (wiring) Ln when the wiring layer N1 is the first wiring layer is, for example, about 0.18 μm, and the wiring layer Nx is the fifth wiring layer Nx. When the wiring layer is used, the wiring width and the wiring interval of the embedded wiring (wiring) Ln are, for example, about 0.36 μm. Taking the 0.1 μm generation as an example, the wiring width and the wiring interval of the embedded wiring Ln when the wiring layer N1 is the first wiring layer are, for example, about 0.14 μm, and the wiring layer Nx is the fifth wiring. The wiring width and wiring interval of the embedded wiring Ln in the case of the layer is, for example, about 0.28 μm.

  In FIG. 23, the buried wiring Ln of the lower wiring layer N1 has the same structure as that of the first embodiment, that is, a structure in which a round taper is formed at the upper corner of the main conductor film 18a. The buried wiring Ln has a normal structure, that is, the upper corner of the main conductor film 18a is not tapered, and the upper surface (first surface) of the main conductor film 18a is the upper surface (CMP surface, second surface) of the insulating film 12b. ) And almost the same structure. As a result, the TDDB life can be improved and the above-mentioned process restrictions can be satisfied, so that a highly reliable semiconductor device can be provided as a whole.

(Embodiment 7)
In the seventh embodiment, a technique for changing the round taper state of the embedded wiring according to the wiring layer will be described. FIG. 24 is a fragmentary cross-sectional view schematically showing the semiconductor device of the seventh embodiment. In the seventh embodiment, the buried wiring Ln in both the lower wiring layer N1 and the upper wiring layer Nx has the same structure as in the first embodiment, that is, a round taper is formed at the upper corner of the main conductor film 18a. It is said to have a structure. However, here, the depth d1 of the round taper in the main conductor film 18a of the lower buried wiring Ln is deeper than the depth d2 of the round taper of the main conductor film 18a in the upper buried wiring Ln. Is formed. That is, the round taper at the upper corner of the main conductor film 18a in the buried wiring Ln of the lower wiring layer N1 is larger. The reason for this is that, as described in the sixth embodiment, the lower wiring layer N1 has a narrow adjacent wiring interval, and a decrease in the TDDB life due to copper diffusion tends to become obvious, whereas the upper wiring layer has a wide adjacent wiring interval. This is because there is a relative margin. That is, the TDDB life is improved by increasing the round taper of the main conductor film 18a in the buried wiring Ln of the lower wiring layer N1 in which copper diffusion is likely to be a problem, while the upper wiring layer Nx having a margin is improved. The overall reliability of the semiconductor device can be improved by forming the round taper of the main conductor film 18a of the embedded wiring Ln smaller to satisfy the process restrictions.

(Embodiment 8)
In the eighth embodiment, a technique for changing the stepped state of the embedded wiring according to the wiring layer will be described. FIG. 25 is a fragmentary cross-sectional view schematically showing the semiconductor device of the eighth embodiment. In the eighth embodiment, the upper surface (first surface) of the main conductor film 18a of the embedded wiring Ln of the lower wiring layer N1 and the upper wiring layer Nx is the upper surface of the conductive barrier film 17a and the insulating film 12b (first surface). It is lower than the CMP surface and the second surface. As a result, the main conductor film 18a moves away from the CMP surface, and the corner portion of the main conductor film 18a is separated from the electric field concentration portion of the corner portion of the embedded wiring Ln (corner portion of the conductive barrier film 17a). Can be suppressed or prevented, and the TDDB life can be improved.

  A technique for providing a step on the upper surface of the main conductor film 18a of the buried wiring Ln is disclosed in, for example, Japanese Patent Application No. 2001-131941 (filing date; April 27, 2001) by the present inventor. However, in the eighth embodiment, for the same reason as described in the sixth and seventh embodiments, the step d3 of the main conductor film 18a of the lower buried wiring Ln is higher in the upper buried wiring layer Ln. The main conductor film 18a is formed larger than the step d4. Therefore, according to the eighth embodiment, the TDDB life is improved by increasing the step on the upper surface of the main conductor film 18a in the embedded wiring Ln of the lower wiring layer N1 where copper diffusion is likely to be a problem. On the other hand, in the upper wiring layer Nx having a margin, the step on the upper surface of the main conductor film 18a of the embedded wiring Ln is formed to be small to satisfy the process restrictions such as suppressing or preventing the occurrence of a defect due to the step. As a result, the overall reliability of the semiconductor device can be improved.

  As a modification of the eighth embodiment, the buried wiring Ln in the lower wiring layer N1 has the buried wiring structure described in the first embodiment and the like, and the buried wiring Ln in the upper wiring layer Nx is shown in FIG. You can leave it. Further, the embedded wiring Ln of the lower wiring layer N1 remains as in FIG. 25, and the embedded wiring Ln of the upper wiring layer Nx is replaced with the embedded wiring structure described in the first embodiment or the upper layer of FIG. A normal buried wiring structure in the wiring layer Nx may be used.

(Embodiment 9)
In the ninth embodiment, another technique for changing the stepped state of the embedded wiring according to the wiring layer will be described. FIG. 26 is a fragmentary cross-sectional view schematically showing the semiconductor device of the ninth embodiment. In the ninth embodiment, the upper surface (first surface) of the buried wiring Ln of the lower wiring layer N1 and the upper wiring layer Nx and the upper surface (first surface) of the conductive barrier film 17a are the upper surfaces of the insulating film 12b (first surface). It is lower than the CMP surface and the second surface. Thereby, it is possible to suppress or prevent the formation of a leak path by moving the main conductor film 18a away from the CMP surface, and to improve the TDDB life.

  Such a technique for providing a step on the upper surface of the embedded wiring Ln is also disclosed in, for example, Japanese Patent Application No. 2001-131941 (filing date; April 27, 2001) by the present inventor. However, in the ninth embodiment, for the same reason as described in the sixth to eighth embodiments, the step d5 of the main conductor film 18a of the embedded wiring Ln in the lower wiring layer N1 is higher in the upper wiring. The layer Nx is formed to be larger than the step d6 of the main conductor film 18a of the embedded wiring layer Ln. Therefore, according to the ninth embodiment, it is possible to improve the TDDB life by increasing the step on the upper surface of the embedded wiring Ln of the lower wiring layer N1 where copper diffusion is likely to be a problem. In a certain upper wiring layer Nx, it is possible to improve the overall reliability of the semiconductor device by forming a small step on the upper surface of the embedded wiring Ln to suppress or prevent the occurrence of problems due to the step.

  As a modification of the ninth embodiment, the buried wiring Ln in the lower wiring layer N1 has the buried wiring structure described in the first embodiment and the like, and the buried wiring Ln in the upper wiring layer Nx is changed to that shown in FIG. You can leave it. Further, the embedded wiring Ln of the lower wiring layer N1 remains as in FIG. 26, and the embedded wiring Ln of the upper wiring layer Nx is replaced with the embedded wiring structure described in the first embodiment or the like in the upper layer of FIG. A normal buried wiring structure in the wiring layer Nx may be used.

(Embodiment 10)
In the tenth embodiment, another technique for changing the stepped state of the embedded wiring according to the wiring layer will be described. FIG. 27 is a principal part sectional view schematically showing the semiconductor device of the tenth embodiment. In the tenth embodiment, the upper surface (CMP surface, first surface) of the buried wiring Ln of the lower wiring layer N1 and the upper wiring layer Nx and the conductive barrier film 17a are formed of the insulating film 12b. It protrudes from the upper surface (second surface). As a result, the main conductor film 18a can be moved away from the CMP surface, and the formation of a leak path can be suppressed or prevented, so that the TDDB life can be improved. Further, in this case, since the insulating film for the insulating cap is eliminated, the step can be formed by etching and removing the upper surface of the insulating film 11b during the reducing plasma treatment, and therefore the process can be simplified.

  A technique for providing a step on the upper surface of the embedded wiring Ln is also disclosed in, for example, Japanese Patent Application No. 2001-131941 (filed date: April 27, 2001) by the present inventor. Then, for the same reason as described in the sixth to ninth embodiments, the protruding step d7 of the embedded wiring Ln in the lower wiring layer N1 is more prominent than the protruding step of the embedded wiring layer Ln in the upper wiring layer Nx. It is formed larger than d8. In other words, the TDDB life can be improved by increasing the protruding step on the upper surface of the embedded wiring Ln of the lower wiring layer N1 where copper diffusion is likely to be a problem, while the upper wiring layer Nx with sufficient margin can be improved. The overall reliability of the semiconductor device can be improved by satisfying process restrictions such as suppressing or preventing the occurrence of defects due to the step by forming the protruding step on the upper surface of the embedded wiring Ln to be small.

  As a modification of the tenth embodiment, the buried wiring Ln in the lower wiring layer N1 has the buried wiring structure described in the first, eighth, and ninth embodiments, and the buried wiring Ln in the upper wiring layer Nx is changed to the embedded wiring Ln. 27 may be left as it is. Further, the embedded wiring Ln of the lower wiring layer N1 remains as shown in FIG. 27, and the embedded wiring Ln of the upper wiring layer Nx is replaced with the embedded wiring structure described in the first, eighth, and ninth embodiments or FIG. A normal buried wiring structure in the upper wiring layer Nx may be used.

As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  In the first to tenth embodiments, the case where the cap film is continuously formed without vacuum break after the post-treatment (plasma treatment) has been described. A cap film may be formed. Although the effect of the present invention can be more effectively achieved if the vacuum is not broken, a thin nitride layer is formed by the ammonia plasma treatment in the post-treatment. Formation can be suppressed. Therefore, even when the vacuum breaks, the effect of the present embodiment can be achieved to some extent.

  Further, the method of forming the round taper in the main conductor film of the embedded wiring is not limited to the one described in the first to tenth embodiments, and can be variously modified. For example, the processing chamber of the plasma CVD apparatus is evacuated. A round taper may be formed at the upper corner of the main conductor film of the buried wiring by maintaining the state and performing heat treatment on the wafer without supplying gas in the processing chamber.

  In the above embodiment, the case where the round taper is formed on the upper surface of the embedded wiring in the film forming apparatus for forming the insulating film for the insulating cap has been described. However, the present invention is not limited to this. A round taper may be formed on the upper surface of the embedded wiring by performing heat treatment in a hydrogen gas atmosphere or a nitrogen gas atmosphere outside the film forming apparatus. Specifically, for example, the processing temperature in the low-temperature hydrogen annealing of the embodiment may be set higher than that of the embodiment, and the processing time may be lengthened. In this case, the treatment temperature is preferably about 300 ° C. to 400 ° C., and the treatment time is preferably about 30 seconds to 15 minutes, for example.

  In the above description, the case where the invention made mainly by the present inventor is applied to the manufacturing technology of a semiconductor device having a CMIS circuit which is a field of use as a background has been described. However, the present invention is not limited to this. (Dynamic Random Access Memory), SRAM (Static Random Access Memory), flash memory (EEPROM: Electric Erasable Programmable Read Only Memory), FRAM (Ferro electric Random Access Memory), etc. The present invention can also be applied to various semiconductor device manufacturing methods such as a semiconductor device having such a logic circuit or a mixed-type semiconductor device in which the memory circuit and the logic circuit are provided on the same semiconductor substrate. The present invention can be applied to a manufacturing method of a semiconductor device, a semiconductor integrated circuit device, an electronic circuit device, an electronic device, a micromachine, or the like having at least a buried copper wiring structure.

  The present invention can be applied to the semiconductor device manufacturing industry.

It is a top view of the sample used for TDDB lifetime measurement of this Embodiment. It is sectional drawing of the B-B 'line | wire of FIG. It is sectional drawing of the C-C 'line | wire of FIG. It is explanatory drawing which showed the outline | summary of the measurement at the time of using the sample of FIG. It is a flowchart of the manufacturing process of the semiconductor device which is one embodiment of this invention. It is a principal part top view in the manufacturing process of the semiconductor device which is one embodiment of this invention. It is sectional drawing of the X1-X1 line | wire of FIG. FIG. 8 is a cross-sectional view of a portion corresponding to line X1-X1 in FIG. 5 during a manufacturing step of the semiconductor device following that of FIG. 7; FIG. 9 is a cross-sectional view of a portion corresponding to line X1-X1 in FIG. 5 during a manufacturing step of the semiconductor device following that of FIG. 8; FIG. 10 is a cross-sectional view of a portion corresponding to line X1-X1 in FIG. 5 during a manufacturing step of the semiconductor device following that of FIG. 9; FIG. 11 is a cross-sectional view of a portion corresponding to line X1-X1 in FIG. 5 during a manufacturing step of the semiconductor device following that of FIG. 10; It is a principal part expanded sectional view of FIG. FIG. 13 is a cross-sectional view of a portion corresponding to the X1-X1 line in FIG. 5 during a manufacturing step of the semiconductor device following that of FIGS. 11 and 12; FIG. 14 is a cross-sectional view of a portion corresponding to line X1-X1 in FIG. 5 during a manufacturing step of the semiconductor device following that of FIG. 13; FIG. 15 is a cross-sectional view of a portion corresponding to line X1-X1 in FIG. 5 during a manufacturing step of the semiconductor device following that of FIG. 14; FIG. 16 is a fragmentary plan view of the semiconductor device during a manufacturing step following that of FIG. 15; It is sectional drawing of the X2-X2 line | wire of FIG. It is a principal part expanded sectional view of FIG. It is a flowchart of the manufacturing process of the semiconductor device which is other embodiment of this invention. It is principal part sectional drawing in the manufacturing process of the semiconductor device which is other embodiment of this invention. It is principal part sectional drawing in the manufacturing process of the semiconductor device in other embodiment of this invention. It is principal part sectional drawing in the manufacturing process of the semiconductor device in other embodiment of this invention. It is principal part sectional drawing which shows typically the semiconductor device which is other embodiment of this invention. It is principal part sectional drawing which shows typically the semiconductor device which is other embodiment of this invention. It is principal part sectional drawing which shows typically the semiconductor device which is other embodiment of this invention. It is principal part sectional drawing which shows typically the semiconductor device which is other embodiment of this invention. It is principal part sectional drawing which shows typically the semiconductor device which is other embodiment of this invention.

Explanation of symbols

1W Wafer 1S Semiconductor substrate 2 Separating part 3 Gate insulating film 4 Gate electrode 5 Side wall 6, 7 Semiconductor region 8 Insulating film 9 Contact hole 10 Plug 11a Insulating film 11b to 11d Insulating film (first insulating film)
12a Insulating films 12b to 12d Insulating film (first insulating film)
13 Through hole 14 Plug 15a Insulating film (first insulating film)
15b Insulating film (second insulating film)
15b1 insulating film (third insulating film)
15b2 Insulating film (fourth insulating film)
15c Insulating film (first insulating film)
15d Insulating film (second insulating film)
16a, 16b Wiring groove (wiring opening)
17a, 17b Conductive barrier film (first conductor film)
18a, 18b Main conductor film (second conductor film)
19 Through hole (wiring opening)
L Comb wiring M2 Second wiring layer P1, P2 Pad S Measurement stage H Heater Qp p channel type MIS • FET
Qn n-channel type MIS • FET
PWL p-type well NWL n-type well N1, Nx wiring layer L2 buried second layer wiring (wiring)
L3 Embedded third layer wiring (wiring)
Ln Embedded wiring (wiring)

Claims (14)

In each wiring forming step of the plurality of wiring layers formed on the wafer, (a) a step of depositing a first insulating film on the wafer, (b) a step of forming a wiring opening in the first insulating film, (C) forming a wiring including a first conductor film having a barrier property against copper diffusion and a second conductor film containing copper as a main component in the wiring opening; (d) the first insulating film; And a step of depositing a second insulating film on the wiring,
Among the plurality of wiring layers, in the wiring forming step of the wiring layer relatively close to the main surface of the wafer, the second conductor film includes the first conductive layer between the step (c) and the step (d). A process of forming a step between the first surface on which the second insulating film is deposited and the second surface on the first insulating film on which the second insulating film is deposited; Have
Of the plurality of wiring layers, in the wiring forming step of the wiring layer relatively far from the main surface of the wafer, the second insulating film is deposited without passing through the step. A method for manufacturing a semiconductor device. In a wiring forming process of at least two wiring layers of a plurality of wiring layers formed on the wafer, (a) a step of depositing a first insulating film on the wafer, (b) a wiring opening in the first insulating film. (C) forming a wiring including a first conductor film having a barrier property against copper diffusion and a second conductor film containing copper as a main component in the wiring opening; A step is formed between the first surface of the second conductor film on the side where the second insulating film is deposited and the second surface of the first insulating film on the side where the second insulating film is deposited. And (e) depositing the second insulating film on the first insulating film and the wiring,
Among the plurality of wiring layers, the step of the second conductor film in the wiring of the wiring layer relatively close to the main surface of the wafer is relatively far from the main surface of the wafer among the plurality of wiring layers. A method of manufacturing a semiconductor device, wherein the second conductor film is formed to be larger than the step in the wiring of the wiring layer. The method of manufacturing a semiconductor device according to claim 2.
In the step (d), the surface layer of the first surface of the second conductor film is formed such that the first surface of the second conductor film is recessed in the direction of the main surface of the wafer from the second surface of the first insulating film. A method of manufacturing a semiconductor device, wherein the step of selectively etching away is performed. In each wiring forming step of the plurality of wiring layers formed on the wafer, (a) a step of depositing a first insulating film on the wafer, (b) a step of forming a wiring opening in the first insulating film, (C) forming a wiring including a first conductor film having a barrier property against copper diffusion and a second conductor film containing copper as a main component in the wiring opening; (d) the first insulating film; And a step of depositing a second insulating film on the wiring,
Among the plurality of wiring layers, in the wiring forming step of the wiring layer relatively close to the main surface of the wafer, the first and second conductor films are provided between the step (c) and the step (d). In the processing, a step is formed between the first surface on the side where the second insulating film is deposited and the second surface on the side where the second insulating film is deposited in the first insulating film. A process of applying,
Of the plurality of wiring layers, in the wiring forming step of the wiring layer relatively far from the main surface of the wafer, the second insulating film is deposited without passing through the step. A method for manufacturing a semiconductor device. In a wiring forming process of at least two wiring layers of a plurality of wiring layers formed on the wafer, (a) a step of depositing a first insulating film on the wafer, (b) a wiring opening in the first insulating film. (C) forming a wiring including a first conductor film having a barrier property against copper diffusion and a second conductor film containing copper as a main component in the wiring opening; A step is formed between the first surface of the first and second conductor films on the side where the second insulating film is deposited and the second surface of the first insulating film on the side where the second insulating film is deposited. And (e) depositing the second insulating film on the first insulating film and the wiring,
Among the plurality of wiring layers, the step in the wiring of the wiring layer relatively close to the main surface of the wafer is changed in the wiring of the wiring layer relatively far from the main surface of the wafer among the plurality of wiring layers. A manufacturing method of a semiconductor device, wherein the semiconductor device is formed larger than the step. In the manufacturing method of the semiconductor device according to claim 5,
In the step (d), the first and second conductor films are formed such that the first surfaces of the first and second conductor films are recessed in the direction of the main surface of the wafer from the polished surface of the first insulating film. A method for manufacturing a semiconductor device, the method comprising selectively etching away a surface layer of a first surface. In the manufacturing method of the semiconductor device according to claim 5,
In the step (d), the first insulating film is formed such that the first surfaces of the first and second conductor films protrude in a direction away from the main surface of the wafer relative to the second surface of the first insulating film. A method for manufacturing a semiconductor device, wherein the second surface is selectively etched away. At least two wiring layers of the plurality of wiring layers formed on the semiconductor substrate are: (a) a wiring opening formed in the first insulating film; and (b) a barrier against copper diffusion in the wiring opening. A wiring formed by embedding a first conductive film and a second conductive film containing copper as a main component; (c) a first insulating film and a second insulating film deposited on the wiring; ,
Of the plurality of wiring layers, the wiring of the wiring layer relatively close to the main surface of the semiconductor substrate includes a first surface on the second conductor film on which the second insulating film is deposited, A step is provided between the first conductor film and the second surface of the first insulating film on which the second insulating film is deposited;
Among the plurality of wiring layers, the wiring of the wiring layer relatively far from the main surface of the semiconductor substrate includes a first surface of the second conductor film, a second of the first conductor film and the first insulating film. A semiconductor device characterized in that the semiconductor device is formed so as to substantially coincide with a surface. At least two wiring layers of the plurality of wiring layers formed on the semiconductor substrate are: (a) a wiring opening formed in the first insulating film; and (b) a barrier against copper diffusion in the wiring opening. A first surface of the second conductor film on which the second insulating film is deposited, and the first conductor. A wiring provided with a step between the film and the second surface of the first insulating film on which the second insulating film is deposited; (c) a first film deposited on the first insulating film and the wiring; Has two insulating films,
Among the plurality of wiring layers, the step in the wiring of the wiring layer relatively close to the main surface of the semiconductor substrate is the wiring layer relatively far from the main surface of the semiconductor substrate among the plurality of wiring layers. A semiconductor device characterized by being larger than the step in the wiring.   10. The semiconductor device according to claim 9, wherein the step is such that the first surface of the second conductor film is recessed in the direction of the main surface of the semiconductor substrate from the second surface of the first conductor film and the first insulating film. A semiconductor device characterized by being formed. At least two wiring layers of the plurality of wiring layers formed on the semiconductor substrate are: (a) a wiring opening formed in the first insulating film; and (b) a barrier against copper diffusion in the wiring opening. A wiring formed by embedding a first conductive film and a second conductive film containing copper as a main component; (c) a first insulating film and a second insulating film deposited on the wiring; ,
Among the plurality of wiring layers, the wiring in the wiring layer relatively close to the main surface of the semiconductor substrate includes a first surface on the side where the second insulating film is deposited in the first and second conductor films, A step is provided between the first insulating film and the second surface on which the second insulating film is deposited;
Among the plurality of wiring layers, the wiring of the wiring layer relatively far from the main surface of the semiconductor substrate includes a first surface of the first and second conductor films, and a second surface of the first insulating film. Are formed so as to substantially coincide with each other. At least two wiring layers of the plurality of wiring layers formed on the semiconductor substrate are: (a) a wiring opening formed in the first insulating film; and (b) a barrier against copper diffusion in the wiring opening. A first surface of the first and second conductor films on which a second insulating film is deposited; and A wiring in which a step is provided between the first insulating film and the second surface on which the second insulating film is deposited; (c) the second insulating film deposited on the first insulating film and the wiring; Have
Among the plurality of wiring layers, the step in the wiring of the wiring layer relatively close to the main surface of the semiconductor substrate is the wiring layer relatively far from the main surface of the semiconductor substrate among the plurality of wiring layers. A semiconductor device characterized by being larger than the step in the wiring.   13. The semiconductor device according to claim 12, wherein the step is such that the first surfaces of the first and second conductor films are recessed in the direction of the main surface of the semiconductor substrate from the second surface of the first insulating film. A semiconductor device formed by the method described above.   13. The semiconductor device according to claim 12, wherein the step protrudes in a direction in which the first surfaces of the first and second conductor films are farther from the main surface of the semiconductor substrate than the second surface of the first insulating film. A semiconductor device characterized by being formed.

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