JP2006174104A - Transport stream signal distribution device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To supply a transport stream signal to a plurality of devices without changing a cable.
An MPEG transport stream of a differential signal is received by an input line receiver 10 and converted into a single-ended transport stream. The clock signal from the input line receiver 10 is supplied to a clock recovery means (CLOCK) 12, and each signal is generated in the stream data synchronization means (DATA) 11, the packet synchronization signal synchronization means 13 and the DVALID signal synchronization means 14 by the recovered clock. Are synchronized, distributed and supplied to the output line drivers 15 and 16. The output line drivers 15 and 16 generate and output a differential signal MPEG transport stream.
[Selection] Figure 1

Description

  The present invention relates to a transport stream signal distribution device that distributes a transport stream signal obtained by compressing video data according to MPEG (Moving Picture Experts Group) standards.

  The MPEG system stipulates a method for multiplexing individual streams such as an arbitrary number of encoded video, audio, and additional data and reproducing them while synchronizing them. For example, in the MPEG-2 system, two types of schemes of a program stream (PS: Program Stream) and a transport stream (TS: Transport Stream) are defined in order to deal with a wide range of applications. It is assumed that the program stream is applied to data transmission / storage in an error-free environment, and since the redundancy can be reduced, it is a digital storage medium using a powerful error correction code such as a DVD. in use. On the other hand, the transport stream is assumed to be applied to an environment in which data transmission errors occur, such as broadcasting and communication networks, and the redundancy is higher than that of the program stream. The transport stream is used in a communication path with a fixed transmission rate.

  The transport stream is composed of a plurality of transport packets (TS packets). The TS packet is a 188-byte fixed-length packet, and its length is determined in consideration of consistency with the ATM cell length and applicability when performing error correction coding such as Reed-Solomon code. The TS packet includes a packet header having a fixed length of 4 bytes, an adaptation field having a variable length, and a payload. PID (packet identifier) and various flags are defined in the packet header. The type of TS packet is identified by this PID. There are cases where only one of the adaptation field and the payload exists or both, and the presence / absence thereof is indicated by a flag (adaptation_field_control) in the packet header. The flag (adaptation_field_control) has information transmission such as PCR (Program_Clock_Reference) and a stuffing function in the TS packet for making the TS packet have a fixed length of 188 bytes. The PCR is a time stamp of 27 MHz, and the value of the PCR is referred to reproduce the reference time when encoded by the STC of the decoder. In the MPEG-2 transport stream, the STC of the decoder has a PLL function by PCR, but the PCR transmission interval is 0.1 ms or less in order to stabilize the PLL synchronization operation.

  Such a transport stream signal is transmitted via a cable between digital image apparatuses and digital image-related devices. When performing experiments and measurements using digital imaging devices and digital image-related devices, it is sufficient to selectively supply transport stream signals to these devices. Conventionally, however, any device can be connected by changing the cable. A transport stream signal was supplied. For this reason, there is a problem that the cable must be reconnected every time the device for supplying the transport stream signal is changed, and the work is troublesome.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a transport stream signal distribution apparatus that can supply transport stream signals to a plurality of devices without changing cables.

  In order to achieve the above object, a transport stream signal distribution device of the present invention converts a differential transport stream signal into a single-ended transport signal, performs signal processing and distributes the differential signal, and further performs differential signal processing. The most important feature is that it is converted into a transport stream signal and output respectively.

  According to the present invention, a differential transport stream signal is converted into a single-ended transport signal for signal processing and distribution, and further converted into a differential transport stream signal for output. Thus, a plurality of transport stream signals can be output. As a result, transport stream signals can be supplied to a plurality of devices, so that the work of changing the cable can be omitted.

  Converting a differential transport stream signal to a single-ended transport signal for the purpose of providing a transport stream signal distribution device that can supply transport stream signals to multiple devices without changing cables Then, the signal processing is performed and distributed, and further converted into a differential transport stream signal and output.

FIG. 1 is a circuit block diagram showing the configuration of a transport stream signal distribution device according to an embodiment of the present invention.
In the transport stream signal distribution device 1 shown in FIG. 1, the input line receiver 10 is provided with, for example, a 25-pin terminal for SPI (Synchronous Parallel Interface), and video is transmitted via a cable connected to this terminal. An MPEG transport stream signal (MPEG TS) obtained by compressing data according to the MPEG standard is input. The MPEG transport stream signal is transmitted as a differential signal, for example, transmitted by low voltage differential signaling (LVDS) and received by the input line receiver 10.

  LVDS is a communication system that performs data communication with a differential signal with a very small amplitude of about 350 mV, using one balanced cable or two wiring patterns of a printed wiring board as one transmission path. LVDS is capable of transmitting data on a single channel at a high speed of several hundred to several thousand Mbps, and is designed to transmit differential signals. Therefore, it is affected by common-mode noise compared to single-ended signals. It has difficult properties. This differential signal is transmitted as a signal (current, voltage) opposite to each other using a pair of wires. On the other hand, since the single-ended signal transmits data with one wire, the influence of noise becomes large. Further, since the differential signal cancels the magnetic field, the noise tends to be smaller than that of the single-ended signal. In the current mode driver, ringing and switching spikes are less likely to occur, and the noise is further reduced. Thus, since LVDS has high resistance to noise, it can be transmitted using a differential signal having a small voltage width, and can be transmitted at a high data rate and with low power consumption.

  Here, the pin arrangement in the 25-pin terminal for SPI in the input line receiver 10 through which the MPEG transport stream signal is transmitted by LVDS is shown in the table of FIG. At the 25-pin terminal for SPI, a differential signal for separating a clock signal as a differential signal, 8-bit parallel stream data as a differential signal, and a data portion and an error correction code portion in the stream data The MPEG transport stream signal in which the DVALID signal and the packet synchronization signal (PSYNC), which is the differential signal in the stream data, are supplied in parallel is supplied. The stream data is composed of a plurality of transport packets (TS packets), and the TS packet in the data part is a fixed length packet of 188 bytes.

  In this case, as shown in the table of FIG. 2, the differential clock signal is assigned to the first pin and the 14th pin (inverted clock signal) and transmitted, and the ground is assigned to the second pin, the 13th pin, and the 15th pin. ing. The seventh bit (bit 7), which is the differential MSB, is assigned to the third pin and the sixteenth pin (inverted seventh bit signal) for transmission, and the sixth differential bit (bit 6) is transferred to the fourth pin and the 17th pin. Pin 5 (inverted 6th bit signal) is assigned and transmitted, and differential 5th bit (bit5) is assigned to 5th pin and 18th pin (inverted 5th bit signal) and transmitted. Bit (bit 4) is assigned to the 6th pin and 19th pin (inverted 4th bit signal) and transmitted, and the differential 3rd bit (bit3) is assigned to the 7th pin and 20th pin (inverted 3rd bit signal) The differential second bit (bit 2) is assigned to the eighth and 21st pins (inverted second bit signal) and transmitted, and the first differential bit (bit 1) is transmitted to the ninth and 22nd pins. Pin (inverted first Tsu transmitted preparative signals) assigned to the zeroth bit is LSB differential (bit0) is transmitted assigned to the 10th pin and the pin 23 (the inverted 0th bit signal). Further, the differential DVALID signal is assigned to the 11th and 24th pins (inverted DVALID signal) and transmitted, and the differential packet synchronization signal (PSYNC) is assigned to the 12th and 25th pins (inverted PSYNC signal). Is being transmitted.

  In the input line receiver 10, a clock signal received as a parallel differential signal, an 8-bit parallel stream data converted into a differential signal, a DVALID signal converted into a differential signal, and a differential signal are input. The packet synchronization signal (PSYNC) is received and converted into a single-ended clock signal, 8-bit parallel stream data, a DVALID signal, and a packet synchronization signal (PSYNC). The single-ended signal level is preferably the level of the C-MOS logic circuit. This is because it is desirable to perform signal processing of each signal converted to single end by a C-MOS logic circuit.

  FIG. 3 shows an example of waveforms of the converted single-ended clock signal, 8-bit parallel stream data, DVALID signal, and packet synchronization signal (PSYNC). As shown in FIG. 3, the clock signal is a periodic rectangular pulse determined by the transmission rate. In addition, stream data [0 ... 7] converted to 8-bit parallel (1 byte parallel) includes a data portion (1 to 187) of a 188-byte transport packet and a transmission error for correcting the data portion. It consists of a 16-byte error correction code part (1d to 16d), and the 8-bit parallel leading bit of the data part made 8-bit parallel is a synchronization signal (sync). The DVALID signal is at the H level during the 188-byte period (t0 to t188) and is at the L level during the subsequent 16-byte period (t189 to t204). Therefore, stream data can be separated into a data part and an error correction code part based on the DVALID signal. The packet synchronization signal (PSYNC) is at the H level in the period (t0 to t1) of the first bit of the 8-bit parallel that is the synchronization signal (sync) of the data part that is 8-bit parallel, and is L in the other periods. It is a level. Therefore, the synchronization signal (sync) can be separated from the data portion based on the packet synchronization signal (PSYNC).

  Such stream data [0 ... 7] is supplied to the stream data synchronization means (DATA) 11 and the clock signal is supplied to the clock recovery means (CLOCK) 12. The packet synchronization signal is supplied to a packet synchronization signal synchronization means (PSYNC) 13 and the DVALID signal is supplied to a DVALID signal synchronization means (DVALID) 14. The clock recovery means 12 has a built-in PLL circuit, reproduces the clock signal based on the single-ended clock signal supplied from the input line receiver 10, and outputs a recovered clock signal from which phase jitter has been removed. . This reproduced clock signal is supplied to the stream data synchronizing means (DATA) 11, the packet synchronizing signal synchronizing means (PSYNC) 13, and the DVALID signal synchronizing means (DVALID) 14, and the stream data [0 ... 7] is generated by the reproduced clock signal. The phase jitter is removed by resynchronizing the packet synchronization signal and the DVALID signal.

  Stream data [0 ... 7] from which phase jitter output from the stream data synchronization means (DATA) 11, the packet synchronization signal synchronization means (PSYNC) 13 and the DVALID signal synchronization means (DVALID) 14 is removed, and the packet synchronization signal. And the DVALID signal are distributed and supplied to the output line driver 15 and the output line driver 16. The output line driver 15 and the output line driver 16 convert the supplied single-ended stream data [0 ... 7], the packet synchronization signal, and the DVALID signal into a differential signal, a clock signal, a difference An 8-bit parallel stream data converted into a motion signal, a DVALID signal converted into a differential signal, and an MPEG transport stream signal in which a packet synchronization signal (PSYNC) converted into a differential signal is made parallel are output. The output line driver 15 and the output line driver 16 also have a 25-pin terminal having the pin arrangement shown in FIG. 2, and the output MPEG transport stream signal is transmitted by LVDS.

The stream data synchronization means (DATA) 11, the clock recovery means (CLOCK) 12, the packet synchronization signal synchronization means (PSYNC) 13, and the DVALID signal synchronization means (DVALID) 14 that perform signal processing are, for example, C-MOS logic. This is realized by an integrated circuit constituted by circuits.
In the transport stream signal distribution apparatus 1 configured as described above, a device for outputting an MPEG transport stream signal is connected to the input line receiver 10 via a cable, and MPEGs are respectively connected to the output line drivers 15 and 16. A device to which a transport stream signal is input is connected via a cable. As a result, the MPEG transport stream output 1 output from the output line driver 15 is supplied to the first digital image-related device, and the MPEG transport stream output 2 output from the output line driver 16 is the second. Will be supplied to digital image related equipment. As a result, the MPEG transport stream signal can be supplied to a plurality of digital image-related devices without reconnection.

In the above description, the MPEG transport stream signal distribution device is used. However, the present invention is not limited to this, and the present invention can be applied to a parallel stream signal distribution device transmitted as a differential signal.
Moreover, although the transport stream signal distribution device 1 is provided with the SPI terminal, it is not limited to the SPI terminal, and may be provided with a terminal of another standard. However, at least 23 pins are required. Furthermore, although the MPEG transport stream signal is transmitted by LVDS, it may be transmitted by differential communication such as HVDS (High Voltage Differential Signaling).

It is a circuit block diagram which shows the structure of the transport stream signal distribution apparatus of the Example of this invention. It is a table | surface which shows the pin arrangement in the terminal of 25 pins for SPI with which the transport stream signal distribution apparatus of this invention is provided. It is a figure which shows an example of the waveform of the converted single end clock signal in the transport stream signal distribution apparatus of this invention, 8-bit parallel stream data, a DVALID signal, and a packet synchronization signal (PSYNC).

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Transport stream signal distribution apparatus, 10 input line receiver, 10 input line receiver, 11 stream data synchronizing means, 12 clock reproduction means, 13 packet synchronizing signal synchronizing means, 14 DVALID signal synchronizing means, 15 output line driver, 16 Output line driver

Claims (2)

At least the stream data and the clock signal are made parallel and a transport stream signal transmitted as a differential signal is received, and the stream data and the clock signal which are made a differential signal are converted into single-ended stream data and a clock. An input line receiver that converts the signal to output, and
Clock recovery means for outputting a recovered clock signal recovered based on a single-ended clock signal output from the input line receiver;
Stream data synchronization means for outputting the single-ended stream data output from the input line receiver by resynchronizing with the recovered clock signal output from the clock recovery means;
The single-ended stream data output from the stream data synchronization means and the reproduced clock signal are distributed and supplied, and by converting the supplied single-ended stream data and the clock signal, A plurality of output line drivers that respectively generate and output transport stream signals that have been converted into differential signals;
A transport stream signal distribution device comprising: The stream data is composed of a plurality of transport packets, and the input line receiver also receives a packet synchronization signal of the transport packet, which is a differential signal in the transport stream signal, and converts it into a single-ended packet synchronization signal. A packet synchronization signal synchronization means that outputs the converted signal and resynchronizes the single-ended packet synchronization signal output from the input line receiver with the recovered clock signal output from the clock recovery means; In addition, each of the plurality of output line drivers is parallelized and converted by converting the single-ended packet synchronization signal output from the packet synchronization signal synchronization means supplied and distributed. Transport stream as a dynamic signal Transport stream signal distribution apparatus of claim 1, wherein it has signals to generate and output respectively.

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