JP2006173194A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a means capable of avoiding the cause as well as specifying the cause of the breakdown of a gate insulating film generated in the manufacturing process of a semiconductor device having a pad with multilayer structure. <P>SOLUTION: It may be considered as the cause of the breakdown of a gate insulating film that the electric charge collected in a lower layer pad 10 acts on the gate of a transistor 20 when the lower layer pad 10 functions as an antenna element. The electric charge which poses a problem is discharged to a semiconductor substrate 30 by connecting the lower layer pad 10 and the semiconductor substrate 30 by wiring 40 in the manufacturing process. Then, the wiring 40 is cut after the manufacturing process. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor device such as a memory device.

  2. Description of the Related Art Conventionally, a technique is known in which pads are multi-layered into a plurality of pad portions in order to prevent peeling of the pads during wire bonding, and these are interconnected by a large number of contacts or vias (for example, Patent Document 1). Such a memory device is also employed.

  At present, the number of layers of a multilayered pad employed in a memory device is generally two or three, and aluminum is generally used as a material for each pad portion and via.

JP-A-2001-267319, column 0004 and FIG. 5, column 0021 and FIG.

  In the manufacturing process of a memory device including a multi-layer pad, there is a problem that a gate insulating film of a transistor constituting the memory device is broken. Specifically, even in the case of a memory device having the same layout as that of a memory device that does not cause a problem, the gate insulating film may be broken if the manufacturing conditions are different or the device used for manufacturing is different.

  An object of the present invention is to provide a means for identifying the cause of the breakdown of the gate insulating film and avoiding it.

  As a result of searching for the cause of the gate insulating film breakdown described above, the inventors of the present invention collect positive charges in the lower pad part in a plasma CVD process for forming a plurality of contacts on the lower pad part. I realized there was a problem.

  Since the lower layer pad portion has a larger area than ordinary wiring or the like, there is a high possibility that it functions as an antenna element that easily collects charges. In particular, the input pad is connected to the gate of a transistor included in the memory device, and the collected charge may damage the gate insulating film.

  In order to protect the gate insulating film, an ESD (electrostatic discharge) protection element may be provided in the memory device.

  However, the ESD protection element usually starts to function after the completion of wiring, whereas the lower layer pad portion may be unnecessarily charged up before the wiring is completed. Therefore, a normal ESD protection element cannot cope with it.

  In addition, the gate potential fluctuation due to the antenna effect of the lower layer pad portion is not instantaneous as in the ESD spike but gradually rises. Therefore, the ESD countermeasure itself is not suitable as this kind of problem solving means. is there.

  On the other hand, the amount of positive charge collected at the lower pad portion is instantaneously small. Therefore, if the positive charge collected in the lower pad part is dropped into a kind of saucer each time, the potential rise in the lower pad part that would be a problem can be avoided, but it seems to be optimal as such a charge catcher. It is the substrate.

  The present invention has been made on the basis of the above consideration. Specifically, the following method for manufacturing a semiconductor device is provided as means for solving the above-described problems.

  In other words, according to the present invention, in a method of manufacturing a semiconductor device including a lower layer pad portion, an upper layer pad portion, and a pad having a multilayer structure having a plurality of contacts electrically connected therebetween, before forming the plurality of contacts. A method for manufacturing a semiconductor device is obtained in which connection means for electrically connecting the lower layer pad portion to the semiconductor substrate is established, and the connection means is invalidated after forming the plurality of contacts.

  As described above, the present invention has been made by paying attention to the problems in the pad having a multilayer structure, but the concept itself of dropping the electric charge collected on the antenna element onto the substrate is that the antenna element is specified. It can be widely applied to cases. For example, a single-layer pad may function as an antenna element in view of its large area compared to other elements, and other antenna elements other than the pad may cause the same type of problem. However, the concept of the present invention can be applied if an element that can function as an antenna element can be identified. Under such consideration, the present invention further provides a method for manufacturing a semiconductor device as described below.

  That is, according to the present invention, a first step of electrically connecting an antenna element that easily collects charges to a semiconductor substrate and dropping the charges collected on the antenna element to the semiconductor substrate, and the first step As a subsequent process, a method for manufacturing a semiconductor device including a second process of cutting off electrical connection between the antenna element and the semiconductor substrate is obtained.

  According to the present invention, the semiconductor device manufactured according to the semiconductor device manufacturing method described above is an invalidated electrical connection means in a semiconductor device including an antenna element and a semiconductor substrate that easily collect charges. A semiconductor device is further provided that further includes an electrical connection means that electrically connects the antenna element and the semiconductor substrate when they are effective.

  When the semiconductor device includes a lower layer pad portion, an upper layer pad portion, and a multi-layered pad having a plurality of contacts electrically connected therebetween, the antenna element is, for example, the lower layer pad portion.

  According to the present invention, first, an antenna element that can cause a gate insulating film breakdown is specified. Moreover, since the number of pads specified as the antenna element is, for example, about 30 to 50 in the current memory device, it is not an unrealistic countermeasure targeting all the transistor gates, but a realistic countermeasure. Thus, the effect of preventing the gate insulating film from being broken can be obtained.

  Secondly, since a substrate having a large capacity is used as a tray for receiving charges collected in the antenna element, the reliability is higher than in the case where a wiring, a diffusion layer, or a specific element is used as a tray for receiving charges.

  Third, since a simple means of connecting the antenna element to the substrate is adopted, it is easy to cope with the antenna element even if it is registered before the wiring is completed. Can be prevented appropriately.

  Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 1 to 3. The semiconductor devices according to the embodiments of the present invention exemplified below are all DRAM devices and have a double-layered pad. The lower layer pad portion 10 is formed simultaneously with the formation of the first layer of Al wiring, and the upper layer pad portion is formed simultaneously with the formation of the second layer of Al wiring. W wiring may be formed below the Al wiring of the first layer. After the formation of the lower layer pad portion 10, an insulating layer is formed on the lower layer pad portion. A plurality of through holes are formed in the insulating layer, and contacts are formed. Thereafter, an upper layer pad portion is formed to obtain a two-layer pad. By forming the second-layer Al wiring, the wiring is completed. At this time, the pad is connected to the gate of the transistor 20 in the input stage. On the other hand, wiring is not yet completed at the time of forming the first Al wiring. Therefore, at this point in time, it cannot be known whether the lower layer pad portion 10 and the gate of the transistor 20 are connected without verifying the layout of the multilayer wiring structure, but there is a possibility of connection. When connected, the lower layer pad portion 10 functions as an antenna element and collects charges, thereby raising the gate potential of the transistor 20 and possibly damaging the gate insulating film. The embodiments listed below are specific examples in which the concept of the present invention is applied to such a problem.

  (First embodiment)

  As shown in FIG. 1A, in the first embodiment of the present invention, the lower layer pad portion 10 and the semiconductor substrate 30 are connected by a wiring 40 during the manufacturing process of the DRAM device.

  The connection by the wiring 40 may be performed at any time before the lower layer pad portion 10 may start to function as an antenna element. Specifically, it may be at the time of W wiring or at the first Al wiring. In the present embodiment, the wiring 40 is formed simultaneously with the Al wiring of the first layer, that is, when the lower layer pad portion 10 is formed. Since the wiring 40 is formed, the charges gradually gathering in the lower pad portion 10 are dropped into the semiconductor substrate 30 each time, so that the gate potential of the transistor 20 does not rise unnecessarily.

  Thereafter, as indicated by reference numeral 42 in FIG. 1B, the electrical connection between the lower layer pad portion 10 and the semiconductor substrate 30 is cut off by cutting the wiring 40. In the present embodiment, the wiring 40 is cut after the second-layer Al wiring is completed.

  More specifically, after the second layer Al wiring is completed, a passivation film is formed, and further, during the process of etching the passivation film to expose the upper pad portion and performing wire bonding, the passivation film, the insulating layer, etc. Etching is performed to at least partially expose the wiring 40, and the wiring exposed at any subsequent stage is physically cut.

  For example, a DRAM device usually includes a redundancy cell and a redundancy fuse for enabling / disabling the redundancy cell. In most cases, the redundancy fuse is formed in the same layer as the Al wiring of the first layer, but is exposed after the formation of the Al wiring of the second layer, and is cut as necessary. Since the wiring 40 according to the present embodiment is formed at the same time as the formation of the first-layer Al wiring, the partial exposure can be performed by slightly changing the mask in the fuse exposure process. It can be realized without increasing. The wiring 40 may be cut before the inspection process including the normal fuse cutting process.

  The electrical connection means between the lower layer pad 10 and the semiconductor substrate 30 in the present embodiment is a very simple wiring 40. Since the wiring 40 does not need to be routed unnecessarily, the position where the wiring 40 is formed is preferably in the vicinity of the lower layer pad portion 10. By forming the wiring 40 in the vicinity of the lower layer pad portion 10, the wiring 40 and the redundancy fuse can be easily distinguished from each other, so that erroneous cutting can be prevented. On the other hand, in consideration of the primary purpose of protecting the gate insulating film of the transistor 20, the wiring 40 may be formed in the vicinity of the gate of the transistor 20.

  (Second Embodiment)

The substrate potential V _bb is normally set to a negative value when the DRAM device is used. Therefore, a negative power supply (V _bb ) generation circuit 52 is provided in the DRAM device. This negative power supply generation circuit 52 is not turned on unless power is supplied to the DRAM device. That is, no negative power supply is generated. The second embodiment uses this negative power supply generation circuit 52.

  Specifically, as shown in FIG. 2A, the source S and the drain D of the depletion type nMOS transistor 50 are connected to the semiconductor substrate 30 and the lower layer pad portion 10, respectively. The nMOS transistor 50 is normally on, and continues to electrically connect the lower layer pad portion 10 and the semiconductor substrate 30 unless a negative power supply is supplied to the gate G. As a result, the charges collected in the lower layer pad portion 10 are dropped on the semiconductor substrate 30. Thus, the gate insulating film of the transistor 20 can be prevented from being broken.

  The gate G of the nMOS transistor 50 is finally connected to the negative power supply generation circuit 52 as shown in FIG. 2B, but this connection may be established at any time. For example, it may be at the time of forming the first layer of Al wiring or at the time of forming the second layer of Al wiring.

When power is supplied to the DRAM device, the negative power generation circuit 72 is also turned on. Thereby, a negative power supply (substrate potential V _bb in the present embodiment) is supplied to the gate G of the nMOS transistor 50, whereby the transistor 50 is turned off. In this way, the electrical connection between the lower layer pad portion 10 and the semiconductor substrate 30 is interrupted in a circuit manner when the DRAM device is actually used.

  According to the present embodiment, since invalidation of the electrical connection between the lower layer pad portion 10 and the semiconductor substrate 30 is achieved by turning on the power to the DRAM device, the first embodiment that requires wiring disconnection is achieved. In comparison, there is an effect that physical work for invalidating the electrical connection is not required during the manufacturing process of the DRAM device.

  (Third embodiment)

In the DRAM device, a high voltage (V _pp ) generation circuit 64 for generating a voltage V _pp higher than the power supply potential is provided for driving a word line. The high voltage generating circuit 64 is not turned on unless the DRAM device is powered on. That is, the high voltage _Vpp is not generated. The third embodiment uses this high voltage generation circuit 64. In the present embodiment, the semiconductor substrate 30 is a p-type substrate, and an n + -type diffusion layer 32 is formed in the semiconductor substrate 30.

  As shown in FIG. 3A, in the present embodiment, the drain D and the source S of the pMOS transistor 60 are connected to the semiconductor substrate 30 and the lower layer pad portion 10, respectively. The gate G of the transistor 60 is connected to the n + diffusion layer 32. Since the gate G is substantially at the same potential as the semiconductor substrate 30, the pMOS transistor 60 is in the on state, and the charge collected on the lower layer pad portion 10 is dropped to the semiconductor substrate 30. Therefore, the gate insulating film breakdown of the transistor 20 is prevented.

  The gate G of the pMOS transistor 60 is finally connected to the high voltage generating circuit 64 as shown in FIG. 3B, but this connection may be established anytime. For example, it may be at the time of forming the first layer of Al wiring or at the time of forming the second layer of Al wiring.

When power is supplied to the DRAM device, the high voltage generation circuit 64 is turned on. Thereby, the voltage V _pp is supplied to the gate G of the pMOS transistor 60, whereby the transistor 60 is turned off. In this way, the electrical connection between the lower layer pad portion 10 and the semiconductor substrate 30 is interrupted in a circuit manner when the DRAM device is actually used.

  In the present embodiment, like the second embodiment, the wiring connection is disconnected in order to invalidate the electrical connection between the lower layer pad portion 10 and the semiconductor substrate 30 that has been functioning during the manufacturing process of the DRAM device. There is an effect that no physical work is required.

It is a figure which shows the manufacturing method of the semiconductor device by the 1st Embodiment of this invention. It is a figure which shows the manufacturing method of the semiconductor device by the 2nd Embodiment of this invention. It is a figure which shows the manufacturing method of the semiconductor device by the 3rd Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Lower layer pad part 20 Transistor 30 Semiconductor substrate 32 n + diffusion layer 40 Wiring 50 (depletion type) nMOS transistor 52 Negative power supply generation circuit 60 pMOS transistor 64 High voltage generation circuit

Claims (21)

  In a method of manufacturing a semiconductor device including a lower layer pad portion, an upper layer pad portion, and a pad having a multilayer structure having a plurality of contacts electrically connected therebetween, the lower layer pad portion is formed on a semiconductor substrate before forming the plurality of contacts. A method for manufacturing a semiconductor device, comprising establishing connection means for electrical connection and disabling the connection means after forming the plurality of contacts.   The method for manufacturing a semiconductor device according to claim 1, wherein the connection means is established simultaneously with the formation of the lower layer pad portion.   The method of manufacturing a semiconductor device according to claim 1, wherein the invalidation of the connection means is performed after the formation of the upper layer pad portion.   4. The semiconductor device manufacturing according to claim 1, wherein the connection means is a wiring for connecting the lower layer pad portion and the semiconductor substrate, and the invalidation of the connection means is cutting of the wiring. 5. Method.   The connection means is a depletion type nMOS transistor having a source connected to the semiconductor substrate and a drain connected to the lower pad part, and the invalidation of the connection means supplies a negative voltage to the gate of the nMOS transistor. The manufacturing method of the semiconductor device in any one of Claims 1 thru | or 3.   The connection means is a pMOS transistor having a drain connected to the semiconductor substrate, a drain connected to the lower pad portion, and a gate connected to a diffusion layer provided in the semiconductor substrate. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the invalidation is supplying a voltage higher than a power supply voltage to a gate of the pMOS transistor.   The method of manufacturing a semiconductor device according to claim 5, wherein the invalidation of the connection means is achieved during actual use of the semiconductor device.   A first step of electrically connecting an antenna element that easily collects electric charges to a semiconductor substrate to drop the electric charge collected on the antenna element onto the semiconductor substrate, and a step after the first step, the antenna element And a second step of interrupting electrical connection with the semiconductor substrate.   The method of manufacturing a semiconductor device according to claim 8, wherein the antenna element is a pad.   The method of manufacturing a semiconductor device according to claim 9, wherein the antenna element is an input pad. The first step is to connect the antenna element and the semiconductor substrate by wiring;
The method of manufacturing a semiconductor device according to claim 8, wherein the second step is to cut the wiring. The first step is to connect a source of a depletion type nMOS transistor to the semiconductor substrate and connect a drain to the antenna element;
The method of manufacturing a semiconductor device according to claim 8, wherein the second step is supplying a negative voltage to a gate of the nMOS transistor. The first step is to connect the drain of the pMOS transistor to the semiconductor substrate, connect the drain to the antenna element, and connect the gate to a diffusion layer provided in the semiconductor substrate;
11. The method of manufacturing a semiconductor device according to claim 8, wherein the second step is to supply a voltage higher than a power supply voltage to the gate of the pMOS transistor.   The method for manufacturing a semiconductor device according to claim 8, wherein the second step is performed after the uppermost wiring layer is formed.   The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is a memory device.   In a semiconductor device including an antenna element and a semiconductor substrate that easily collect electric charge, an invalid electrical connection means that electrically connects the antenna element and the semiconductor substrate when enabled. A semiconductor device further provided.   The semiconductor device according to claim 16, wherein the electrical connection means is a wiring connecting the antenna element and the semiconductor substrate, and is invalidated by being physically cut.   The electrical connection means is a depletion type nMOS transistor having a drain and a source connected to the antenna element and the semiconductor substrate, respectively, and the gate of the nMOS transistor is connected to a negative power supply. Semiconductor device.   The electrical connection means is a pMOS transistor whose source and drain are connected to the antenna element and the semiconductor substrate, respectively, and a voltage higher than a power supply voltage is supplied to the gate of the pMOS transistor. Semiconductor device.   The semiconductor device according to claim 16, wherein the antenna element is a pad. 20. The semiconductor device according to claim 16, further comprising: a lower layer pad portion, an upper layer pad portion, and a multi-layer structure pad having a plurality of contacts electrically connected therebetween. A semiconductor device that is a lower layer pad portion.

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